A Compact and Efficient FPGA Implementation of DES Algorithm

Saqib, N.A et al. In:International Conference on Reconfigurable Computing and FPGAs, Sept 2004

**ENG6090(4)**

Reconfigurable Computing Systems

References• Wilcox,D et al:A DES ASIC suitable for network encryption at 10Gbs

and beyond. In: CHESS 99• Patterson,C: High performance DES encryption in Virtex FPGA using

Jbits. In: Field programmable custom computing machines,FCCM’00 • Swankoski.E et al:A Parallel Architecture for Secure FPGA Symmetric

Encryption.In:18th International Parallel and Distributed Processing Symposium,2004

• Wollinger,T:How secure are FPGAs in Cryptographic applications. In:IACR,2003

• Stallings,W:Cryptography and NetworkSecurity:Principles and Practice. Prentice Hall

• Wong,K: A single chip implementation of DES algorithm. In:IEEE Globecomm Communication Conf.,Australia, 1998

• www.nist.gov

Outline

• Introduction to Cryptography

• Why Cryptographic Algorithms on FPGAs

• DES Algorithm

• DES ASIC Implementation

• DES Implementation using JBits

• DES Implementation on FPGAs

• Summary

Cryptography

• Process of transforming data,using keys, to protect its intelligence and unauthorized use

• Cryptography and tamper resistance hardware first used for military application

• ATM- the “killer application” which pushed technology into commercial mainstream

Cryptography cont’d..

• Technology advances have increased the number of embedded systems in various computing devices

• PDAs, GSM mobile phone identification etc have pushed towards low cost crypto-processors

• Security of data important for military and commercial applications

Cryptographic algorithms on FPGA

• Algorithm Agility-Can be reprogrammed easily for different application

• Changing Protocols-Algorithms can be updated, protocols can be changed as standards evolve

• Architecture efficiency-Implementations can be optimized for specific parameter set

Cryptographic algorithms on FPGA cont’d..

• Resource efficiency-Can use run time reconfiguration to configure only certain parts

• Throughput- Can offer higher throughputs as compared to CPU’s

• Development cost-Less design time, can be reprogrammed without additional time/cost penalty

Cryptographic algorithms on FPGA cont’d..

• Ease of experimenting with different architectures without long fabrication waits

• Unit cost is also not very significant

DES algorithm

• Data Encryption Standard is one of the commonly used block cipher algorithm

• It encrypts/decrypts 64-bit blocks using permutations and substitutions

• 64-bit key is passed through initial permutation to obtain a new 56-bit key

DES cont’d..

• 64-bit plaintext is permuted to get initial left half and right half of 32 bits

• Right half of first round is obtained by passing the text and keys through 16 rounds

• In each round, in the first step,permuted 32-bit right half is XORed with 48-bit subkey

DES cont’d..

• The 48-bit output of first stage is transformed into 32-bit by using 8 S-boxes

• In the last stage, this 32-bit result is permuted to right half of this stage

• This new right half becomes the left half for next iteration

DES cont’d..

DES Algorithm

DES Implementations

• Recent DES implementations

DES ASIC implementation

• Fully pipelined design thereby increasing the throughput

• 0.6 micron,105MHz,6.5Watts

DES Jbits implementation

• Hardware-Software approach allowing high speeds and throughput

• Sub-key generation moved to software

• Saves slices required for 48 XORs per round and key input IOBs

• Can be reconfigured at run time

• 0.22 micron, 168MHz, 3.2 Watts

DES Jbits implementation cont’d..

Single DES round (1)Unoptimized, (2)Optimized for Jbits implementation

DES on FGPA

• Implements parallel and pipelined approach

• Critical path delay is significantly reduced

• Sub-keys are pre computed and stored in memories

• The main difference in this approach is the parallel implementation of S-boxes

DES on FGPA cont’d..

DES implementation on FPGA

• Fixed permutations do not occupy much resources which can be implemented by changing wires

DES on FGPA cont’d..

• 64-bit input divided in RIN and LIN

• Before next clock cycle old right half is input to REGB and new left is input to REGA

• T/A factor is high indicating higher Mbits/s and less area used

Summary• Different applications need fast processing,

higher bandwidths, less area etc

• These constrained systems implemented on FPGAs for their obvious advantages

• Use parallelism and pipelining to maximize performance

• Critical path delay, area, power consumption are some of the important parameters to be optimized