A COMPARATOR AND TRACK AND HOLD FOR USE IN A 1 GS/s, 10 BIT ANALOG TO

DIGITAL CONVERTER

b~

Vasilis Papanikolaou

X t,hcsis submitted in conforrnity with the

requirenients for the degree of

Mater 's of Applied Science

C raduate Department

Electrical and Cornputer Engineering

University of Toronto

@Copyright by Vasilis Papanikolaou. 1999

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ABSTRACT

Data converters have become an integral electronic component since they are needed to interface

digital computing and signal processing electronics to the analog world. The rnonolit hic implernenta-

tion of high speed. and high resolution Analog to Digital (.a/ D) converters has been and will remain

to be important. The focus of tliis thesis is the design of a C'omparator and a Track and 1-Iold for

use in a L Giga-Sample per second (GS / s ) 10 bits A/D converter in a GaInP Heterojunction Bipolar

Transistor (HBT) process. Experimental results demonstrated that the coniparator was functional

iip to 3 GHz. .\ BER of 10-%v;ts measured with a I mV input signal. with d.c. otDet calibration.

The chip occupies -500 x 500 p n 2 of' active area with the core corn pnrator consurning 77 rnW from

a -6.5 V supply. Siniulation results of the track ancl hold indicate that 8.11 ENOB is achievable nt 2

G H z . with the rore track and hold circuitry dissipating 512 rnLV from a -8.0 and 4 . 5 V supply.

ACKNOWLEDGEMENTS

1 rvould like to thank Professor John Long for hiç guidance in the creation c.f this thesis. 1 would

also like to thank the engineers at 'lortel for their help with the testing of my comparator, a s well

as advice on the HBT proçess. .-Uso. 1 would like to thank my fellow students in E A 104 for rnaking

my graduate studies a experience to remember: the Olympic torch will continue to burn even after

E.-1105 is vacated. Finally. 1 want to thank my family and fricnds for their support over the pcwt

two years.

Contents

1 INTRODUCTION 2

2 HETEROJUNCTION B I P O L A R TRANSISTOR TECHNOLOGY 4

2.1 HOMOJLTNCr~lON VERSUS HETERO.JENCTIO'I TR:INSISTOR . . . . . . . . . -1

2 . 2 G.-ILLIUM .4 RSENIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 HBT PROCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3.1 TRAXSISTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ij

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 . 2 RESISTORS 8

2 . 3 . C=i\P.t\CITORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 ANALOG TO DIGITAL CONVERTERS 9

3 . 1 :!N:ILOG 'fO DIC1T:tL CONVERTER FIGLrRES OF JIERIT . . . . . . . . . . . . 9

3 . 2 :IN:ILOC 'r0 D1GIT:IL CONVERTER :\RCHITEC'TC'RES . . . . . . . . . . . . . 10

3.2.1 FL=\SFf +\N:\LOC;TOD[GIT:ILCOfiVERTER . . . . . . . . . . . . . . . . I I

. . . . . . . . . . . . . . . . . . . . . . . 2 2 INTERPOLATION AND FOLDI'IG L L

. . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2.2.1 1NTERPOL:ITION 1:'

3 . . 2.2 FOLDINC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 . 2 . INTERPOL.ATION ;\ND FOLDING . . . . . . . . . . . . . . . . . 1.5

. . . . . . . . . . . . . 3.2.3 PIPELINED .\ NALOG TO DIGITAL CONVERTER 16

. . . . . . . 2 4 TIME INTERLEAVED ANALOG TO D1GIT.AL CONVERTER 16

. . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 ARCHITECTURE SELECTION 17

4 COMPARATOR 18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 REGENERATTVE L.-t'T'CH 19

. . . . . . . . . . . . . . . . . . . 41.1 -4NALYSIS OF REGENERATIVE LATCH 19

. . . . . . . . . . . . 4.1.2 METASTABILITY IN THE REGENEWTIVE LATCH 21

. . . . . . . . . . . . . . . . 4.2 REGENEEWTIVE LATCH WlTH A PREAMPLIFIER 22

. . . . . . . . . . . . . . . . . . . . . 4.3 51.4STERSLAVEREGENEFUTTVE LATCH 23

CONTENTS i v

4.4 CIRCUITS REALIZATIONS OF COMPARATOR . . . . . . . . . . . . . . . . . . . 24

4.4.1 SIMPLE COMP.4R.ITOR CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.1.1 XOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.2 RECOVERY TIME .L tj

4.4.1.3 REGENERITION TIME . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4.1.4 COMPARISON RATE . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4.1.5 OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4.1.6 INPUT CXP:\CIT-INCE . . . . . . . . . . . . . . . . . . . . . . . . 27

.1..1.1.I POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 S

.!:L.1.8 COhIPLESfTY OR .-IRE.-! . . . . . . . . . . . . . . . . . . . . . . . 28

4 . 4 COMP.4R.ATOR CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

. . . . . . . . . . . . . . . . . . . . . .C.4.%. I Ci\SC.%DED COhIP.4R.4TOR 28

. . . . . . . . . . . . . . . . . 4.4.2.2 V.4 RI:\ B L E L3:I D CO M P:\ RAT0 R 29

4.4.2.3 COhI Pt\ RATOR WITH EMITTER FOL LOlVERS . . . . . . . . . :II)

5 C'Oh[P:\R:\TOR DESIGN A N D ESPERIhIENT:\L TESTIIIG . . . . . . . . . . . . :I 1

4.5.1 COMP.-IR:!TOR TOPOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.5.1.1 ;\.CIPLIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;l-l

4.5.1.2 C'LOCI; BEFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . :1-1

4.5.1.3 OUTPUT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5

4.5.1.4 CURRENT SOLrRCE . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.ij COMPLETE CIRCUIT AND LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7 SIMLTL.4TION AND ESPERiMENT:\L RESULTS - . - . . . . . . m . . . . . . . . . :IC

. . . . . . . . . 4.1.1 SINGLE E N D E D INPCT .-1 'iD C'LOCI; W.-\FER PROBING 38

.i.C.L.i OFFSET .4 ND SENSITIVITY . . . . . . . . . . . . . . . . . . . . . 38

4.7.L.2 RECOVERY :\ND REGENERATION TIME . . . . . . . . . . . . . 40

4.7.2 P.4CKXGED RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

. . . . . . . . . . . . . . . . . . . . . 4 . 7 . 1 OFFSETXNDSENSITIVITY 41

. . . . . . . . . . . . . 4.1.2.2 RECOVERY :\ND REGENER.4TION 'I'IhlE 42

4.8 BIT ERROR RATE RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.9 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -46

5 TRACK AND HOLD 52

5.1 SELECTION OF SWITCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2 ANALYSIS OF SIMPLE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

e 5 . 2 . 1 SLEW RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.2.2 SMALL SIGNAL BANDWrIDTH . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.2.3 HOLD MODE CAPACITTVE FEEDTHROUGH . . . . . . . . . . . . . . . . 57

CONTENTS v

15.2.4 DROOPR.4TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2.5 PEDESTAL ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2.6 =\PERTURECrNCERTXINTY . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.7 CONDITIONS REQUIRED FOR :IN OPEN SLVITCH . . . . . . . . . . . . 60

5.3 INPUT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3.1 DIFFEREIVTLAL P.-iIR WITH EMITTER DEGENER.4 TION . . . . . . . . tj2

5.3.2 DIODE LO.ADED D1FFERENTI:IL P.4IR . . . . . . . . . . . . . . . . . . . 65

5.4 SWITCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5 . 4 . DICI'FEREX'TI..\ L IJIPLE>IEYt':ITION OF .4 SJYITCJdED EJIITTER FOL-

LOCVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ti

5.4.2 SWITC'H DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 - - .î .;, OUTPUT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.5.1 DESIGN O F THE OUTPUT BUFFER . . . . . . . . . . . . . . . . . . . . . 71 - ' 5.6 C'LOCI? BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,.$

5. i i . L DESIGN O F C'LOCI< BCFFER . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 -.C . . . . . . . . . . . . . . . . . . . 5.6.1.1 ;IXXLYSIS OF C'LOCI\: BCFFER I ..> -- 5 .7 OUTPUT D R I V E R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i r

5.8 SIMCLXTION R. ESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

.5. 8.1 HOLD SETTLINC; TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s

. 5 . 2 .-\ C'QUISITION TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.8.3 PEDEST:IL ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8L

5.23.4 HOLD MODE FEEDTHROUGH . . . . . . . . . . . . . . . . . . . . . . . . . $ 1

5.8.5 DR0OPR.- \TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $2

. . . . . . . . . . . . . . . . . . . 5.23.6 DISTORTION NOISE AND SIN:\D/ENOB 83

5.9 'i'RACIL4ND HOLD LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

.10 SUhI>lARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6 FUTURE WORK AND CONCLUSIONS 90

ij.1 FUTURE WORIi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '30

6.l.L COMPARATOR . * . . . . - . . . . . - . . . . - . - . . . . . . . . - . . . . . '30

6.1.2 TRACK AND HOLD . + . . . . . . . - . . . . - . . - - - - . . . . - . . . . . 90

. . . . . . . . . . 6.1.2.1 TRACIi AivD HOLD SCVITCH IMPROVEMENT 91

. . . . . . . 6.1.2.2 TRACIi AND HOLD FEEDTHROLTGH REDUCTION 91

6.2 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

A APPENDIX A 93

A.1 PROBABILITY OF ERROR IN THE LATCH . . . . . . . . . . . . . . . . . . . . . 93

B APPENDIX B 95

B. l COMP.4RISON OF SINGLE TONE :\Y D TWO TONE THIRD ORDER DISTOR-

TlON COMPONEXTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

B.2 TR.ACI< X ND HOLD .\ND &I.-lSTER-SLAVE TR=\CI\: :\ND HOLD ANALYSIS . . '36

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2.1 EDEXL SXMPLER (36

B.2.2 TR.4CK.UD HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '-37

. . . . . . . . . . . . . . . . . . . . . B.-..< >l:\SrrERSL;iL:ETRXCI\: .-1 Y D tIOLD 99

List of Figures

1.1 Superheterodyne and Digital IF Receiver . . . . . . . . . . . . . . . . . . . . . . . . 3

'1.1 Simulatecl Characteristics of a. ii.5x.lPtn2 't'ransistor . . . . . . . . . . . . . . . . . . ij

2.2 HBT Cl~aracteristics of a 6.5 x 3prn' Transistor . . . . . . . . . . . . . . . . . . . . . 7

1 Ideal .A D C Iripu t-Ou tprit Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 :halog to Digital Corivcrter Static Errors . . . . . . . . . . . . . . . . . . . . . . . . 11

1 . 3 Flash A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Demonstration of InterpoIation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1 . 5 Esarripie of Interpolation in a Fkwh AD(-' . . . . . . . . . . . . . . . . . . . . . . . . 1-1

3 . A 4 Bit Flash .A nalug to Digital C'oriverter with Folcling . . . . . . . . . . . . . . . . 15

3.7 Pipelincd Analog to Digi ta1 C'onverter . . . . . . . . . . . . . . . . . . . . . . . . . l t j

4.1 Ideal Input-Output Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2 Block Diagram of Regetlerative Latçh . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3 First Order Mociel for the inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 'lormalized Differential Oritput Voltage Probability Distribution . . . . . . . . . . . 22

4.5 Regenerative Latch prcceded by a Limiting Preaniplifier . . . . . . . . . . . . . . . . 22

4.6 Preamplificr Transfer Characteristic and Input Signal PDF . . . . . . . . . . . . . . 23

-1 . 7 Master Slave Cornparntor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8 Simple Cornparator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.9 Cascaded Comparator Circuit Topology . . . . . . . . . . . . . . . . . . . . . . . . . 29

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Variable Loaded Comparator 30

. . . . . . . . . . . . . . . . . . . . . . . . 4.1 1 Simple Comparator with Einitter Follower 3 1

4-12 Amplifier used in the Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Clock Buffer 36

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Output Buffer 37

. . . . . . . . . . . . . . . . . . . . 4.15 Current Source Topology used in the Comparator 38

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 The Comparator Circuit 39

vii

... CIST OF FIGlrRES vl11

4.17 Test Setup for Single Ended on Wafer Probing . . . . . . . . . . . . . . . . . . . . .

4.18 Offset Voltage of Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 Test Sctup for the Packagecl Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.20 Phase relat. ionship between the clock (1 GHz) and input signal (500 MHz) . . . . . .

4.21 Offset and Sensitivity of the Packaged Comparator . . . . . . . . . . . . . . . . . . .

4.22 Test Setup for the Bit Error Rate Tests . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 BER Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-4.3 Sweeps of Design Variables to Maximize C'omparator Speed for Simple Coniparator .

1.25 Swccps of Design iJriablcs to 1Iaximizc i'uriiparntur S p e J for L'i~riiiLle (lu~tiparatùr

4-26 Sirndation and Esperimentnl Results for Recovery 'rime with a Single Enclccl Input

and Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.27 Layoiit of the Entire C'omparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 . 1 Block Diagram of a T'rack and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . 52

5.2 Track and Hold Signal LVavefornis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 .3 Switched Emitter Follower 55

5 . Single Enrlcd . Open Loop . Track and CIolcl Circuit . . . . . . . . . . . . . . . . . . . 55

5.5 Eqtiivalerit Xetwork R.cpresentntion nt the Hold C'crpacitor . . . . . . . . . . . . . . . 5t j - - .5 .(j Simple Model of Switch in Hold 5Locie . . . . . . . . . . . . . . . . . . . . . . . . . . t

. . 3 1 Feedthrough as a Function of Hofd Sapacitance . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Simple Mode[ for Pedestal Error

5.9 Quinn's Cascomp and hI ik i Differential Pair . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *5.10 Othcr Input Birffer C'irrwits

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 . l l Ernitter Degeneratiori

+5.1:! Input Buffer Lrtilized i r i tlie ïrack and i-iold . . . . . . . . . . . . . . . . . . . . . . .

5.13 Distortion of the input Uuffer as a Function of Bias Ciirrent and Emitter Degeneration

5 .hl Differential lmplementation of the Switchecf Emitter hllower . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 Single Ended View of the 'lew Switch

5 . if5 Capacitive Feedforward to Reduce Feedt hrougli . . . . . . . . . . . . . . . . . . . . .

5.17 Realization of Compensation Capacitors . . . . . . . . . . . . . . . . . . . . . . . . .

5.18 Switch used in the Track and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . .

5.19 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.20 Collecter and Emitter Voltage and Differential Base Current in Q1. Q2 of the Output

Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 .2 1 Current Source and Current Gain

5.32 Clock Buffer Utilized in the Track and Hold . . . . . . . . . . . . . . . . . . . . . . .

5.23 Mode1 of the Clock Buffer with a Positive Output Voltage . . . . . . . . . . . . . . .

LIST OF FlGURES

.5 .24 Output Driver used in the Track and Mold Circuit . . . . . . . . . . . . . . . . . . . 78

5.25 Hold Settling Time and Droop Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

. . . . . . . . . . 5.26 Error Voltage During the Acquisition Phase of the 'T'rack and Hold $0

5.27 Track and Hold Pedestal Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

.5 .28 Track and HoId Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $3

.5 .29 Track and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $8

5.N kfaster-Slave Track and tIolc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $8

5-31 Layout of Track and Hold and Master-Slave Track and Hold . . . . . . . . . . . . . 89

6.1 Improved Current Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . !Il

6.2 FeedthroughReduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B. l Ideal Sampler 07

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 Ideal Track anci Hold 07

B . 3 The Chnracteriziiig Furictions in a n ideal Track and Holci . . . . . . . . . . . . . . 98

B.4 [cical '[rack and tIold Circuit Followed by an Ideal Sampler . . . . . . . . . . . . . . $19

List of Tables

2.1 tiey Electrical Parnmeters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

. . . . . . 3.1 Summary of X / D Converter Specification for Radio Receiver .Ipplic.ations 12

. . . . . . . 3.2 Operations Occurring During the Clocking of thc a Step Pipclined ;\/D 17

4 .1 Design Goals for the Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2 Resistor Ratios usecl in the L'nriablc Loaci C'ornparator Topology . . . . . . . . . . . 33

4.3 Sunimary of Design C'hoices for the Clomparator . . . . . . . . . . . . . . . . . . . . 3-1

-1 .. 1 . lrldi tional C'ircui t Blocks iised in the (l'orriparator < 'ircriiit . . . . . . . . . . . . . . 3-1

4.5 Siimniary of the Experimental Serisitivity Results on the Packaged C'onipnrntor . . . I2

4.t; Surnmary of Regencration Tirrie hleasurenients . . . . . . . . . . . . . . . . . . . . . 43

4.7 Surrimary of Experimental Resul ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41;

Design C;oals for the Track anci tIolc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

coniparison on the use of Emitter Dcgeneration in a Differmtial Pair . . . . . . . . . (5.)

Siniulatcd fiold Settling 'Tirne as a Function of the [npiit Signal Airiplitucfe . . . . . 19

Sirnulateci Peclestal Error as a Function of the Input Signal Aniplitiide . . . . . . . . $ 1

. . . . . . . . . . . . . . . . . . . . . . Droop Rate 'as a Function of the Iripiit Signal 8-4

l'rack and Mold Distortion Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Distortion ïests 8.5

. . . . . . . . . . . . . . . . . . . . . . Summary of Track and Hold Figures of Merit 87

. . . . . . . . . . . . . . . . . . . . . . .. 1. 1 Signal to Xoise ratio needed for a givcn BER 94

Chapter 1

INTRODUCTION

For many years the dominant receiver architecture for radio coriirnunications li'w been the super-

heterodyne architecture. The primary disadvantngc of this architecture is that it needs nnalog

circuit blocks which are sensitive to operating temperatlire ancf power supply vol txge. Fiirt herrnore

the poor repeatxbility of annlog circuits. cornparecl to their digital coiinterparts. make it clifficult to

rt-icass rriariuf'act tire rnclios. In reccnt years. advarices in integrated c-irciii t ( iC) t,rc.hnology have niade

it foasihk to directly ciigitize an intermecliate frequency ( IF) . ï l i is radio arc-fiitectiire is reférreci t.o as

tfic Digital IF rrceiver[l. 2. 31. Throirgh t h e iisc of a wicleband .!nalog to Digital (.-l /D) converter,

the cliannel selection nnci clownçonversion are performed digitally tlirotigh t tw rise of a Programmable

Down C'onverter (PDC). This is nceded becnuse a Digital Signal Procfissor ( DSP) cfoes not have the

speecl to process the clnta at the same rates as the ;\ID converter (ADC). .-l digital IF architecture

;dlows thc sanie receiver to handle various wireless communication standards. This architecture is

also extreniely usefiil for base stations. where power dissipation is IPSS of a concern tlian in portable

~inits. In a typical superheterodyne basestation, analog front ends are recltiireci for each channe!.

This costly duplication is not necessary in a digital IF receiver. sirice the widebancf XDC digitizes

the entire band. There is also an increasing effort to elimiriate t8hc IF stage by performirig the A/D

conversion at the Radio Freqtiency ( R F ) input. crcating the software radioi[-!. 51. A block diagrani

of the superheterodyne receiver and of the Digital IF receiver are shown in Figure 1.1.

In addition to the drive to create a software radio, there is also a niovement torvards broadband

wireless communications. This is demonstrated through the allocation by the Canadian government,

of the Local Multipoint Communication Systems (LMCS) band' at 28CHz with a bandwidth of

.jOOiC[Hz[G]. The focus of this thesis is on the design of n comparator and track and hold for use

in a L Giga-Sample per Second ( G S / s ) 10 bit .-IDC in a G a h P Heterojunçtion Bipolar Transistor

'The t c m software radio is IooseIy defined as a radio in which a11 of the dawnconuersion. demodulation, and signal processing are done wit h software

In the United States the equiwlent is the Local Multi-Point Distribution Service (LhlDS)

(HBT) process. The comparator and track and Iiold were chosen as the circuit blocks to implement

since these are cornmon to rnany high speed data converters. Tlirough the design and esperimental

çharacterization of these circuit blocks an educzted decision on which ADC architecture to be used

can be made.

The next chapter of this thesis will discuss the IC technology iised for the design of the circuits.

Chapter Three will discuss the .-IDC, its figures of merit and some high performance architectures.

The results of the comparator and track ancf hold are describeci in Lhapters Four and Five. The

final chapter will summarize the results along witli siiggested improvements.

a) S liperhe tcrody nt. Recciver

MIXER BPF

1-0

b) Digital IF Rccciver

Sripcrhetcrodync and Digi ta1 IF Receiver

Chapter 2

HETEROJUNCTION BIPOLAR

TRANSISTOR TECHNOLOGY

'The Norte1 Heterojiinction Bipolar Transistor (HBT) proçcss is a high spccri ( ;alri P te(-hnology. A

bricf look will be taken at the standard homojunction transistor and sortie of the important design

eqlintions for them. The Iimitatioris of hornojiinction technology is t lie motivation for the use of ;t

heteroj unction structure. w here stiperior performance (.an be actiiev~rl. 'This is followerl by n look nt

t. ht. transistor. resistor and cxpac-i tor avrrilablc in t h e process.

2.1 HOMO JUNCTION VERSUS HETEROJUNCTION TRAN-

SISTOR

This section will outline the key ciifferences between homojunction and heterojiinction bipolar tran-

sistors. The niaterial presented is not intended to be al1 encorripusing in t h e area of device ptiysics,

and it is assumed that the reader is familiar with the fiindarncntals.

The vast majority of today's bipolar transistors are basecl on p-n junctions wfiicii have the same

base material and energy gap; that is a homojunction. In a bipolar transistor, one of the key

parameters is the current gain. 3. [n order to increase the current gain. the base width must be

rninimized JO that base recombinat ion current is minimized. Furthermore, the eniit ter doping levei

should be much larger than that of the base in order to maximize the ratio OC forward to back

injected current. Tlie current gain can be written as[i]:

where NE and NB represent the emitter and base doping levels respectively. This demonstrates that

:VE should be greater than -YB for a high current gain. Tlius, the homojunction transistor designer

does not have the freedorn to independently select the doping levels. To minimize the series base

resistance ( f b b l ) . which is a major source of noise in analog circuits, the doping level in the base is

increased. Furtherrnore, to minimize the base-emitter capacitance. the eniitter doping level should

be decreased [ f ] . Through the use of a base-emitter heterostructure. the designer has more flexibility in selecting

the doping levels. X heterostructure is formed between by trvo materials that have different energy

bandgaps. it can be s h o w that the ratio of collecter to b,ae diffusion coefficients in a ff BT structure

is given by [il:

rvherc AEq is the energy handgap difference of the two materials. The prcsence of the esponentiai

in equaiion 2.2 provicles the clesignw sotrie tlexibility in selecting the hase anci eniitter duping levels.

'fliis allows the clesisner to optimize the base and emitter regiotis t'or a low base resistanrc and

jiinction capacitance withoiit compromising the current gain. 'This. in corij unction with the use

of n semi-insulating rnaterial such as Ga.-1s. make III-V tIBT proccsses icienl for higli freqiiency

applications.

2.2 GALLIUM ARSENIDE

From n pure speecl perspective, gallium arsenicle (C;a:is) is a siipcrior rnaterial to use L'or the fnbri-

cation of transistors due its higher mobility. Also, since Ga.-1s is a senii-insulating seniiconcfuctor.

parasitic capacitances to the substrate are minimized. rvhich facilitates the design ot' Iiigli frcquency

crrcuits.

Lrnfortunately, GaAs hm otlier characteristics wtiich are inferior to Silicon (Si). Silicon has a

liigber thermal concluctivity than GaAs (0.46 vs 1.5 W/crn-OC;). This. in corljunction with the higher

power dissipation ty pical of G a . 4 ~ transistors causes pro blems w hen integrat ing a large num ber of

cievices demanded by modern digital circuits. This is important for an X / D since it reqirires many

transistors. From a n economic standpoint. Cahs tecfinology has been limited to high performance

circuits and has not been able to overtake Si as the dominant rriaterial of use due to yield and

reliability issues[8].

2.3 HBT PROCESS

The rernainder of this chapter will focus on the HBT process utilized. The characteristics of the

transistors will be presented followed by a short discussion on the passive elements available.

CHA PTER 2. HETEROJC~iVCTlON BIPOL -4 R TRANSISTOR TECHNO L OG Y

2.3.1 TRANSISTORS

The Heterojunction Bipolar transistors have a maximum transit frequency (/,) and maximum oscil-

lation frequency (f,,,) of 30 GHz and 100 GHz respectivcly. The heterojunction is fornied between

the base-emitter junction with a CaXs and GaInP layer. Figures 2.1. 2.2. and Table 2.1 sumrnarize

some of the transistor's electriçai cliaracteristics.

a) 1-V Chilracteristic b) Gummel Plot

Figure 2.1: Simulated Cliaracteristics of a 6 . 5 ~ :jPrn2 Transistor

An interesting characteristic of the III-V HBT transistors is that they exhibit a negative differ-

ential resistance ( N D R ) as I/CE increases. This becomes more prevalent as the current increases and

it is in stark contrast to a Si hornojunction transistor, where the collecter current increases with

CfCE and thus exhibits a positive output resistance. In a hornojunction transistor. where the base

is doped lightly in order to increase the current gain, the transistor exhibits the Early effect. The

Early effect refers to the modulation of the base width due to the variation of the base depletion

region wi t h the collector-emit ter voltage[9]. In a heterojunction transistor, the base is doped much

CHAPTER 2. HETEROJLWCTION BIPOLAR TR4NSISTOR TECHNOLOGY

Figure 2.2: CIBT Characteristics of a 6.5 x :jPrn2 Transis, or

Table 2.1 : Key Electrical Parameters

higlier than the collector in order to minimize the extrinsic base resistance. Since the base is doped

more than the collector. the depletion region does not extend iar into the base region and therefore

changes in the base width are negligible. The dominant factor cletermining the collector current

versus L>E characteristic is the decrease in the current gain as the power dissipation increases due

to self heating[ï]. As a result of the poor thermal conditctivity of GaAs, the transistors operate at

a higher junction temperature than their Si based counterparts and are niore prone to the thermal

degradation of their current gain.

Another peculiar characteristic of the HBT concerns the maximum transit frequency. In a typical

homojunction transistor, fi increases as the collecter-emitter voltage increases. The Early effect is

also responsibIe for this. .As the collecter-emitter voltage increases. the decrease in base thickness

also decreases the base transit time. one of the dominant time constants in a siIicon homojunction

transistor. Thus the speed of the device increases with the power consumption. In an HBT the

reverse is true; the transit frequency increases with a decreasing collecter-emitter voltage. or as the

CH-4 PTER 2. HETEROJUiVC'TlON BIPOL-4 R TR-LVSISTOR TECHNO LOG Y 8

power dissipation of the transistor decreases. The dominant tirne constant in a III-V HBT is the

collector depletion region transit time[7]. The base transit time is negligible because of the high

electron mobility in GaAs which significantiy reduces the base transit tirne. -4s a result. the total

transit time is strongly dependent on the deplet ion region's transit time. Thus, a s CCE increases, so

does the collector space-charge region width. and rvith it the transit time. The reiationship between

JI and VcE is an extremely important distinction between a Si homojunction transistor and a III-V

LIST and leads to sorne interesting design decisions. To rnaxirnize the speed of a single transistor.

the coliector-ernitter voltage of the HBT should be decreased. which is at the expense of linearity

arici voltage swing at the collector. rhese parameters are important in a high speed linear amplifier,

or a buffer with a large dynarnic range.

2.3.2 RESISTORS

The resistor available t.o the designer are NiCr. with a low shect resistivity. ïhesc resistors are

better suited for high frequençy applications than a ciiffuseci resistor bccarise of their Iower parasitic

capacitance, tliermai stabili ty and low process tolerance. The presençe of rr parasi tic capacitance

netessitates rr design compromise between acctiracy and frequcncy of operation. A large resistor

(i.e.. large area) is neecleci in order to minimize the effeçt of Iithographic variations[ 101, whereas the

opposite is triie for maximizing its ilsable frcquency of operntion CU a resistor. At tiigti frequeriçies

the resistor will begin to appcar ,as a cczpacitor. which has dcleterious effects. As an csample of how

this coiilci affect rr design. oonsider the use of resistive degeneration in the emitter for stabilization.

At high frequencies the resistor appears capacitive and woiild be transformeci to a negative resistance

in the ba;ie[ll]. This causes instabilities and limits the usefiilness of the circuit at high frequencies.

The bandwidth of the thin film resistor allows the designer greater Hexibility in designing a high

frequency circuit, while still rnaintaining accuracy.

2.3.3 CAPACITORS

Cnpacitors in the process are realized as reverse bias pn junctions and as .Cletal Insulator Metal

(MIM) Capacitors. It is desirable to use MIM capacitors since p-n junction capacitors are highly

non-linear, inaccurate and have a low hreakdown voltage. X p-n junction could be used when a large

capacitor is needed since it has a large capacitance per unit area. The MIM capacitors available

in the HBT process are rnodeled as having an infinite Q. This can be attributed to the use of an

excellent conductor for the plates. and the use of a semi-insulating substrate.

Chapter 3

ANALOG TO DIGITAL

CONVERTERS

The Analog to Digital Converter is needed to interface digital electronic systerris ta the rinalog world.

This chapter will discuss chta converters a t t he systeni level. Ttieir figures of merit ,as well as the

popular high performance ADC' nrchitccturcs will bc esarriinccl.

3.1 ANALOG TO DIGITAL CONVERTER FIGURES OF

MERIT

The Analog to Digital converter maps the analog input signal rrppearing at its input terminais to a

digitai value a t its outpiit. The Input-Oiitpiit relntionship of an ideal data ronvertcrl is sliorvn in

Figure 3.1.

The resolution of the converter is given by the step size 1, where

where ~ E F represents the full scale input range of the converter and B represents the number of

bits of resolution. The h / D converter output is an approximation to the original analog input signal.

The difrerence betiveen the original signal and the digitized output is referred to as the quantization

noise. The mean-square quantization noise power for a uniformly distributed input signal betrveen

f ;1/2 is given by[13]:

'The Input-Output characteristic shown is that of Midriser Bipolar curve. For other curves refer to [12]

Digital Word 4

Figure 3.1: icleal XDC' Input-Output Rrtlationship

N'ith n fi111 scale input signal of C.REF, the signal to ciurintizrition noise ratio can be written

'as[ LI]:

T h e arc rriany Figures of Merit for an ADC. Some of the static perfarmancc metrics are:

i ) Offset: The vertical ( y ) intercept of the converter transfer rcsponse.

i i ) Differential Yonlinearity : ï h e maximum deviation of the step size frorti the icical value of A.

i i i ) [ntcgral Nonlinearity: The maximum deviatioti of the A/D Input-Output Relritionship from a

a straight Iine pacised through the endpoints of the converter's transfer response.

.-\ figure depicting graphically the above mentioned errors is shown in Figure 3.2. For more

information on static performance metrics refer to [13].

In addition to the static performance characteristics OC an .-\/D converter. the dynamic per-

formance is also important. Some of the dynamic characteristics of an . l / D converter that are

important in a radio receiver are summarized in Table 3.1[15. 161.

3.2 ANALOG TO DIGITAL CONVERTER ARCHITEC-

TURES

In ciesigning an Anaiog to Digital Converter, the designer is presented with many architectures frorn

which to choose from. This section will lirnit the discussion to high speed Nyquist data converters.

Digi ta1 Word

/ Offset - ,Analog -

Figure 3.2: Xnaloç to Digital Convertrr Stntic Errors

3.2.1 FLASH ANALOG TO DIGITAL CONVERTER

T h e flash =\/D converter is the sirnplcst. most direct. and fastest possible rirctiitectirre. A diagrarn

of tliis architecture is shown in Figure 3.3.

In a Hash .-\DC w i t h a rnidriser bipolar curve. 2" comparators and resistors' arc needed. Tlius.

tlie major limitation of fImh data converters is the esponential growth in cornplesity nncl power with

the nttrnber of bits. B. This preciucies the use of n. Fl'ash A/D for rcsolutions greater tlian 8 bits. It

is important to note that tlie Flash arctiitectiirc does not necessarily need a Track and ~ o l d . ' but

in high performance A/D converters it is typically used.

3.2.2 INTERPOLATION AND FOLDING

The main drawback of Flash A/D converters is their exponential increase in cornplesity with reso-

lution. The use of interpolation or folding, or a combination of the two, attempts to overcorne this

limitation.

-

'For a rnidtread characteristic .ls + 1 3The Track and Hold will be discussed in depth in Chaptcr 5

Table 3.1: Sumrnary of A/D Converter S~ecification for Radio Receiver .-ipplications

3.2.3.1 INTERPOLATION

Spec ifica t on Signa1 to and Distortion Ratio (SINAD)

l i i th in every cornparator of the flash arcliitecture there is a prearnplifier and a regenerative Intch.

The use of interpolation reciiices the number of preamplifiers usccl in a c h t a corivcrter. by sharing

the preamplifiers aniongst the latcties. 'The concept of interpolation is best illustratcci through the

lise of ari example. C'onsider the system showri in Figure 3 . - I whcre the resistors arc. part of n resistor

lndcler wliich sets the reference voltage for rach of t>he prearriplifiers. At thp voltage l i s r (Figure

3 .4 ) . it cran be shown that[l-l]:

Definltion 51 na ower

Quanti;atron .k Thermd?Vo:rr P v w r r + Dts ior t i rn Power

Ftirthermore. using the relation:

it can be shown that:

This last relation demonstrates that through the clever use of the prearnplifier's outputs. the

resolution has increased by a factor of two. while using half the number of preamplifiers. In the

literature, this is referred to as an interpolation factor of two. The nurnber of prearnplifiers that are

needed can be written as:

P .Vurnber of Prearnpli fiers = -

I

wliere 1 is the interpolation factor. .-1 diagram dernonstrating the use of this twhnique is shown

in Figure 3.5. The concept of interpolation Tan be extendcd further through the use of a resistor

string between two preamplifiers. Through the use of the resistor string, ttie interpolation factor ha

increued and hence the number of preamplifiers and complesity of the data converter tias ciecreased.

The interpolation crin not be increased without bounci, since as the number of resistors in the resistor

string increases, so does the response time of the regenerative latch.

3.2.3.3 FOLDING

The underfying reason for using a folding architecture is to reduce the esponential increase in the

number of Iatches with increasing resolution. This is done tiirough the use of analog preprocessing,

which allows the X/D converter to be split into coarse digitization and fine digitization. otherwise

known a s the Most Significant Bits (MSB) and Least Significant Bits (LSB). . l n example of a 4 bit

FIash A/D converter utilizing folding is shown in Figure 3.6[1q.

The MSB XDC in Figure 3.6 is used to determine which of the four regions (i.e..(-lm,-L/4).

(- l/4,O) ,(O. 1/4) ,( l/Lx))) the input signal is in. It provides coarse digitization. In order to obtain

finer resolution. the LSB section is added. The least significant bits are deierrnined by four latches

CHAPTER 3. .*LV.4 LOG TO DIGIT4 L COiWERTERS

Output . . . . . . . . . . . . . . . vom

* Input '.

- - L -.-----

' K A v!n JK+

Figure 3.4: Demonstration of Interpolation

Figure 3.5: Example of Interpolation in a Flash ADCI'

and folding blocks. The operation of the LSB section is best illustrateci through the tise of an

example. Consider the binary logic tevels at I; to CIi, as b,v increases frorn (-*x.-l/-1). 'The

output of the latches would be 0000,0001.001 1.0111,1111. In a similar rnanner. the output woutd

be 1110,1100,1000,0000 as the input signal traversed the region (-L/-1.0). Thc folding block's unique

input-output relationship allows for the reuse of the sarne four latches. since it lias four zero crossings

in the entire voltage range of the ADC. This causes the latches to change frorn O and 1 four times.

and thus the output signal folds back on itself. The latch in this example is equivalent to 4 latches

in a a ffash ADC. This factor of 4 difference is know as the folding factor[l3]. In general, the number

of latches needed when folding is used can be written as:

FOLDtNG BLOCK LATCH

-7116 -3116 1/16 5116

Figure 3.6: A 4 Bit Flash Analog to Digital (-'onvcrter with Folding

where F is the folding factor. Knt'ort~inatcly. the nonlinear riat.ure of c7 practicd folding block

introducc errors arid thus the iisefiilness of folding is limitcd to lcss than 8 bits[l-LI. Forthermore. for

one cycle of the input signal. the output signal of the folding block undergocs four cycles (e.g. Four

cycles as in Figurer 3.6) , and thus the folding block must be able to handle tliese high frequencies.

3.2.2.3 INTERPOLATION AND FOLDING

In order to decrease the complexity and power consumption of the flash converter further, the de-

signer can use the interpolation and folding techniques in conjunction with each other. Interpolation

between the foiding blocks can be used to reduce the number of these blocks needed. InterpoIation

decreases the number of folding block by the interpolation factor. and the nurnber of latches de-

creases by the folding factor. Thus, combining the two techniques has significant complexity and

power savings. The use of interpolation and folding is limited in the manner outlined in the previous

two sections, and thus its advantages have a practical limit.

CH.4PTER 3. -AN-A LOG 7'0 DIGIT4L CONVERTERS

3.2.3 PIPELINED ANALOG TO DIGITAL CONVERTER

In the Hâsh architecture masimiim speed is achieved because it is a simple two-step conversion

(i.e.. sample and quantize) process. This simplicity is achievecf a t the cost of complexity and power.

Folding and interpolation techniques reduce the hardware cornplexity to a certain extent. but there is

a practical limit to the folding and interpolation rate. The pipelined architecture has a linear increase

in complesity a=; the resoiution increases, a t the cost of a greater reliance o n high performance analog

circuits. .A block diagram of a two step pipelined architecture is shown in Figure 3.7.

CLK CLK

l

i + SISB LSB

Figure 3.7: Pipelined Analog to Digital (.'onverter

tn the two step pipelined system. t h fi rst stage performs a coarse qunntization on the input

signai. nncl t hen throtigh t h use of ri Digital tu :\rialog C'onvcrter [ D:lC'), Siibtrrictor and Aniplificr.

n resicluc signal is created for tlie fine qiinntization in t l ie secotir1 stase. The miplifier is not necessary.

but it cases the sensitivity and speed rcqiiircrnerits of the coniparator. In qcnrral, t h pipelined

arcliitccture can he k stages long, witli each stage tiaving a resotiition of .llk bits for an overall

system resoliition of . I lK. An esample of the clocking schenie used for a two stage pipelined

architecture. and the various operations that are reqiiired. are shown in Table 3.2. As can be seen,

two step conversion is possible. but within cadi dock cycle the pulse wicfth miist be large enough

to accommoclate al1 of the operations and their associateci scttling tirnes. This is in stark contrast

to the F l c ~ l i ADC. wfiere only sarnpling aricf qtiaiitization needs to be done. This, the! pipelined

architecture is slower. Another disadvantage is that two liigh performance track and hold circuits are

needed. which can be very power hungry, and each analog element fi.e. subtractor. DAC, Amplifier)

needs a dynamic range that is ccnsistent with the overall system resotution.

3.2.4 TILME INTERLEAVED ANALOG TO DIGITAL CONVERTER

The time interleaved analog to digital converter has the potential to achieve estremely fast sampling

rates. This is achieved by multiplexing the output of i21 X / D converters in parallei, each operating

a t a. sampling rate of Is/!CI, where J, is the overall sampling rate. Mthough this architecture can

achieve high conversion rates, interleaved architectures are limited in the resolution that they can

achieve due to mismatches between the .A/D converters[l4].

CHA PTER 3. AN-4 LOG TO DIGIT4 L CONVERTERS

Table 3.2: Operations Occurririg During the Clocking of the a Step Pipelined .-\/D

3.2.5 ARCHITECTURE SELECTION

Positive Clock Cgcle

TktI 1 in Hotd mode TkH 2 in T'rack mode

hl Bit X/D Quantization Digital to Analog Conversion

Subtraction

In orcler to create a LO bit ADC. some architectures are prcçliidecl. [t is not possible to lise a

siniple flash architecture due to the complexity and power consimption of such a design. Due to

riiisrriatches between the A / D converters. the tirne interleaved architecture is a n inipractical archi-

tecture. The most promising architectures are the pipelined as well 'as the fdclinç and interpolation

t l~asl i nrrhitectiirc. In order to cleterrnine which architecture to piirsiie for t,he ir~tcnrlecf application,

the Track and Hold and C'ornparator, which are cortirnori blocks to botti architecttires. were desigrieci

and fribricatetl.

.Vegative Clock Cycle

TSrH I in Track Mode TS: H 2 in Hold Mode

Y Bit X / D Quantization

Chapter 4

COMPARATOR

ï h e purpose of the comparator is to prodiice a binary vali~e accorclirig to wtiether n signal is greater

t8han or srria!ler than a reference value. .As a specific example. if the referenw value is I ;,! then the

coiriparator wo~ild output a binary value of ! if clic signal of intrrest is grenter tliari otherwise

the output would be a, binary 0. The ideal input-output relationship is shown in Figure 4.1.

:- Input

Figiire 4.1: Ideal input-Output Relationstiip

I t is possible to utilize a hi& gain limiting amplifier ris a comparator since its transfer curve

approximates the ideal comparator characteristic[l3]. To simultaneously achieve high resolution

and speed, one needs to use a regenerative latch which utilizes positive feedback to attain its speed.

Some common metrics used to characterize the performance of a comparator are:

i ) Resolution/Sensitivity: The minimum input signal for which the comparator consistentlyt

has a valid digital value at its output.

ii) Recovery Time: The time needed for the comparator to switch irom the latch to the track

state.

'In order to quantity consistent, one needs to place a lirnit on the Bit Error Rate (BER)

iii) Regeneration Time: The time needed by the comparator to reach a binary output value for

a given input signal.

iv) Cornparison Rate: The maximum cemparator dock frequency. [t is limited by the recovery

or regeneration time.

v ) Offset: The offset due to random mismatches.

vi) Input Capacitance: The total input capacitance of t h e cornparator.

vii) Power

viii) Couiplexity/Area

4.1 REGENERATIVE LATCH

'The regellerative lntch consists of two back to back inverters. This simple circuit relies on positive

feedback to resolve smclll sigrials qiiickly. Ttic analysis that hllows rtssumes t h t the inverters can

be approsimated as first orcier systerns.

4.1.1 ANALYSE OF REGENERATIVE LATCH

.-1 simplifieci diagram of the rcgenerative latcli is shown in Figure -1.2.

Figure -1.2: Blacli Diagram of Rcgenerative Latch

For the purposes of this analysis it will be assumed that the inverters can be approxirnated as

f i rs t order systerns. with a small signal time constant r o and low frequency gain -Ao. .-lkm, it is

assumed that the inverters are initially operating in the linear region[l3].

CK4PTER 4 - COL\¶ P--\R-4TO R 2 O

Given these approximations. the individual inverten can be represented by the circuit shown in

Figure 4.3. From Kirchoff's Voltage Law ( K V L ) :

Figure -1.3: First Order Mode1 for the i n v e r t e r s

+

out

d - - - \ ( ~ ~ ' i n ( 1 ) = ~ ' , I , ' t ( t j + ~ g - ~ o u t ( l )

21

Using equation 4.2. the system of e q u a t i o n s that describes thc bnck to bnck invertrrs arc:

Su btracting equation -1.4 frorn -L.:l.

Let the initial voltage difference across the latch be given by (soucm - c,,,tp)lt=u = P.^^,,, and let

tioUt = v,,c, - Uour, [t follow~ tliat:

Let I/o,t,,,,, be the logic level needed to drive the succeeding digital logic. The time, t ~ o c r c

CH-4 PTER 4. COMP--\R.4 TOR

that is rcquired to rise from L ~ , , ~ , to CouI ,,,,, is:

Equation 4.9 shows that the time ( tLocrc) required to rcach Z ~ r ~ T r o G r c ciepencis on the unity

gain bandwidth. Furtherrnore. t'or srnaIl initial voltages (u,,~,,). ~ o c . 1 ~ niay esceed lialf a dock

cycle. This is referred to as rnetastability. and its probability of occurrence stioulcl be minimized.

4.1.2 METASTABILITY IN THE REGENERATIVE LATCH

Comparators have the undesirable characteristic that for mal1 signals the comparator will not latch

to the correct digital value before the nest clock cycle; this is referred to ns metnstnbility. This

section ticscribes the probability of failiire for n comparator based on a first orcler annlysis[l-l].

Ttic assumptions and variables used in the nnalysis are:

i ) I ',,,,t ,,,,, is the output loçic Icvel.

i i ) t.,,,,t,, is the initial clifferential voltage across t h e Intch's tcrminals. [ t is assumerl to be n

iiniformly ciistributed rnncloni variable Crorn i l:,,,fLOcïrc. +

i i i ) Tlie dock period is ?K. and tliercforc the compnrator is givcn 'K. to rerich n valid cfiçitnl valiie.

The comparator is rrsstirncd to be in a be metastable wlien t ~ c ) ~ r c . > Tc. Tlicreforc the proba-

hility of a failure occurring becnitse VcIcT < I & ~ r t o , ; , c at Tc is:

Siibstituting equation 4.9 into equation -1.10:

In equatian 4.13, u,,,; represents the output voltage norrnalized to Ii..~,,,,,. The distribution

of the normalized output voltnage is shown in Figure 4.4. Therefore to solve the probability of error

(P.) the area under /,:ut ' within f e (- *") , must be deterrnined.

'The probability density function (pdf) of the norrnalized output voltage.

Figure -4.4: ?Jormalized Differential Output Voltage Probability Distrihutioii

Equation -1.15 derrionstrates that in orcler to niinimize the probability of error in n comparator.

one miist design the systeni to ninsimize (.-\il - \ ) / r i , . or eqiiivalently the 1init.y gain handwidth given

by - 4 0 ~ 3 d ~

4.2 REGENERATIVE LATCH WITH A PREAMPLIFIER

I I I the prcvious sections it fiLas been aminicd t h . the i n p u t to the comparator is ri iiniformly

distributcd random variable. .-Issurning that the input to the h i tins amplifier is a iiniformly

distribiited randorn variable, the outpiit of the liniiting amplifier is not becaiise of its nonlinear

transfer cliaracteristic[li]. Hcnce the nnalysis presented in the previous section is no longer vdid.

Figure 4.5: Regenerative Latch preceded by a Limiting Preamplifier

Vout

The system shown in Figure 4.5 lias two modes of operation: track and latch. During the track

state the preamplifier is operating and the latch is off. while in the latch state, the reverse is true.

REGENERATiVE LATCW

Trac k 7- Latch

Since the input signal to the latch is now preceded by a limiting amplifier the input to the Latch

is no longer a uniforrnly distributed randorn variable. In order to determine the probability of

rnetastability. it will assumed that the preamplifier transfer characteristic and input signal pdf are

,as shown in Figure 4.6.

I I

I 1 'Input

, y 1 - Vout

Figure 4.8: Prenniplifier Transfer C'harscteristic rtriti Iriput Signal P D F

Tlie probability of error for tliis system is:

Lomparingequation 4.1.5 with -I.ltj it is cvident that the prearnplifier's gain decreases tlic nietasta-

bility, but the unity gain bandwidth is the dominant factor.

4.3 MASTER SLAVE REGENERATIVE LATCH

The rnetastability of the latch alone. and that of the prearnplifier-lat,ch systern h a been reviewed.

The probability of error. due to a metastable event is rninimized by masimizing ttic unity gain

bandwidth in both cases. but for the preamplifier-Iatch system the probability of error was decreased

slightly by the gain (-4,) of the preamplifier. The rnetastability can be decreased significzintly through

the use of a master-slave regenerative latch. T h e master-slave latch is shown in Figure 4.7.

Wittiin each of the comparator blocks shown in Figure 4-7, is the system shown Figure 4.5. To

simplify the andysis of master-slave architecture i t wilI be assurneci tha t the preamplifiers have a

negligible effect3 and that each of the comparators are identical.

3 ~ s was shown in equatian 4.16 the gain has a small effect on the probability of error.

CLOCK CLOCK

in *

Figure 4.7: 51czster Slave Comparator

I t can be s h o w that the probability of error is given by:

t t out

Compamtor#l A

[n comparing -1.17 with -I.1+5 the probability of error in the niraster-slaw ;~rcliitecture is a factor

r ( - ' ' ' '~~: . ' ' T c ) less than tlint of the siiigle corriparator. nt the cost of i n c r e ~ d coriiplcxity. power and

Compantor #2

The rn=ster-slave architecture leads to sonie interesting design possibilitics. instead of designing

one comparator that consumes n lot of power it may be better to lise n master-slave architecture that

uses two comparators. eaçb with half the bandwidth. and less than half the power. In ri ninstcr-slave

design the two comparators need not be identical. 'The measter c.oiild use larger trarisistors. ancl

thus have a srrialler offset, but (ronsiime more power. 'The slave. co~ilcl have srriallcr t.ransistors, and

consume less power. sirice offset is not as important.

In conclusion. throiigh the use of a niaster-slave architecture there is triorit design fle'cibility to

rcach the desired probability of error in the system. at the cost of increrisecl complesity.

4.4 CIRCUITS REALIZATIONS OF COMPARATOR

ï l ius far. this chapter lias focuseci on a theoretical analysis of the regenerative 1atcI.t. 'i'hc rest of

tiiis chapter will discuss various corn parator topologies. t heir advantages and disacivantages. as well

CU a tliscussion of the comparator that was designed and testeci.

4.4.1 SIMPLE COMPARATOR CIRCUIT

A simple circuit that acts as a comparator is shown in Figure 4.8. The preamplifier is implemented

with transistors Q I , Q2 and resistors Rcl and RC2. The regenerative latch is realized by cross-

coupled transistors Q3. Q4 and resistors Rci and Rc2. This circuit is a direct realization of the

preamplifier-latch block diagram shown in Figure 4.5. Transistors Q5 and Q6 irnplernent a current

switching differentia1 pair under the control of the ctock signals. The current switch controls which

CHAPTER 4. COMP-4RATOR 2 5

state (track or latcli) the cornparator is in. This cornparator circuit will be used to illustrate how

the design parameters inHuence the various figures of merit described in the introduction.

Figure -1.8: Simple Comparator Circuit

4.4.1.1 NOISE

The minimum resoltition of the comparator is liniited by ttie noise and offset. This section will

focus on noise. and the offset will be discussed in a later section. The noise is important since

the corriparator can not accurately resolve a signal that is buried in noise. The effect of noise on a

comparator, and its ability to consistently latch to the correct value is discussed further in Appendix

A. 1.

The input referred noise spectral density applies to linear circuits but the comparator has two

states: track (linear) and latch (nonlinear). The limitation on the resohtion of the latch is the noise

that is introduced into the system when it is in the track state. The noise spectral density appearing

at the input of' the simple comparator is[L4]:

where k. T. and y, rcpresent Boltzmann's constant (13.8 x L O - ~ ~ . / / I ~ ) , operatine; temperature and

the transconductance of the transistors. The resistors rbbl and rr,l represents the estrinsic series

base and emitter resistances of Q 1 and Q2, In order to rninirnize noise. equation -1. Id preciicts a large

transistor, biased a t a high ciirrent shoiild be iised in order to niinimize the estrinsic resistances,

and to masirnize the transistor's t,ransconcliict,anc.e. Fi~rt herniore. t he I(md res is tm ( R,:! .;lio~~ld he

increased iri order to niaximize the gain.

4.4.1 .S RECOVERY TIME

'The comparator switches between the track sncl latch mocles o l operation. tn orcier to determine

t,he recovery time of ttic cornparator the overdrive test is iised[l-1). 'This test applies n large negative

(or positive) input signal to the prcarnplificr. whcn there is positive (or negative) outpiit tliiring the

lattrh rnode. In order to operate correctly. the preamplifier nii~st b~ able to recovcr to n. negntive (or

positive) voltage before the latch is strobeci itgain.

.-issurning that the preamplifier can be accurately niodeleri w i t h tinie coristarit r . the recovery

rinie is shown to bc [[SI:

Eqiiation -1.19 cienionstrates that in order to riiinimizc the rermvery tinie. the tirne time con-

stant ( r ) must be minimized. :\ssriming that the estrinsic resistances (i.e.. rbbl. r C e r . and r , , ~ ) are

negligible. a n d using the Miller efkct. the time constant of :L differentinl pair is shown to be[8]:

Equation 4.20 demonstrates the delicate interplay of the various design parameters and d.c.

operating point. From equation 4.20, it can be seen that to rninirnize the time constant, the input

and toad resistance needs to be minimized. The selection of the bias current is difficuit since ft and

the gain are dependent on the bias current. Assuming that the Miller capacitance is negligible (i-e.,

the gain of the preamp is srnall), the value of C, can be minimized without concern of C,. In the

MBT. fi monotonically increases with current density. Thus, to masimize the speed of the amplifier,

the bias current should De increased to the maximum current density rating of the transistor. T h e

transistor size is selected to minimize C, and C,, but care rnust be taken since the extrinsic series

resistors may limit the bandwidth and noise performance of the circuit.

4.4.1.3 REGENERATION TIME

Tlie time needed by the regenerative latch to reach a valid logic level for a given initial voltage w~as

given in equation 4.9. The low frequency gain and srnail signal time constant can be approximated

b~

The sclection of the bias point and circuit parameters to mirlin~ize the rcgeneration tiri-ie is similar

t,o those uscd for the recovery tiiiie.

4.4.1.4 COMPARISON RATE

Tlie mnsimurnclock Srequcncy is lirnited by the recovery or regeneratiori tiriie. Tliererore lie rlesigner

shoulcl concentrate on botli figures of merit.

4 . 4 5 OFFSET

:1ny offsct that ocrcurs at the input terminals of the preamplificr will clecrease the sensitivity of the

coniparator. Both systematic and randorri offset can occilr in ;~ny miplifier. For cl balancecl circuit.

the systematic offset is not a problcni. if a symnietric Iayoiit is rlsed. Sirice the siibstrate iised in

the process is Ga.-1s. which is a very poor thermal conductor. estra attention rnust be paid to the

thermal symmetry of the layout. .-lny nsyrtirnetry will create a systematic. therri-ial offset. Tlie

random offset in the comparator is due to random mismatches in the active and passive devices.

ï h e input offset that will appear at the input terminals of the amplifier is given by[10, 141:

The r a n d ~ m offset c m be rninirnized throuçh the use of physically large transistors and resistors.

4.4.1.6 INPUT CAPACITANCE

The total input capacitance of the comparator can be approximated as:

4.4.1.7 POWER

The total power dissipated by the comparator is an important consideration in a large circuit, such

as an ADC. Ijnfortunately. in the HBT procrss the transistors dissipate a lot of power. This is due

to the fact that the transistors have a large emitter area ancl because they have n large tiirn on

voltage ( l,&,, z 1 .-1). necessitating the use of a correspondingly larger supply. Tlierefore the total

pawer dissipation:

is also large.

4.4.1.8 COMPLEXITY OR AREA

This is an important corisicleratiori t'or n large integrated circuit sincc ttic yielcl decreaes for an

increwing chip area. Xlso. 'as the arca. iricreases. the routing oC the signals becornes increasingly

t.oniplicnted. and signal lines becorne longer. t hlis limi ting thc specc! of the (.hip. 'I'lie comparator's

t'ootprint should be niininiizeci tliroiigh the use of physically ~triiill transistors and rcsist,ors.

4.4.2 COMPARATOR CIRCUITS

'The circuit schemntic shorvn in Figure 4.8 is one of many (rortiparator circuit t,opologies. Ottier

poptilar comparator designs will be clisciissed in the next few sections.

4.4.2.1 CASCADED COMPARATOR

One of the clrawbacks of the circuit i n Figure -1.8 is the large base chargirig ciirrent. when the prenrn-

pli fier is strobecl. This phenotrienoti is knorvn lis kick back rioisc~[l:i]. ' ïhe preceding circuit ( Vnity

(;riin Buffer or 'frack ancl Cfold circuit) must source this current in order to turn the preamplifier on

qiiickly. In the fl,wh architecture. 'as the resolution increases. anci witli it the ntirriber of romparators.

the amount of current to be sourced grows esponentially. .-1 circuit tliat overcomes this problem is

shown in Figure 4.9[13, l4].

This circuit has minimal kickback noise since the input emitter-coupled pair (Q 1.Q2) is on for

both the track and latch states. To a first order approximation there will be no kickback noise.

Practically, there is a transient a t nodes 3 and 4. Sy placing a large shunt resistor. any casymrnetry

across the terminal will be shunted through the resistor, and will not affect the base currents of Q1

and Q2[14]. The cascode transistors Q5-Q6 increase the small signal bandwidt h of the preamplifier

in track mode. and also increase the isolation of nodes 3-4 from the input, when in latch mode.

One disadvantage of this circuit is that a larger supply voltage is neecied since t h e are a maximum

of 4 transistors in cascade. This cornparator ce11 also requires approsimateiy 33% more area since

'in P 'in,.,,

R S I R s 2

Figure -!,il: Cc;caded Cornparator circii i t Topology

it h'as 8 transistors and 2 resistors. compared to the ti transistors and 2 resistors that the simple

comparator employs.

4.4.3.2 VARIABLE LOAD COMPARATOR

In the variable loaded compiirator, the recovery time and the regeneration time can be designed

with ,z greater arnount of flesibility. The circuit schematic is shown in Figure -L.10[19].

During the track phase the preamplifier only has resistors Rci and Rc2 as loads. whereas during

the latch phase the comparator has al1 four resistors a s loads. By splitting the resistors in this

manner, it is possible to design the comparator such that the preamplifier speed is sufficient, while

simultaneously having a large enough output voltage swing to drive the succeeding digital encoding

logic. This design is useful when the preamplifter is limiting the cornparison rate.-'. Crnfortunstely

there is a alight increase in complexity in the design when the load resistors are split as shown.

4The recovery and regeneration time dcpeod on the 3 dB and unity gain frequency respectiveiy.

Figure 4. LU: Variable Loaded Carriprirator

4 . 3 COMPARATOR WTTH EMITTER FOLLOWERS

In the analysis of tlie simple cornparator circuit (Figure 4.8). it w u ihown that the dominant pole

of the circuit was a t the base of the input differential pair. Xnother pole isists at the colleetor

terminats (i.e. nodes OCrT and OI'T) , which can be approximated by:

where CL is the load capacitance presented by the next circuit block. In an XDC, the load capaci-

tance is due to the encoding logic. To minimize the effect of tlie load capacitance, an emitter follower

can be placed between the load resistor and the nest stage. A comparator using emitter followers is

shown in 4.1 l[L3]. The emitter folIowers (Qï, Q8) buffer the resistors, Rci and Rc2 frorn the load

capacitance (i.e., the encoding logic) , while at the same time providing a large base charging current

for transistors Q3 and Q4. Unfortunately this topology increases the complelcity and power due to

the two extra transistors and current sources.

Figure 4.11: Simple Çornparntor with Emitter Follower

4.5 COMPARATOR DESIGN AND EXPERIMENTAL TEST-

ING

The remainder of this chapter describes the cornparator that WC= cfcsigned. simulated and tested.

4.5.1 COMPARATOR TOPOLOGY

For the design of the comparator block, various circuit topologies were investigated. These indudeci

the simple comparator (Fig. 4.8). variable loaded comparator (Fig. 4. [O), cornparator with emit-

ter followers (Fig. 4.11). and a variable ioaded comparator with emitter followers. The design

specifications for the design are shown in Table 4.1.

[t was decided that a master-slave comparator architecture required too rnuch area to be imple-

mented. .-\ 4.5V supply was selected for the entire ADC. The comparator could run on a Iower

supply, but the track and hold requires -6.5C'. in the design of the comparator, the load resistor

Table 4.1: Design Goals for the Comparator

1 Power 1 Minimum required to meet the other specifications from a -6.5 V supply 1

Flgure of Ment Total Noise

Cornparison Rate Offset

(& ) , bias current ( L E E ) , and transistor enlitter area (=IE.) are varied in order to reach an optimal

tlerign[20, '111.

hlariy SPICE simulations were run to optinlize the design parameters in the cornparator. The

simulation swceps rcvolved around the output voltage logic swing. I . ~ L i T L L i , , , . In the simulation

sivceps. a set of possible logic levels. ( I ~ ~ L : T , , , , , ) are selected. For eacii of these logic ievels. the b i s

ciirrent ( I E E ) is swept, and in conjiirirtion rvith t.hat bicu ciment sweep. the laad resistor (RcI .) is

Design Goal < 0.3 LSB = 1/2B+' = 1!2IL 2 5oopc.'

2 1GH: 0.5LSB z 500pC'

vnried according to. Rc. = I I E E The masinium logic levcl is liniitecl by the power supply

and the c:ollector-eniitter saturation voltage of the transistors, but more iniportantly, the minimum is

cletermined by the ability to swi tch the succeeding encocling logic. clespi te temperature, and process

variations. To fully swi tch a differential pair[& LU] ac roorri tcrriperatiirc, a clifferential input signal

voltage > f 4 l,:r = f - l k T / q zz f 100mV is required. Taking into nccount process variations and

- tcniperature variations. the minimal output signal swing can be estimated as: Ibr-r,c,,,,,,,,,,,, - 1.2 :< LUOrnl.' = 1Z0rnC3'. or a rriinimum of 'L.lOrnl*,,.

'The simulation results for the simple con-iparator (Fig. -1.8) are shotvn in Figure -1.24 on page

-1s. 'This figure shows the recovery and regenerat iori times of the corn parritor for two cliffereiit

transistor m i t t e r arcas: 2 x 2prn2 and 6.5 x The ti.3 x 3prn2 transistor was selected as a

possible transistor size since it is the most thoroughly tested transistor iri the process. and had a lower

process variation. while the '2 x was the smrillest available transistor. These plots demonstrate a

clecreasing regeneration and recovery t ime wi t h an increaing current. Xlso. as C & J ~ ~ , , ~ , increases,

the recovery time incrertses slightly. with a corresponding decrease in the regeneration tirne.

The simulation results for the variable load cornparator (Fig. -1.10) are shown in Figure 4.25

on page 49. This figure shows the regeneration and recovery time for two different transistor sizes:

2 x &~rn' and 6.5 x 3pm2. In these simulations V&rTL,,,, = 300rnV. but various ratios for

resistors Rc 1, RcL and RC-, RCZ2, at various bias cwrents were iised. The total series tesistance of

RT = Rcl + Rcr i satisfied the relation, RT = C;OuTLoGrc/IE~ during the sweep of the bias current

( L E E ) ' . The ratios used in the simulation sweeps are listed in Table 4.2.

The results shiiwn in Figure 4.25 dernonstrate that as the ratio of R c l / R T is increased from

20% to 80%. the recovery time increases. This is expected, since equation 4.20 predicts that the

"The same relation applies to resistors RCZ and RC22.

CH.4 PTER 3. COMPP4RATOR

Table 4.2: Resistor Ratios used in the Variable Load Comparator Topology

Curve # 2 Curve # 3

tinie constant of the preamplifier iricreases as the load resistance incre'ases. Fiirthermore. there is

;L rrorresponding decrease in the regeneration time R C l / RT increases. This increase in speed is

tiot d u e to an increase iri the bandwidtli ot' the iatch. rhe bandwdth renialns at approximately

t h e same level since the total resistance seen at the collecter nodes is constant. The regeneration

tinie tiecreases because the initial voltage across t h e latch is inc-reaing with an increasing f iC2/&.

As is evident in the plots there is only a minor ciifference iri the speed of the comparator for the

two clilfercnt transistor sizes. in order to minimizc the effects of offset and noise. t.tie ij.5 x :jprn'

transistor is ~isecl. X s previoiisly nientiond. t his is also the hest charac tcrizcd transistor. Also.

sirice splitting of the loaci resistor docri not c:rcat.e a large irriprovcment in thc rcgenttration tirrie this

topology is not used. In addition. the bicas current arid outpiit voltage swing arc selecteci according

t o the following criteria:

i ) Froni Figure 4.2-1. Tor low ciirrent levels. the speed of the conipwator slegrndes q ~ ~ i c k l y . Tlie

bias ciirrent \vas chosen such that the regeneration time (t,,,) and recovery tirtie (l,,,) were

insensitive to process variations. and also near t heir rriinimurn value.

i i ) The bias crurrent could not be made too large, since the load rcsistor. ( i . ~ . . Rc. = I&-Ttocï ,c/ lEE)

would becorne too small. As the resistance clecreases. the riccuracy of the resistor decrease since

it will have srnaller physical diniensions.

i i i ) 'The output logic levels are chosen such that the cornparison rate is not comprornised. and also

so t h a t the output voltage is large erioirgh. despite process variatiotis. to drive the encoding

logic. Another factor in determining the output logic levels, w u the required load resistor.

Rc. This vahe couId not be too small, since the accuracy wouid be comprorniscd.

The emitter foilower topoiogy (see Figure 4 . I l ) is used to minimize the effect of the load capac-

itance from the encoding logic on the comparator performance. X summary of aelected values is

shown in Table 4.3.

In addition to the comparator circuit. several other circuit blocks were designed in order to

facilitate the experirnental testing of the comparator. These blocks, along their purpose are ahown

in Table 4.4. The design choices made for these blocks are presented in the following sections of this

chapter.

Table 4.3: Surnrnary of Design Clioices for the Comparator

Table 4.4: Xdditional Circuit BIocks used in the C'omparator Circuit

4.5.1.1 AMPLIFIER

C'ircwt Block .-Implifier

Clock Buffer Output Buffer

C'urrent Mirror

The amplifier is placed before the comparator block and it is used to minimize the kick-back noise

frorn the switching of the cornparator. and also to provide additional gain. 'This amplifier. much like

the prearriplifier in the corriparator block, must be clesigned so that the bnnciwiclth. noise. offset. and

power are within the desired design constraints. ;1 scheniatic diagram of t lie amplifier is shown in

Figure .L. 12.

The bandwidth and gain of the amplifier are important dcsign specifications. The bandwidt h

of the amplifier should be the same as tliat of the preamplifier in the cotriparrttor(22]. Designing

tlie amplifier to have an estremely large bandwidth does not have a significant impact. since the

overall bandwidt h of the amplifier/comparator depends on bot h the amplifier and prearnplifier of

the cornparator. Thus the amplifier should bc designed to have approximatety the same bandwidth

as the preamplifier. while at the same lime maximizing its gain. By nzaximizing the gain, the

initial voltage across the latch is larger. The design rnethodology for the amplifier is siniilar to that

described for the comparator.

4.5.1.2 CCOCK BUFFER

Pir rpose To provide sain and limit Kick-Baçk.

Lirnits Kick-Back to the dock Drives the output load resistance (.?O R ) and capacitançe. Replaces ideal current sources.

The high frequency base charging currents of the comparator's current switching differential pair

(i.e.. Q5 and Q6 in Figure 4.8) must be buffered from the dock inputs. .4 schematic of the clock

buffer is shown in Figure 4.13. A problem encountered in the design of the clock buffer was ringing

Descnpt m n Differcntial Pair. preceded by emitter followers. Ernitter followers. Differential pair.

Simple C'iirrent Source witl i .1 r:ompcnsatiori and etnitter cfegenerntion.

CHA PTER 4. COibI P-4 R4TOR

F+,= ssa %,= ssn

- in 50 O UT OUT

P QJ 6 . 5 ~ 3 pm2

Figure 4.12: Amplifier used in the C'ornparntor

xt the bcases of the current switching differential pair. This wcas attribiitcd to ctie estrinsic base

resistance of the ernitter followers anci the bond wire inductance at the dock inputs. The ringing

cirises frorn the l/(J( f ) + 1) inlpetiance trnrislormation in a bipolar transistor[ll]. The Irequency

dependence of tlie a.c. ciirrent gain plays ari important role nt high Sreqiiencies. 'This tfequency

dependent gain causes a gyration of the irnpedances hetween the b<we and erriitter at high frequencies

(i.e.. above the 3 ciit-off t'requency). A rcsistor and inductor. in series with the hcase. gyrnte to a

series inductance and negative resistance at the eniittcr respectively. A srnaller ernitter area provides

a signal with less ringing than a larger transistor. prirnarily bccause the extrinsic eniitter resistance

is large large enough to dampen the ringing.

4.5.1.3 OUTPUT BUFFER

The output buffer is shown in Figure 4.13. Resistors. Rci and R c s 2 were added to reciuçe reflections

from the load. The impedance looking into the collectors of Q3 and Q4, with these resistors incliided

in the circuit is approximately 50 R. [f the load is a .ïO L! resistor. then Rci and Rc? are unnecessary,

since there is no reffected wave. However. the resistors protect the circuit from instabilities that

could occur if the output is not terminated correctly.

Ernitter followers. QI and Q2 are used to minimize the load capncitance presented to the com-

parator. This is necessary since transistors. 4 3 and Q4 consisted of five 6.5 x 3 transistors in

parallel. To minimize ringing at the base of differential pair Q3,Q4 two small series resistors, REr

and RE3 are added.

Figiire 4.13: Clock Buffer

4.5.1.4 CURRENT SOURCE

Tlie trurrerit source tised in the comparntor is shown Figure -1.13. 'illis is a qooci topolaçy becaiise

the output current ( l C v 2 ) tins n smnll dependence on t1.ç. 3. The output curr~r1t is givm by[iO]:

Dcçcneration resistors R I and RZ are used to prevent thermal runaway? and to improvc the

relative accuracy of the output current with respect to the reference current[l0]. These resistors. in

cior~jiinction with t h e transistor areas of QI and ($1 are usecl to sçale the output current with respect

t.o the reference current. Two important design eqiiations for this circuit tire:

[C 7 - - - ErniLter --Ireu of Q:! - - - R i RE F Emitter -4rea of Q 1 R2

The degeneration voltage across resistors R1 and R2 is an important design choice. As the

voltage across the degeneration resistor increases. there is a corresponding increase in the absolute

accuracy of the reference current and the relative accuracy between the output current and reference

current[lO]. Unfortunately. for an increasing degeneration voltage, a corresponding increase is needed

in the supply voltage.

-- - - - - -

6E~pecially important in CaAs due to the lower thermal conductivity

Figure 4.14: Oiitpiit Butfer

4.6 COMPLETE CIRCUIT AND LAYOUT

' rhe cntire circuit is sliown in Figure -1.16. Two t!stcrnal rd'erence resistors :ire irsecl to set the

rcference cirrrcnt. A11 50 R mntching resistors are placcd on-c-hip in orcier to iniprove the rrtcirn

loss[23]. The chip micrograph of the entire voniparetor is slioivn in Figure -1.27 on page 51. Extra

attention wcas paid to thermal syrrimetry in the layoiit of the inclividual blocks. Each circuit block hcw

gooci electrical ancf thermal symmctry. but the Iayout of the entire corriparator can he improvcd. The

bias circuit was placeci below the entire signal path. This blosk is placed far away (npprosimatcly 200

pm) from the amplifier and regenerative latch. and did not cause a thermal gradient. but it could

bc improveci. The ctirrent sources should be positioned wittiin the signal conditioning circiritry

thiis irnproving the overall thermal symrnetry. This was done for the Track and Hold (described in

Cliapter 5).

4.7 SIMULATION AND EXPERIMENTAL RESULTS

This section will present the simulation and experimental results for the comparator. Three sets of

measurernents were made; single ended dock and input with on wafer probe, differential clock and

signal witli packaged devices, and differential clock, single ended input on wafer probe measurements.

b VEE

Figure -1.1.5: C'urrcnt Source Topology uscd in the C'omparator

4.7.1 SINGLE ENDED INPUT AND CLOCK WAFER PROBING

The first set of experimerits performed on the cornparator iised single ericled on wafcr probes. A

ciiagram repreljenting the test m u p is shown in Figure 4.17. For th i s expertment a single ended

clock and input signal w~as used. It was riot possible to utilize a ciiffcrential dock signal because the

RF wafer probe tips for clifferential probing wcire tinmaged. Fully rlitferential tests were done wi th

packclged devices.

4.7.1.1 OFFSET AND SENSITIVITY

The offset in the comparator is due to the random mismatches between devices in the circuit.

caused by process variation across the wafer. If there is no input signal present, the output of the

comparator is constant (positive or negative!. depending on the polarity of the offset'. A photograph

of the comparator operatirtg without an input signal is shown in photograph # 1, in Figure 4.18. In

this photograph the latch always regenerates to a positive output voltage, since there is a positive

offset. To mesure the offset. the 500 MHz, sinusoidal. input signal $vas slowly increased until the

comparator would randomly latch to positive and negative values. This implied tliat the offset

had been compensated for, and the noise was determining the output signals. in Photograph #2,

of Figure 4.18. the input signal level is 1-2 mV and the latch output takes on both positive and

; ~ h i s will happen if the offset is larger than the total noise at the input. if the noise is greater than the offset then the output is random.

- - MWSURING INSTRUMENT .- (OSCILLOSCOPE)

1

R 1

LOAD :

Figure 4. ltj: The Comparator Circuit

tiegntive values. and thus the otfsct is 1-2 rriV. 'ru sec how an offset of 1-2 mV was interreci [rom this

nieasurement. consider the îbllowing. 'The input signal can bc. writtcri ris:

whcre C.;,,,,,. L;,ll,,,r aricl C ' o s rcpresent the noise. signal and off'set voltage respcctivcly. I f the offset

is 2 mV and the input signal is -2 rriV. t hen:

and thus the output voltage is randorn. This oçcurs a t the rightmost portion of photograph # 2.

The comparator output is both positive and negative a t this time instant.' The measurement of

offset in this rnanner is lirnited by the sensitivity of the oscilloscope and the purity (i.e., noise) of

the sources. From rneasurements across the entire wafer. the offset w u f 1-2 mV.

The resolution or sensitivity of the comparator depends on the total noise and offset voltage

present at the input. In order to determine the sensitivity (i-e., noise and ofFsetf of the comparator,

the input signal is increased so that the tatch output is consistent. The input voltage at which this

happened was approximately f 3 mV across the wafer.

aThe oscilloscope was in persistance mode.

-

Figure -1.17: Test Setup for Single Erided or1 LC'rifer Probing

4.7.1.3 RECOVERY AND REGENERATION TIME

The recovery time of the comparator was deterrriintld by using the overdrive test[I+l]. [ri tliis test. a.

'LOO mV input signal, at half the dock frcquency wris used. The simulation and esperirnental results

for a 1 C;lEz test are sliowri in Figure -1.26 on page 50.

The recovery tirne of the comparator was foiind to be 100 ps ir i simulation and approximately 90

ps in esperirnental results. The measured recovery time of t hc vomparator derriorist rates that the

cornparison rate cari be much higher than 1(:;th9.

The regeneration time of the comparator w,zs tested by applying a small input signal. at half

the dock frequency. A small signal w m used so that the latch was initially in the lincar region of

operation. Tlic regeneration time was tested at different Sreqiiencies but for brevity I GFfz results

are only presented. This experiment used a 1 GHz. 200 rnVp (-4 dBm) clock with ri 500 MHz input

signal. The initial voltage ncross the latcli wns approximately 50 mV. In experimental results it took

100 ps to reach its final voltage. Simulations predicted 105 ps.

4.7.2 PACKAGED RESULTS

[n this section the packaged results are presented. A tiigh speed test fixture was used to test the

comparator that was in a lead ceramic Rat package. A schematic representation of the test setup is

shown in Figure 4.19. In these tests, a differential dock and input signal were used.

'The circuit was functional up to 3 GHz. It could not be tested any higher due to limitations of the test equiprnent

Photograph $1: No Input Signal Photograph #2: A t Offset Voltage of C'omparator

Figure 4.18: Offset Voltage of Comparator

4.7.2.1 OFFSET AND SENSITIVITY

'The sensitivity of the coniparator is a functiori of the offset and noise in the cornparator. [ri order

to determine the offset of the comparator. ~ h e same methocf used for wafer probing w,w utilized.

The input signal power at which the comparator is able to latrh to both negative and positive

values is considered the offset. The input signal power at which the comparator latched consistently

to the correct value is considered the sensitivity. In determining the offset and sensitivity of the

comparator, it is important to ensure that the input voltage is at its peak voltage when the transition

€rom traclc to latch is made. Figure 4.20 demonstrates the phase reIationship between the dock and

input signai. In these tests, the clock power was also varied. Much like a mixer in a radio. the power

that is needed to drive the comparator is important because a tow power RF drive signal is desirable.

The offset and sensitivity measurement for two chips are summarized in Table -4.5 and Figure -1.21.

In the rneasurements, the losses in the cable. phase shifter and 180' hybrid were compensated for in

the quoted clock, offset and sensitivity values.

[t is interesting to note that the sensitivity and offset depends on the clock amplitude. This c m

be attributed to the clock feedthrough and the capacitive base-emitter mismatch of the cross coupled

transistors in the regenerative latch. The clock feedthrough is due to the base-collector capacitance

of Q6 in Figure 4.11. if the base-emitter capacitances of transistors Q3 and Q4 are matched, then

- KIKUSI -

DC SUPPLY 0

DC SUPPLY e

HPXWA r TEKTRONW TDRlll R : VBMS REFIL. Oscilloscope -

1N OLT - IN OLT i

CLK R - REE CLK "EE

-

Figure 4.L9: Test Settip for the Packaged Tests

Table 4.5: Summary of the Experimentnl Sensitivity Rcsiilts on tlic Pnckaged C'ornparator

CHIP # 1 CHIP # 2 Offset 1 S e n s ~ t i v i l y

tliere is no dynamic change in the base voltages duc to the dock fecdthrough. if there is a capacitive

niismatch. then there will be a dynamic voltage mismatch in the latch. anci thus the sensitivity will

he cornpromised. in order to obtain good sensitivity a low power dock is desired.

4.7.3.2 RECOVERY AND REGENERATION TIME

The recovery time was rneasured using the overdrive test. In the packaged results." the sensitivity

of the recovery time to the clock power was tested. The dock power Iiad a srnail effect on the

measured results. The phase shifter was used to ensure that the signal was at its most positive or

negative peak when the transition from Iatch to track mode was made. The recovery time was found

to be 100 ps for a 500 MHz input signal and LGHz dock. with simulations predicting 90 ps.

The regeneration time was measured in a sirnilar rnanner to that done for the on wafer probing.

The input signal was a t .500 MHz, with the clock at 1 GHz. Through the use of the phase shifter the

- -

''The results in this section are from CHE' # 2. Chip # 1 was not functioningdue to a broken bondwire connection

Figure 4.20: Phase relationship between the dock ( 1 GHz) and input sigrial (500 hI HZ)

phcase relationship between the dock and input signal was the same ns that in shown in Figure 4.20.

In the testing of the regeneration tirne. the ctock power w w varied in order to denionstrate its effect

on the speed of the compnrator. h conccrted effort wu made to maintain the same initial voltage

across the terminais t'or al1 dock levels in orcier to make a fair cornparison between the diffcrent

dock powers. .I\ summary of the experimental resuIts is shown in Table -1.6.

Table 4.6: Summary of Regfineration Timc .tleasurements

-. - . -

EXPERIMENTA L Clock Power dBm

- -

- -- S I M (rt-AATiiKNN .Y Differential Out- put Id tage m C'

Timr ps ' Clock Potuer dBm

Tinre ps Dlffrrentiol Out- pirt Loltuye rn C'

I -4

- I I -10 4 4 4 2 a 2 --(<hl

a) Offset in Chip # 1 and Chip # 2 b) Sensitivity in Chip # I and C'liip # 2

Figure -4.2 1: Orset and Sensitivity of the Packageci C'omparator

4.8 BIT ERROR RATE RESULTS

As h w bcen mentioned. in order to obtain a better estirriate t'or the sensitivity of the comparator n

bit error test (BERT) needs to be clone. A B E R T is a quantitative meastlre of how consistent the

vomparntor latches to the correct value. A clingram of the test sctup is shown in Figure -1.22.

Figure 4.22: Test Setup for the Bit Error Rate Tests

In a bit error rate test, the bit error rate will depend on the ratio of the signal power. to that

of the noise. [f there is an offset in the system, then the signal needs tu be larger than this offset

before a bit error rate measurernent can be made.

CHAPTER 4. COR.fP.4RATOR

It can be shown that the bit error rate, assuming a Gaussian mode1 for the noise source is:

BER = @) where S represents the signal power. C'os is the offset in the systern. and a is the noise. Equation

4.32 demonstrates that the otfset reduces the BER.". Experiments were rrin with and without

compensating t'or the otfset. on différent chips. [n the test setup. the offset of the comparator

was cornpensateci for through the use of d.c. power supply on the negntive input terminal. One

clisadvantage of using the power supply a t the negative input terminal. to compensate for the offset is

the power siipply noise t'rom that dc source. which will limit the BER. This was niinimized as much

as possible through the use of a decou pling capacitor across the terniinals of the supply. Nonetheles,

the power supply will have a srnall effect or1 the performance. 'The experiments were riin on varioiis

1-hips. ancl a t different frcquenriies. The experimental results of the BER tests. rvit t i a 2SOrnI > cloci:

signal is shown in Figiire 4.23. Figure 4.23 a) shows the BER as n fiinction of the absolute signal

Ievel. Figiire 4.23 b). shows the rneasured BER and theoretical BER 'as a functiori of thc Signal to

Yoise Ratio (SNR), for an cstimatecl noise of -100 p V. Figiire 4.23 CI) is the samc ris Figiire -1.23 )

a). but in this test the offset was not compensated l'or through the use of the dc sourcc. 'flic effect

of the otfset was rernoved by subtracting the estimated offset froni the signal lcvcls. At the low bit

rrror rates. < 1 0 - ~ . acciiratc rrieasiirements become tlifficult since a n y small pertiirbance (i.e.. rell

phone turns on. other equiprnent. people walking by. etc.) in the system wiIl create a burst of errors.

which is noc representative of the noise in the circuit. This may bcx the cause of the BER levelling

off a t the lower bit error rates.

Pattern dependent errors. due to the thermal properties of the transistors were also observed.

Consider the case where there is a large string of positive inputs. Thus. in a differential pair one of

the transistors has been on the predorninant amount of thc tinie. and thus its junction teniperature

is higher than that of the other transistor. This creates a thermal offset in the two transistors. Thus,

if a negative input occurs after this long string of positive inputs, the input must be large enough

to overcome the thermal offset chat h a s been built up in the two transistors. This will increase the

BER of the comparator. Figure 4.23 d ) shows an example of this pattern dependent. thermal offset.

In the Ieftmost portion of the waveiorm. the comparator experiences a transition from a a long string

OF positive inputs, to a negative one. Then there is a string of negative inputs. During this string of

negative inputs. the initia1 voltage difference across the Latch, before it enters the Latch state slowly

"The Q(-), and the BER are discussed in more depth in Appendix A

begins to increase. This is a manifestation of the thermal offset in the latch being reversed. At

the rightmost portion of the figure, the same transition made at the Ieftrnost portion of the figure

is made, but this time the thermal offset is not as prevalent. as is evident from the lnrger voltage

difference across the latch.

4.9 CONCLUSION

This chapter h a discussed the theoretical and practical aspects o fa comparator design. The metasta-

bility df tlie coniparatùr was ciiialyzed tlirougli tlie use d a si~tiplifieci cross-coirpled first orcler inverter

model. It w u shown that the probability of error falls off exponentially with the unity gain bnnd-

width of the indiviclual inverters. 'The design of the comparator circuit w~as outlinod dong with the

Iayout. The esperimental results dernonstrated that the comparntor wns ftinctional iip CO :l(:;tIzl'.

The serisitivity was rneasured using the oscilloscope as a rough, qualitative meastire of when the

vomparrttor latched consistently to the correct value. These tests denionstratecf tliat the conipara-

tor's sensitivity depended on the dock signal power due to clock feedthrough. [ri order to obtain

a better rneasure of the sensitivity of the chip. BER tests wcre conductecl rtt different frequencies.

and input signal Ievels. The offset in the chip rvas greater than expecteci, wliich may he dile to a

fabrication delay in the exler13 ancl is being fabricntetl and restecl again. .-1 short stimmary of the

ésperimental resiilts is stiown in Table 4.7.

Table 4.6: Sumniary of Esperimental Resiilts

Recovery Time ps Regeneration 'rime ps

Offset mV Sensitivity mV

Active Area Power of cornparator core rnLV

'Total power mW Power Supply V

Ftgtrre of .\lent Cornparison Rate C; HL

1

Overdrive test 'LOO rnV threshold value. and -6 dBm dock

1GHz dock and 500 1IHz input Wi th offset compensation. BER of IO-''

12The frequency iimit of the test equipment was 3GHz I3There were some quality assurance issues

- -

.\leclsurement Defin1 t ion E~penmental 3

a) BER vs Signal Power at L.2.2.5 ancf :l GHz b) BER vs SNR at i and 2 CiHz

(1) BER vs SNR with no dc bi'u source for offset compensation <. :A* l , , -"'

1

I . .

I I " ' " ! !

2.l$lr,;:-- -. --*" ----- a-.

q:'. - 1 1 2 -- - - t r i@/diu 137.

d) Pattern Dependent Thermal Offset

Figure 4.23: BER Experirnental Results

CH-4 PTER 4. COMP.4 RATOR

1 I I I L I O 1 2 3 .t 5 6 7 a 9 1 O

IEE ImAl

a) Regeneration (TREs) and Reçovcry ( f i E c ) time for ti.5 x :iPm2 Transistor vs Eniitter Bias C'iirrent ( I E E )

i 150 -

3 ;1w- - t

50 - - 7 -

O0 1 1 1 l L 1

0.5 1 1.5 2 2.5 3 IEE [mAl

b) Regeneration (TnEc) and Recovery (fiEC) tirne for 2 x 2pm2 Transistor vs Ernitter Bias Current ( I E E )

Figure 4.24: Sweeps of Design Variables to Maximize Comparator Speed for Simple Comparator

Curve # 1: + Curve # 1, x Curve # 2. " Curve # 3 300 I 1 1 I 1 1 1 I

250 - - g200

- - C 150 ° t 100

I

a ) Regeneration (TREc) and Rccovery (GEc) timc for 6.5 x :lPrn2 Transistor vs Ernitter Bias C'iirrcnt ( L E E )

IEE [dl

b) Regeneration (TREG) and Recovery (TnEc) time for 2 x 'LPm2 Transistor vs Ernitter Bias Current ( I E E )

Figure 4 -25: Sweeps of Design Variables to Waximize Cornparator S peed for Variable Comparator

2 -4dBm : j d J .- ' Jn 2 a n : dn 4 J~ n ." Time s I )

HSPICE Simulation

Expanded View Zoomed in View

Figure 4.26: Simulation and Experirnental Results for Recovery Time with a Single Ended Input and Cloçk Signal

Figure 4-27': Layout of the Entire Comparator

Chapter 5

TRACK AND HOLD

The t,rack and hold circuit is a c:orrirnonly used circuit block in Analog to Digital Coriverters. As

tvas seen in Ctiapter 3 i t was used in the pipelineci and flash architectures. A block level diagram of

an open-loop track and hold is shown in Figure 5.1.

LOAD

Figure 5.1: Block Diagram of a Track and Hold Circuit

In the above circuit, amplifier AL is used to buffer the source from the targe current spikes createcl

by turning switch ( S l ) on and off. Similady, amplifier A2 buffers the hold capacitor, CH from the

Ioad (i.e.. cornparator in an ADC), and .A3 acts as the buffer for the dock. For one half of the dock

cycle, switch S1 is closed and the circuit operates as a unity gain buffer. For the other half, the

switch is open and the charge stored on the capacitorl remains constant. An example of the signal

- - - - - - - - - - -

'Typicaliy a capacitor, rather than an inductor is used to store the signal level because monolithic capacitors have

52

CHAPTER 5. TR4CK -AND HOLD

waveforms present in an ideal track and hold circuit is shown in Figure 5.2.

Input and Output of Track and Hold

Time [nsj

Clock

Time [ns]

Figure 5.2: Track and HoId Signal Waveforms

Some comnion rnetrics to measure the performance of the track and hold arefl-lj:

i ) Hold Settling Tirne: The time requircd for the held signal to settle within a specified error

band.

i i ) Acquisition Time: The tirne needed for the track signal to settle within a specified error

band.

i i i ) Pedestal Error: The voltage step experienced by the held signal when the switch is turned

off.

iv) Hold Mode Feedthrough: X measure of how much of the input signal appears at the output

during the hold mode.

Si nul Power v) SINAD: The signal to noise and distortion ratio. SIN;LD = ,voire Po<ucr

a much higher Q than the monolithic inductors.

CH.4PTER 5. TR4CIi .4ND HOLD

vi) ENOB: Effective number of bits. E X O B = sr""D - ; SINAD in dB. O 07

vii) Aperture Uncertainty: Deviation of the sarnpling instants from equally spaced points in

tirne.

viii) Droop Rate: The linear decrease in the output voltage due the discharge of the hold capacitor.

.-1 surnrnary of the design specifications for the track and liolci for use in a 10 bit. lGS/s XDC is

shown in Table 5.1.

Table .5.1: Design Goals for the Track and HoId

5.1 SELECTION OF SWITCH

Frgure of Ment Hold Settling Timc .-icquisition Time

Peciestal Error

Hold .Clode Feedtlirough Droop Rate

SINXD ENOB

Signal Swing

The switçh of a track and hold circuit is a criticnl block because many of ttie rtictrics depend on

its performance. In the liternture, the diode rjwitch has ciertionstrateci the nbility to operate in the

Ci iga-sarnple rangef241. TypicalIy Schottky diodes are used because of their ability to switch very

quickly.

[n recent years it h a been dernonstrated that the use of a Switched Emitter Follower (SEF) can

bs used in a high performance track and hold [25. 26. 271. h circuit ciiagram of a SEF is shown in

Figure 5.3. This circiiit is linear. and has a wide bandwidth because it is an ernitter follower[lO]-

Due to the absence of Schottky diodes a SEF was used as the switch.

Destgn Goal < 50Ops < +jOOps

Linearly dependent on input signal cornmensurate with 10 bit. operation. X constant. or linear step can be calibrated out.

< -6OdB < O.5Lj.B in .ïOO ps. or Ipl ' lps

ij2 cl13 LO Bits

1 I i r l

5.2 ANALYSIS OF SIMPLE CIRCUIT

En order to illustrate some of the design choices that were made in the design of the track and hold,

a single-ended, open-loop track and hold circuit will be analyzed. This illustrative circuit is shown

in Figure 5.4.

In this circuit transistor Q2 acts as the switched emitter follower, with the differential pair

composed of transistors Q4 and Q5 acting as the current switcli. The input and output buffers are

CHAPTER 5. TR4CK AND HOLD

Figure 5.3: Switçticd Erriitter Follower

Swiiched Emittcr Unitv Gain Fdlowor Output

B i u Ter Buffcr / Ruffrr

tl SUPPLY

Figure 5.4: Single Ended. Open Loop, Track and Hold Circuit

CHAPTER 5. TR4Cii AND HOLD

represented by transistor Q1 and Q3 respectively, ivith CH representing the hold capacitor.

5.2.1 SLEW RATE

Tlie slew rate is an important design parameter for a high frequency, large signal swing circuit, such

ns the track and hold. This figure of merit is important for the transition irom the Iiold to the track

state. The slew rate, in conjunction with the small signal bandwidth of the circuit, miIl deterniine

the acquisition time of the track and hold. For the circuit shown in Figure 5.4. the slew rate is given

b y:

Equation .5.l illustrates that the bias current ( I F E ) should be maximized. while the liold capac-

itance (Cf[) shoiild be rninirnized for a large Slcw Rate (SR).

5.2.2 SMALL SIGNAL BANDWIDTH

The dominant pole in the circi~it shown in Figure 5.4 is ac the holci capacitor. Through the use of

the beta tranaiormation'[~. i 11 the eqiiivalent srnall signal circuit at the hold capacitor is sliown in

Figure .5 5 .

J) Sm11 Sipnd Equivalcnt Mdel b l Appmx~mtc Smdl Signai Equivdrnt .Mafrl

Figure .5.5: Equivalent Network Representation at the Hold Capacitor

The bandwidth and Q of the circuit is given by:

'Note that the gyration between the baçe and emitter, at high frequency causes the extrinsic base resistance to appear as an inductor at the emitter

CHAPTER 3. TR4CK AND HOLD 3 7

From equations 5.2 and 5.3 in order increase the bandwidth. the resistor RL must be minimized,

wliereas to decrease the Q, the reverse should be done.

5.2.5 HOLD MODE CAPACITIVE FEEDTHROUGH

Ever: prnctical switch h a a finite capacitance when it is off. For the switched emitter folloiver this

is tiom the base emitter junction capacitance. An equivalent circuit of Figure ,.AI, in the hold mode

is shown in Figure .5.6.

Figure 5.6: Simple 41odel of Switcli in Hold Mode

From Figure 5.6. the lielcl signal ( L , ; r o L D ) is given by:

wliere C;, represents the j unction capaci tance of the base-tirnitter junction. To rninimize the

keclthrough of the input signal. the input voltage swing and junction capacitmcc should be mini-

mized. while the hold capacitance should be increucid.

The variation of the feedthro~igh with the junction capacitance is given by:

Thus. for every halving of the junction capacitance the feeclthrough decrerises by the same

amount. .-ln interesting. and very iiseful property of cl. junction capaci tances is their nonlinear

dependencc on reverse bias voltage. The junction capacitance t'or a p n junction3. with a grading

factor m,,, built in potential of @o. zero bias junction capacitance of Cjo, and reverse b i s of VD is:

Equation 5.6 pcedicts that for srnail changes in the reverse bias voltage near the built in potential.

translate to large differences in the junction capacitance. Thus, in hold mode the voltage drop across

.IThis equation applies to both heterojunction and homojunction transistor

CH.4 P TER 5. TR4 CI< -4 :VD HO L D

the base-emitter junction sliould be rninimized to limit the feedthrough.

The feedthrougli's dependence on the input signal swing can be written as:

Therefore. any tlecrease in the signal swing translates to a decrease in the feedthrough. The depen-

dence of the feedthrough on the hold capacitance cnn be written as:

'Thus <as cl and z incre;ise, the feedthrough cfecreases. -4s r heçonics very Inrgc. equntion 5.9 beconies:

%me representative plots of rlcriiation 5.9 are stiown in Figure 5.7

Figure 5.7: Feedthrough as a Function of Hold Capacitance

The analysis in this section suggests that it is more effective to try and minimize the feedthrough

by optimizing the junction capacitance and input signal signal swing, rather than by increasing tlie

Figure 5 . 8 : Simple Model for Pcdestal Error

hold rapacitance. This is due to the fact that the Ieecittiroiigh is more sensitive to thcse design

parameters than the hold çapacitance.

5.2.4 DROOP RATE

The ciroop rate is a mesure of the linear decrerrse of voltage on the hold capacitor diiring the hold

mode. In the representative track and Iiold circuit of Figure 5.4. the droop rate is due to the finite

bcase ciirrerit of transistor Q4. To deterniine the tiroop rate. consider the charge on the capacitor

given hy. Qcr = CfIl 'h. Differentiating this with timc:

al i f I o Y Ci* - AT

CVhere lo represents the d.c. bcase current of transistor Q3.

can be written CU:

nr,h Droop Rute = - =

CT

( s 5 . 1 1 )

Rewriting eqiintion 5.11 the droop rate

in order to minimixe the droop rate the base current must be minimized, wliile the hold capaci-

tance shoufd be maximized.

5.2.5 PEDESTAL ERROR

The pedestal error is the change in the hold voltage of the capacitor due to switching. In the circuit

shown in Figure 5.4 . during the transition from track to hold there is a large current spike at the

base of Q2 due to Q4 rapidly turning on. A simple mode1 of the current at this time instant is shown

in Figure 5.8.

In this simple first-order approximation. the change in hold voltage is:

Where TGFF represents the time for transistor Q2 to turn off.

5.2.6 APERTURE UNCERTAINTY

The aperture uncertainty is the deviation of the sarnpling instant from equally spaced points in

time. 'Clie variation in the actual sarnpling instant will mariifest itself as a decrease in the effective

resolution of tlie data çoriverter. I'he number of bits (B) achievable, with a tirne jitter of ( t j i t t e r ) in

the dock is[12].

Wherc f i n is the inpiit

be takcn in selecting (z

signal t'rcquency

low jitter clock.

in C1ert.z. ï h i s equntiori

(.5.14)

dernonstrates tliat great mro rniist

5.2.7 CONDITIONS REQUIRED FOR AN OPEN SWITCH

In order to ensure that the switched ernitter follower (i.e. transistor Q2 in Figure 5.4) is off the

base-ernitter junction voltage ne& to be Iess than \ ,OEIOFF V a t al1 tinies. [ r i order to maintain

n. collecter current in the nario-.-Imperes region the base-jurictiori voltage rieeds to be kept below

approxirmtely 0.9 V ( \ . O E I O F F ) in tlie CIBT process. The masirniim base-tmitter voltage diiring

the hoId mode is:

If the design constraint that l'oE < C . i E l o p ~ is imposed. tlien tlie required switch b i s current

( I E E ) and load resistoc (RL) product is:

As a numerical example. consider the specific case where I;i,vpp=l V. \'bEloPF=0.9 V and

C , ~ E j o L v = L . - I V. Through the use of equation .5.lo. iEE Rr > 15V. This deinonstrates that the

required drop across RL can be quite large. thus care must be taken to prevent the saturation of

QI. If QI saturates during the hold mode. the acquisition time will be compromised since extra

time will be needed to take it out of saturation.

5.3 INPUT BUFFER

The input amplifier of the track and hold ideally acts as a large bandwidth. low noise. and highly lin-

ear unity gain buffer. The input buffer is the limiting factor in the linearity of the overall system[26].

The various amplifier topologies t,liat. were loo ked at are sumrnarized below.

i ) Simple Ernitter Degenerated Differential Pair.

i i ) Diode Loaded Differential Pair.

i i i ) Quinn's C'ascomp['28].

iv) Caprio's Quad['L9]

v ) Karanicolas' Foldecf Diode Loaded Differential Pair[3U].

v i ) Miki Differential Pnir[31].

One of the input aniplifiers lookeci a t w u Qirinn's Cascornp. This circuit is shown in Figure

-5.9 a). This circuit h a an eniitter degenerated différentia1 pair (Q1,Q'L) with cnscock transistors

Q:I.Q4. 'Throiigfi the use of a feedforivard transconciurrtance rrror amplifier (Q5.Qti) the nonli~iearity

in the collecter currents of Q3,QL is compensatecl Tor. This circuit w,as not utilized bccausc of the

mmplesi ty and ponter dissipation neecled to rrchieve the linearity cfesired.

The input buffer from Miki in [3 11 rv,?s &O considered as an input bufkr. This circuit is shown

in Figure 5.9 b). This circuit compensates for the nonlincarity in the rollec-tor ciirtent of Q 1 ancl

Q2 through the use of emitter foltowers Q3.Q.I whicfi have a signal dependent bkw. Tliis circuit wc?s

not used due to t l i ~ nurnber of transistors required, and simulations iridicated tliat the liriearity w u

riot comparable to the otlier circuits.

Caprio's Quad was also c-onsidered as an input buffer. Through the clever interconnection of

transistors (Q3 and Q4) (Figure 5.10 a ) ), the transconductnnce of this amplifier becornes dependent

on the degerieration resistor R E . The computer simulations of this circuit demonstrated that it had

the capability of achieving the linearity specifications of the system with minimal cornplexity and

power. and thus is a good candidate for the input buffer.

The folded diode Ioaded differential pair in [30] was considered as an alternate input buffer.

This circuit (Figure 5.10 c ) ) clraws its inspiration from the diode loaded differentinl pair. with an

improved ability to operate a t lower voltage supplies. Unfortunately the linearity of this circuit did

not approach that of the diode loadeci differential pair, and of the other circuits and was not used.

T h e diode loaded differential pair (Figure 5.10 b) ) was used as the input buffer because it

satisfied the linearity requirements of the system with the least arnount of power and complexity.

Furthermore it has been used successfully in a previous high resolution track and hold[25]. in the

CHAPTER 5. T R - K K A N D HOLD

(p 9 O

b) M i k i Différentiai Pair

Figure 5.0: Qiiinn's Ccascomp and Miki DifFerenticzl Pair

following sections an analysis in the linenrity of the rlifferential pair with ernit ter degenerntion ancl

n diode loaded differential pair will bc givcri.

5.3.1 DIFFERENTIAL PAIR WITH EMITTER DEGENERATION

Liriearization. throtigti the lise of emitter deçencration. c m be rione in one of two ways. The two

possible implementations are stiown in Figure 5.11

:\ qualitative cornparison of the two crnitter degeneration rnethods is summarized in Table 5.2.

In order to decrease the supply voltage, and iricrease the linearity of the circuit, Circuit #2 was

iiseci. The analysis that follows is for Circuit # 2. but similar analysis can be used for Circuit # 1.

Table 5.2: Cornparison on the use of Emitter Degeneration in a Differential Pair

Figtrre of .\lent b-oltage Supply

Signal Feed t hrough to Current Sources

Lineari ty

COmpansori Circuit # 1 ilas a larger supply

Circuit # I has a srnaller îèedthrough

Circuit #2 is more linear

Discussion The voltage drop across the cmitter de- gcneration resistors in Circuit # 1 limits the minimum supply voltage Circuit # 1 lias n smalier feedthrough since the node at which the current source is connected is a virtual ground. in Cir- cuit #2 each current source experiences the entire input voltage swing. For the sarne voltage supply, the base- collecter junction voltage of transistor Q 1 and Q2 is Larger in Circuit #2.

; i j Caprio's Quad -

b) Diode Loadeci Ditfcrential Pair - - - -

'8 198 TT ii A

c) tiaranicolas' Foldcd Diode Load Differential Pair

Figure 5.10: Ot,her Input Buffer Circuits

..\pplying KVL to the input of C'l'ircuit $42:

wliere Ai represents t tie signal current. Using the Taylor scries for the arç tanh(-) function:

In order to obtain the output ciment as a function of the input voltage. the series in eqiiation

.5.18 needs to be reverted. .-ipplying[l'L]:

1 where --lL = -

a1

CfIAPTER 5. TR-iCK -4ND HOL D

a) Circuit # 1 bf Circuit # 2

Figiire 5.1 1: Emittcr D~genertition

t.o cqiiation 5.18. ancl oniy keeping the first two terms:

The differential output voltage can be wri t ten as:

Cising the third order harrnonic distortion as a figure of rnerit for the linearity of the differential pair

wit h emitter degeneration.

This demonstrates that through the use of an ernitter degeneration resistor, the harrnonic dis-

tortion can be decreased. In general the region of linearity is approxirnately equal to I E E RE [IO].

CH-4PTER 5. TRACK -4iVD HOLD

5.3.2 DIODE LOADED DIFFERENTIAL PAIR

The schematic of a diode Ioaded differential pair is shown in Figure 5.10 b). The differential output

voltage (Al,&rT) and current (Ai) crin be written as:

Substituting 5.31 into 5.30.

Equation *5.33 demonstrates that the diode loadeci differential pair is a very lincar circuit. In

practicnl realizations. the linearity depends on the matching of the diodes to the transistors of

the difkrential pair. Fiirthcrmorp, the nrctanh(tanh(.) ) relationship breaks down. since for a large

input voltage. the diode current is not esponcntially related to t h diode voltagc (i.e.. a t tiigh currcnt

levels) and equatioti 5.32 no longer applies.

111 order to increase the linear range to a grexter rxtent ernitter degeneration needs to bo titilized.

.-1 schematic of the input buffer used is stiown iri Figure 5.12.

In the circuit design. a large emitter area is selected to minirnize the noise ancl offset. Also. by

utilizirig a Iarger transistor size for the differential pair and diodes. the liriearity is irriproved. since the

even harmonic distortion products are supprcssed due to the irnproveci rnntchirig. Many simulations

were done in order to determine the combination of b i s current and emitter degenera~ion which

satisfies the linearity requirements. X plot of the clistortion ai a function of emitter degeneration

and bias current for a LLz>, inpiit signal is shown in Figure 5.13.

[n order to obtain a linearity of < -65dB. it was found empirically (see Figure 5.13) that

lEERC 2 0.5 V . The selection of the bias current and load resistor was dictated by the acquisition

time. .As was discussed in Section 5.2.2, one of the deterrnining factors in the srnail signal bandwidth,

and thtis the acquisition speed. is the load resistoi'. The load resistor sclection is dictated by the

bandwidth that is needed, whiIe the bias current is selected so that the Iinearity requirement is met.

" Rt in Figure 5.4. is equivalent to RC, in Figure 5.12

CHAPTER 5. TR4CK AND HOLD

Figurc 5.12: Input Buffer Utilized in the 'i'rnck ancl Hold

5.4 SWITCH

The sivitched enlitter Follower (SEF) will be rliscussed in this section. .4t thc beginning of this

diapter, a n analysis of a single-ended SEF wcw presented. The arialysis is esterided to the ciifferential

irriplemeritation in the Sollowing sectiotis. 'Ttic clifferential linearity, ~ l e w rate. pedestal tirror and

feeclthrough are disciissed. The design of the SEF titilized in the tracrk srid hold are reviewed and a

riew technique that overcomes some of the limitations of the SEF is presenteci.

5.4.1 DIFFERENTIAL IMPLEMENTATION OF A SWITCHED EMIT-

TER FOLLOWER

A circuit diagram of the differentia1 irnplementation of the switched emitter folfower is s h o w in

Figure .5.14.

Following an analysis sirnilar to that in Section .5.2.2, it can be shown that:

S'leu1 Rate = ~ I E E - CH

Feedthrough : AVocrT = cj z

cje + CH WIN

CH-IPTER 5. TRACK -4ND HOLD

-85 L I I

50 100 1 50 200 250 Emitter Degeneration [ i Z ]

Figure 5 . L3: Distortion of the Input Biifler .as 3 Function of Bias C'iirrent and Emitter Degeneration

In a différentia1 topology. the pedestai error is riullified due to the eqiial hold steps nt l & y T and

\ ,OuT. Mismatches in the bias current ( IEE) and hold capacitance (CR) cause a differential hold step

in practice. Furthermore. due to differences in the instantaneous operating points of the individual

switches, there will is a finite difference in the switching time (ToFF) and this aIso contributes to a

pedestal error.

Another important factor that has not been addressed up to this point is the linearity of the

emitter follower. The emitter follower is the most linear of the basic single transistor topologies

(Le.. Common Emitter, Common Base and Emitter Follower) but nonetheless it still cxhibits sorne

nonlinearity. The differential output voltage AL/ocT in the rack rnode%an be written as.

5This expression is valid only after the circuit h a reachcd its steady state opemting conditions

CH-WTER 5. TR-ICK .AND HOLD

Figure 5 .14: Differ~ntinl irnplementatiori of the Switched Emitter FolIower

Where i,., is the signal current iiowing through

cari be shown to be:

the capacitors. 'The third ordcr hnrrnonic distortion

T'lie cxpacitor signal current can nlso bc writtcn in ternis of input voltage 1;. or f~qiiivalently ris:

rvhere C i ( [ ) = I~.v, , .s i t i (2a f r . v t ) . Thus. the peak iiurrent is given by I n fr.vL,j.v,Ç,r. Siihstituting

this into equation 5.39, the harrnonic distortion çan be writteri as:

In order to niaxiniize the linearity of switched emitter follower during the track mode. the ratio

i c I f / I E E must be minimized. This is accomplished through the use of a large bias current and a

srna11 input voltage swing ( çjivp ), small hold capacitor (Cr[ ) and low input frequency ( flLv ).

5.4.2 SWITCH DESIGN

in the design of the switch various parameters play an important role in its performance. Some of

the important parameters are the hold capacitor (CH), ioad resistor (RL), bias current ( I E E ) , and

SE F transistor size.

According to equation 5.4, to reduce the feedthrough, a srnaIl emitter area is needed for the

CH-4PTER 5. TRACK -4iVD HOLD 69

SEF so that Cje is minimized. By selecting a small transistor size. the range of values that can

be selected for the other parameters is limited. The bias current (IEE) OF the switched emitter

follorver is limited to the maximum current density of the transistors: which lirnits the slew rate.

Fiirthermore. recalling equation 5. L6, it places a limitation on I E E R L . Therefore. by minimizing the

transistor emitter ares. the minimum resistor size which turns off the SEF transistor increases. and

with it the srnall signal bandwidth.

In order to minimize the feedthrough and niaximize the banciwidth independently of each other

another design variable is neeclecl. By adding an nclditional design parameter. it is en-sier to satisfy

~tie ciesireci specificacions. che circuit perforrns better. and it is more robust with respect to variations

in the process. The rierv circuit is shown in Figure 5.15 .

CLK

&,,"IN

Figure .ï, 1.5: Single Ended View of the Yew Switch

in this circuit an extra ciment steering differentiat pair is added. This differential pair aicis in

turning off transistor Q 1. For the new circuit. equation 5. lti (:an be re-writtcn as:

From equation 5.42, it is apparent that there is an extra degree of freedom in the selection of the

load resistor (Rt ) and the SEF bias current ( I E E r ), due to the presence of L E E ? . The circuit can

therefore be designed to rnaxirnize banciwidth by selecting a small load resistor ( R L ) , while at the

same time utilizing a srnall emitter area for QL. This extra degree of freedom cornes at the cost of

increased complesity.

With regard to feedthrough, there is no performance improvement in a differential circuit (corn-

paring 5.35 and 5.4). However through the use of feedforward capacitors, signal feedthrough can be

nullified[25]. Figure 5.16 shows the switches in hold mode, with feedforward capacitors.

Figure 5-16: Capacitive Feedforward to Redum Feedtlirough

T h diffcrential tëecltliroiigh is now given by:

Setting C', = CL, nullifies the feedthrough. The compensation capacitors are realizecl iising a bnck-

to- bnck connection of p t i junctions <as shown in Figure 5.17. [ri tliis way the jtinction capacitances

and feetiforward capacitances arc matched.

OUT

a) Circuit b) Modrl

Figure a.17: Realization of Compensation Capacitors

In practice the feedthrough is not compieteiy eliminated due to the voltage dependence of the

base-emit ter junction capaci tance. Furtherrnore, transistor mismatches in the junction capacitances

cause differential feedthrough.

.4 diagrarn of the cornplete switch is shown in Figure 5.18. The current source used in the input

buffer is used in the switch as well.

Figure 5.1s: Swittrh useci in the

5.5 OUTPUT BUFFER

The piirpose of the outptit btifkr (.-Y2 in Figurc 5.1

j

J SL:PPLY 1 SL!PPLY 1

Track and Holrl Circuit

) is to isolate the hold cnpacitors froni the

siibseqiient circuit blocks. 'The clroop rate of the track anci hold is limited by the m t p i ~ t buffer

5.5.1 DESIGN OF THE OUTPUT BUFFER

.-1 clifrcrential pair with emitter tlegeneratiori ( R E ) (:an be iised as an outpiit brifkr. The rfifferentinl

bCwe t:urrent and corresponding droop rate for this circuit is:

Wliere AlB and Alc represent the differential base and collecter current respectively. Comparing

equations 5-47 and 5.12. it can be seen that the differential droop rate will be smalIer chan the single-

ended droop rate For the same sized hotd capacitor and transistor bias current. since AlB < IB.

.A design esample will help dernonstrate why this circuit can not be used as the output buffer.

.Assurning that the differential input signal swing is 1 Ilpp, with a current gain (3) of 100. tiold

capacitance (CH) of .?O0 fF, sample rate of 1 GHz. and a rnaximumdroop rate of 1 pC,*/ps (see Table

5.1) the degeneration resistor ( R E ) must satisfy:

CVhiçh is a relatively large resistor for a Iiigh-speecl/wide bandwidth circuit. :\ 10 kQ emitter

resistor will decrease the bancfwidth at the collector nodes, and introduce a significant arnount

of thermal noise. thereby reducing the sensitivity of the trnck and hold. comparator combination.

Furtherniore. it is difficult to realize stich a large resistor d u c because of tlie low stieet resistivity

of the thin film resistor in the HBT proccss.

From eqiiation 5.4'7 it cnn he seen that tlie droop rate is iriversely proportional to the current

p i r i of transistor. 'Thus. n Inrgc currcnt gain minimizes the cfroop rate while mairitaining rt

reasonably sized cmittcr tlegencrntion resistor.

Figure .5.19: Output Buffer

The circuit shown in Figure 5.19 improves on the emitter degenerated differential pair in two

ways. In order to rninimize the droop rate. the current gain has been increased through the use of

Darlington connected transistors. Furthermore, in order to minimize the effect of the finite output

resistance (i-e.. r,) of the input devices (QI,Q2), the current signal frorn the inner differential pair

(Q3,Q4) has been fed back to the colIectors of Q I and Q2. This keeps the collector emitter voltage

. .;i)Om -2LdL?m 2d0m o J k h

Input Voltage V

Fiçurct 5.20: C'ollector ancf Eniitter Voltage and Differeritial Base C'iirrent in Q 1. Q2 of the Output Biiffer

(Sonstant for d l input signal voltages. A plot of the collector ancf erriittcr voltages for Q 1, Q2 and the

differential base ciirrent (AIs ) with this ncw topology is stiown in Figure 5.20. The coltector voltage

follows the ernitter voltage. ancl thiis the collecter-ernitter voltage remains constant. 'f hrough this

rnechanisrn the îi nite oiitpiit irnpcdiince of the input devices is cornpensated for.

Anotlier rnechanisrn liniiting the droop rate is the finite outpt~t impcdance of the current sources.

in order to rnaxirnize the output impedance of the current sources. a cascode current source was

irtilized. The c,wcode current source iised is shown in Figure 5.21 a ) .

In order to masimize the currerit gain in the o~itpiit buffer. the bi's current was maxirnized. It

i vas maxirnized since the current gain increases monotonically with current. as shown in Figure 5.21

b). The bias current can not be increased without bound since the base-collecter nodes of QL and

Q2 will becorne forward biased, and the transistors wilt enter the saturation region.

5.6 CLOCK BUFFER

The cIock buffer isolates the dock signal from the high frequency base charging current of the current

switches in the track and hold. .A pulse forming circuit w a used in order to maximize the dew rate

of the dock signal a t the zero crossings.

v SUPPLY

v b SUPPLY

t a o u I O O O U I O *

a) Cascode Ciirrent Source b) Current Gain ( 3 ) as a Function of C'ollector Current

Figure .5.21: Current Source and Current Gain

5.6.1 DESIGN OF CLOCK BUFFER

In the comparntor's dock buffer (Figure 4.13) emitter followers arc u s ~ d for ievel shifting and buffer-

ing of tlie dock signal. .-Uthough this topoiogy provides buffering. it sirnply passes the clock waveform

to the current switches. Emitter followers do not gcnerate a pulse signal for the ciirrent switches.

In tlie trnck and hold circuit. a putse-forming circuit ['L6] is tised to rnaximi~e the slew rate of

the dock signal at the zero crossings. A circuit diagram of the dock butfer irtilized in the track and

hoid circuit is shown in Figure 5.22.

In the circuit sliown in Figure .5.12. transistors Ql-QG perforrn a sinusoid-to-square conversion.

Transistors Q3-Q6 form a positive feedback loop. The operation of this loop is very simiiar to that

of the regenerative latch and generates a, 1 GHz square wave. Transistor Q7-QLO level shift the

signal in order to d.c. couple the buffer to the current switch used by the SEFs. Xs was discussed

in section 4.5.1.1. the emitter foIlowers have a tendency to ring if proper care is not taken. Through

the use of a compensation resistor ( R E F ) , the ringing is minirnized. Furtherrnore, t he bias current

fiowing through the emitter followers rnust be large enough to drive the current switches at a speed

that is cornmensurate with the slew rate of the interna1 positive feedback loop.

CHAPTER 5. TR-ICK .4ND HOLD

Figure 5 .22 : C'lock Butfcr L'tilized i r i the l'rack ancf HoId

5.6.1.1 ANALYSIS OF CLOCK BUFFER

Following analysis similar to the regenerative Intch, it can be shown tliat when the r:lock biiffer is

initially in its linear region of operation. the output voltage is:

where represents the initial outpüt voltage. Equation .5.+50 is very similar to the tirne

response of a regenerative latch (see equation -1.6). Similar to the regenerative latch. the speed of

the circuit is dependent on the unity-gain bandwidth. Hence. similar design methods c m be utilized

to optirnize the speed of the circuit. However this circuit can be switched from the positive state,

(or negative state) under the control of the input signal, Al;rLv. This is what creates the sinusoid

to square waveform conversion.

The analysis that follows will demonstrate how the circuit c m be controlled by the input signal

to switch from the positive state. to the negative state, or vice-versa. It mil1 be assurned that the

circuit is in the positive output voltage steady state. A simplified circuit mode1 in this state. with

a srnall negative input voItage is shown in Figure .5.23. - .As can be seen [rom the Figure 5.23 the differential output voltage ( A b v T = - VariT)

is positive. Transistor Q4 is on while Q3 is off, hence al1 the current from IEE2 flows through Q4.

Figure 5.23: Mod el of the Clock Buffer with a Positive Output Voltage

- 44 is modrled .as a iinity gain ciirrent buffer. independent of tlic voltage at I;"~ or Ils. whilc (I3 is

mocleled as an open circuit. In orcler to change states. the vultage ,it the bases of Q3 and Q.4 must

be changeci such that Q4 is ori and Q3 is off. At the threshold. the voltage at the base of these

transistors are approxirnately equal. and the circuit is in the liriear rcgion. Any srnall. negative input

signal will cause the positive feedback circuit to qiiickly toggle to the negative stattr. With this in

mind. the voltage at the base of transistors Q3 ancl Q4 can be written 'as:

In order for Q3. Q4 to change to a negative output signai:

Under this condition, equation 5.5 L becomes:

If there is sufncient gain (i-e., g, RF), then for a negative input signa1 ( A b L v ) , the clock buffer

will Iatch to the negative state. The worst case scenario is that the clock buffer has not switched

states by the time that the input signal f reaches its maximum input voltage. In order to

place a minimum on bound the gain, consider the case where the input differential pair (Ql,Q2) is

fully switched (i.e., maximum input signal). With this input, equation 5.53 can be written as:

This demonstrates that for proper operation. guaranteeing botti positive and ncgative pulses. the

feedback resistor RF needs to be Iarger than the load resistor.

The transistor biCw current and load resistor sizes were selectecl <as was done t'or the regenerative

latch. Ttie voltage swing is selected so chat the (rurrcnt driving the switched emitter followers is

siitFicicnt to toggle the circuit on and off despite process and tempcrntiirc variations. ï h i s stage is

iised to drive ttic ctirrent switches in the track and M d . and the comparators in an ADL.

5.7 OUTPUT DRIVER

'i'he Iast stage of the track and hold circuit is the output driver which drives the drive the 50 12 loads

and the output capacitance of the instrurnentatior~ in the test configuration. A sdiernatic dirigram

of the circuit is s h o w in Figure 5.24.

In contrast to the output ciriver used in the comparator. linearity is a concern in this circuit.

and thus emitter degeneration is used. The emitter degeneration resistors are in series with each

transistor in order to circumvent the possibility of thermal runaway due to the large current densities

flowing in this circuit. The collecter-emitter voltage voltage of the transistors in cascade (i.e.. Q5.Q6)

kvas selected such that the transistors remained well into the active region of operation in order to

minimize non-linearity. Transistors Q3 and Q4 of the differential pair placed a constraint on this

voltage, as they shouid remain in the linear region.

' ~ h i s is a reasonable approximation in a pnctical implernentation of this circuit

OUT

Figure .5.2-1: Output Driver iiseci in t h e 'l'rack ancl Hold Circuit

5.8 SIMULATION RESULTS

This ctiapter will disciiss the siniiilation rrsiiits of the tracli nncf hold. The testbenches utilized to

ûbtain thcse rne,wurements arc cf iscumecl.

5.8.1 HOLD SETTLING TIME

The hold settling time is defincd CU the tirtie needed by the track and hold to s'ettle to within 0.5 LSB

of its final steady state value wtien i t is switched into the hold rrioclc. This is an important figure

of merit since ir, will cleterrnine how long the subsequent quantizing cirtruitry (i.e.. coniparatorfs))

musc be delayed before they are strobed to enter the latch state. The rnethod used to obtain this

rneasurernent is described below.

i ) -1 d.c. voltage is applied at the input terminal of the track and hold circuit.

i i ) The circuit is placed initiaily in the track state.

iii) The circuit is then put into the hold state.

A d.c voltage was applied to the input of the track and hold to suppress the feedthrough. Thus,

the error that appears at the output is due to the finite settling time of the circuit rather than the

Feedt hrough.

The hold mode settiing tirne is also signal dependent. This signal dependence is due to the

signal dependent operating point of the switches. This signal dependence can be best dernonstrated

CHAPTER 5. TMCKAlVD HOLD

Table 5.3: Simulated Hold Settling Tinie as a Function of the Input Signal Amplitude

through an example. Consider the case when the input voltage is zero.'. I;i (refer to Figure 5.14)

is rising (F is falling) and the circuit is in the track mode. Thus. switched emitter folloiver QI. in

Figure 5.14 is sourcing current. On the other side. emitter follower Q2 is soiircing Little current since

Q5 is sinking current from the capacitor C f l . Thus Q 1 will take longer to turn off tlian Q2 due to

charge storage efiects. .-1 representative plot of the hold settling time rneasurement and the signal

ckpcndence of the sarnpling point are shown in Figure 5.25 and in Table 5.3 respectively.

Input Voltage m V A a00

t l Clock Hold Srttling Edgc Timc

- Hold S e t h g ~ h p s -

248

Time s

Figure 5.25: Hold Settling Time and Droop Rate

5.8.2 ACQUISITION TIME

The acquisition tirne is defined as the amount of tirne needed by the track and hold to recover to

within 0.5 LSB of the final steady state value when it is switched from the hold to the track state.

' ~ h e current through the capacitor is the derivative of the voltage. Hence for a sinusoida1 input the largest current occurs at the zero crossings

The worst case scenario occurs when the hold signal is at the most negative (or positive) state and

the input signal is positive (or negative) just prior to entering track mode. In this design. where

there is an input voltage of 1 C , i P in a 10 bit system, the track signal must be within i500pV.

The method in which the acquisition time wu mtasured is summarized below:

i j .-1 ftill scale ( 1 C . i p ) , half-Xyquist frequency (500 MHz) input signal was applied.

ii) The track and hold is initially placed in the track (unity gain amplifier) mode for a time.

TTnAcr\. . This served as the reference, steady-state signal.

i i i ) Tlie circuit is then operated as a truc traçk and hold (i.e.. switched periocfically from the track

to hold state).

i v ) The acquisition time iç the tinie required to settle to rvithin 5OOpC.' O S the firial steady-state

signal. when it is switched from the hold to track state.

.-i plot of the error voltage as a function of time is s h o w in Figure 5.26. This l a t figure

demonstrates that the acquisition time of the trnck and hold WC; npprosirnatt.ly 220 ps.

Figure 5.26: Error Voltage During the Acquisition Phase of the Track and Hold

Table 0.4: Simulated Pedestal Error as a Function of the Input Signal Aniplitude

5.8.3 PEDESTAL ERROR

Input Cdtage m C.' .500

The pedestal error is a mesure of the step in voltage when the transition to the holcl mode is made.

This pedestal error is also signal dependent[ll]. This signal dependence can be nonlinear. due ta the

nonlinearity of the base-ernitter junction capacitance. I f the step is linearly dependent on the signal,

then the rrror that occiirs will appear as a gain error at the output. which cati be c-ornpensatecl for.

in order to determine the pedestal error the following rnethod w u irtilized:

Pedestnl Error m k' 0.982

i ) A ci.(:. voltage is applied at the input terniinal of the track and hold circuit.

i i ) The circuit is initially placed in the track statc.

i i i ) The circuit is theri strobed to enter the holcf state.

iv) The peclestal error is the change in the output voltage frorn just before. to just riftfer the circuit

enters tfhe hold state.

v ) The d.c voltage applied nt the input terminais is changed, and steps ii-iv are repeat,ecl in orcler

to chararterizc the circuit over the (romplete signal range.

.-1 d.c voltage is applied in order to measure the pedestal error independent of the feeclthrough.

Table .5.4 surrimarizes the pedestal error for varioiis input voltages. In Figure 5.27 an example of

the pedestal error is presented.

.As can be seen from Table 5.4, the peclestal error is symmetric about O V. and had a. maximum

value of 1 mV. or 1 LSB.

5.8.4 HOLD MODE FEEDTHROUGH

The hold mode feedthrough is a measure how much of the input signal appears on the hold capacitor

during the hold mode; it is a measure of isolation. The method in which this figure of merit was

measured is outlined below:

i ) A full scaie (1 Gp), half-Nyquist frequency (500 MHz) input signal is applied.

ii) The circuit is placed in the hold mode for the entire simulation.

CHAPTER 5. TR-ICK .AND HOLD

TRACK - : PEDESTA& ERROR t

HOLD

J - 1 ,Jn : ! Z r 1 .'.Jc g 5dn l i Z n I 'J-

Time s

Figure 5.2'7: ïrack and Hold Pedestal Error

i i i ) The differential peak voltage is rneasured.

The definition of feedthrough is:

Figure .5.28 shows the simulation results of a feedthrough test. The feedthrough was -52 dB.

This is larger than the desired specification. X method to improve this figure of merit is presented

in the final chapter of this thesis.

5.8.5 DROOP RATE

The droop rate is a measure of the linear decrease in the differential output voltage due to the

discharge of the hold capacitor. The test bench used to measure the droop rate is similar to that

used for the hold step. Furthermore, since the droop rate is not be dependent on the frequency of

the input signal, the input signal can be a t d.c. The method used to measure the droop rate is

outlined below.

i ) A d.c. voltage is applied to the input terminais.

CH-4PTER 5. TR-ICK .4hrD HOLD

Tnck *

Time s Time s

Figure 5.28: ïrack arici Hoid Feedthroiigh

i i ) The circuit is initially placeci in the track state.

i i i ) The circuit is then strohetl to enter the holcl stnte.

i v ) The droop rate is the linear decrease in the hold voltage after the hold step.

V ) The d.c voltage is ctianged, and steps ii-iv are repeated.

The worst-case droop rate will occur at the positive and negative full scale voltages. Table 5.5

summarizes the droop rate as a function of input voltage. .4 representative plot from the simulations

is shown in Figure 5.25.

5.8.6 DISTORTION, NOISE AND SINADIENOB

The distortion and noise performance of the track and hold determines the dynamic range of the

circuit. The distortion places an upper limit on the input voltage swing, and t h e noise determines

the minimum detectable input signal.

The distortion of the track and hold is determined from the distortion of the held values. since

these voltages are subsequently quantized by the comparators. in order to experimentally test the

Table 5.5: Droop Rate as a Function of the Input Signal

Table 5.6: Track and Hold Distortion Tests

Two Tone. Spectrum of entire output.

Single Truck and Hold Single Tone. Spectrum of Held Values

ï w o Tone. Spectruni of only the heId values.

distortion of the track ancl hold. a niaster-slave nrchitecturc is typically used (see Figure 5.30 on

page ~ 8 ) [ % . 271. In the muter-slave architecture. the master track and hold is operating nt the

full sarnpling frequency (f, ), while the slave is operated at half this frequency (f, /2 ) . The input

signal is a full-scale signal at a freqtiency slightly higlier than the Yyciuist frequency. or /, / 2 + h f .

Through proper timing of the master ancl slave track and hold clocks, the output signal consists

of the frequency A/ ancl al1 of the harmonics. 2Af. 3A f. + - . . + AI. Thus. due to alirising in the

second track and hoid, the signal is downconverted in frequency. Since an audio spectriim arialyzer

.Claster-Slave Tmck and Hold Single Tone. Spectrum of entire output waveform

(:an be tised this type of structure is useful for the experimental testing of track and holcfs.

[ t is interesting to note that if a two tone test is used. a single track and hold can also be used

to experirnentally test for the cfistortion of the track and hold. This is because the sine(.) function

present in the output spectrum of a track and hold is not an issue, since the intermodulation

components lie close to the fundarnentals. Titus, each of these components experience the same

filtering from the sincf.). Cornpareci to the master-slave single tone test discussed previously, there

is no slave track and hold present, which adds tc~ the distortion of the overall systern. Hence. a two

tone test in a single track and hold can provide a better approximation to the distortion of the track

and hold. This two tone test, dong with the master-slave track and hold are discussed in more

depth in Xppendis B. .4 computer simulation environment greatly simplifies testing for distortion.

In a simulation environment. the distortion of the track and hold can be found by sampling the

hold values, and then applying the Fast Fourier Transform (FFT) to measure the THD. This test

was used extensively in the simulations. A summary of the testbenches utilized to determine the

distortion in the track and hold is shown in Table 5.6, with a summary of the results listed in Table - - a.(.

Frorn tabIe 5.7 some observations can be made. The barmonic distortion of the two tone test,

CH-4PTER 5. TR4CII' AND HOLD

Table 5.7: Summary of Distortion Tests

Distortion Test Two tone test at 440 MHz. and 460 MHz. of a track and hold, clocked at LCHz. Spectrum of only the held values. Two Tone Test at 440 MHz, and 460 MHz. of a Track and tlold, ciocked at 1C;Hz. Spectrum of the entire waveform. Single tone test at -100 MHz. of a track and hold, doçkeci at 1GEIz. Spcctrum of only the held values. Single tone test at 900 MHz. of a track and hold. clocked at 2CHz. Spectriim of only the held values. Single Tone rit Test at 510 MHz. of a Master-Slave Traçk and Holcl clocked nt 1 C t I x .

ID3 after Output Driver. 4.5 dB

THD before and after -73 and -6.5 dB output driver.

THD before and after -73 ancl 44.5 dB output driver.

THD before aricl nft'ter -+L and -5 l j ciR Output Driver.

and that of the single tone test are roughly the sanie. 'i'lius the third order harrrionic is the dortiinant

distortion term. F~irthermore. it is evident that the output driver contributes a large portion of the

clistortion in the entire systcrn. as is demonstrated by the large degraclation before and after the

output driver in the tests. 'I'liis output driver would not be present in a monolithic iniplernentation

of the ADC and thus its poor performance is not a large concern.

The clistortion of the track and hold is not the only concern in determining tlie track and hold

SIN.-lD[15. 161. Some recent papers have defined tlie EXOB of t h e track nncl hotci basecl on the

THD(25. 26. 271. However a stricter. and more difFicrilt definition. nlso takes into account the noise.

Since the track and hold ticas two modes of operation, track and hold. it is riifficult to rietermine the

noise performance. The noise is best determinecl during the traçk mode. since in this mode there

are more iioise sources. The noise of the track and hold was !IBO p V . at room temperature. tking

4 5 dB as the T H D of the track and hold8. the SE."j:ID and ENOB are:

O :1507 3'1.V.4D = = .53.3 d B

%Op 1/" + 125pV2 Sl.V.4D - 1.76

E:VOB = = 8.6 bits 6.02

This result falls short of the desired 10 bits, but if the TCID is used to determine the ENOB['LS,

26, 271, then the track and hold is well above ( 1 l.8 and 10.5 bits before and after output driver

respectively) the design specification.

For experirnental testing, a single crack and hold and a master-slave track and hold were designed

'The THD of the single track and hold, after the output driver was used with, with a sarnpling frequency of 2 GHz

and are currently being fabricated. A single track and hold was irnplemented to determine the

acquisition time, pedestal error, etc., as well as the distortion of the track and hold from a two tone

test. A master-slave track and hold was also designed in order to test for distortion['L5. 26, S i ] .

5.9 TRACK AND HOLD LAYOUT

The entire track and hold. and master-slave track and hold at the block level is sliown in Figure 5.29

and 5.30. with the layouts shown in Figure ;.:31. In contrat to the coniparator design. the track

ancl Iiolcl h e s nnt. lise e s t ~ r n a l reterqye reistors. This was done in crder to reduce the numbcr of

external çornponents needed. The niaster-slave design is the c,?scnde of two track and hold circuits.

The same precautions as those used for the cornparator (see Section 4 3 ) were addresseci in the

layout of these circuits. In cornparison to the layout of the cornparator, tlie track and hold layout

represents ri large imprcvement in thermal and elcçtrical symrnetry. Extreme cnrc was taken to

n-inintain thermal syrnmctry at the cost of increased layout area. 'The layout of the Iiolcf capscitors

is also c-ritical. For symrnetry, and to rninimize the offect of the parasitic siibstrate cnpacitance. the

sigrials (positive ancf negative phase) were applied to the top plate of the capacitor. rincl the two

capacitors share the same bottom plate. in order to rnininiizc tlie iriductnnçe present at the bottom

plate of the hold capacitor, a siibstrate vin w,?s uscd. This siibstrate via makes a çonnection to the

bottom plate rnetallization and provides n very low inductance path to groiind.

5.10 SUMMARY

In tliis chapter, the theory, design and simulation of rr track and Iiolcl for iisc in 1 (;S/s. 10 bit

ADC were presented. It w a s sliown that through the use of a novel current switch (Figure 5.15)

the design tracleoffs in the design of the SEI: were relased. Furthermore. through the use of a novel

output buffer, the effect of finite output impedance of the transistors is eliminated. nllowing for very

low droop rates (Figure 5.19). Furthermore. the theoretical analysis and desigii of a pulse forrning

circuit were also discussed. .-i summary of the track and hold simulation results is given in Table

5.8.

CH-4PTER 5. TR-ICK . W D HOLD

Table 5 . 8 : Surnrnary of Track and Hoid Figures of Merit

Figure of . \ l en t

tlold Settling 'rime Acquisition Time Pedestal Error Feect throiigh T H D with a 1GHz dock

Yoise SINAD at 2 G H z dock ENOB at 2 Ci Hz dock Droop Rate Track and f-Iold Active Xrea Mwter Slave Traçk and Hold Ac- tive Ares Power Consumption without dock buffer, and output driver Power C'onsumption of entire circuit Power Supplies

2-18 ps 220 ps 1 mV

-5'2 dB -73 d B and -6.5 dB. before and af- ter outpiit driver respectively. -73 d B ancl -tj4..5 ilB. before and after out put driver rcspeçtively.

c360pV 53.3 B

8 .t; < -100 pV/:'iOOps 1800 x 450 :!:IO0 x -150 prri'

Desr red ~'pecif i - cntton

<500 ps <500 ps

10 bit linearity <-tj0 dB

Figure 5.29: Trnck and CIold

Track and Hold 2

IN 'OUT

Figiiro .5.30: 5Iaster-Slave Track and CIolcl

Track and Hold Master-Slave Track and Hold

Figure 5.31: Layout of Track and Hold and Master-Slave Track and Hold

Chapter 6

FUTURE WORK AND

CONCLUSIONS

6.1 FUTURE WORK

'The next few sections will be devoted to t he improvements that c m bc made to the comparator 2nd

trnck and hold.

6.1.1 COMPARATOR

The comparator is capable of operating up LO 3 GHz . but the sensitivity of this circuit is not

cornmensurate with that of a 10 ENOB system. which requires a BER of 10-' or less. To achieve

this BER. the total equivalent input noise voltage in the cornparator must be less than 200 pl'. In

order to achieve this. the bandtvidth can be decreased. and as a result the arnoiint of noise in the

q s t c m will follow suit. Furthermore, the use of larger transistors will reduce the noise introduced

by these circuit components a t the cost of increased power. In conclusion. more design effort should

be placed in optimizing the noise performance of the cornparator. since it is known that the speed

of the chips easily meet the specification.

6.1.2 TRACK AND HOLD

Unfortunately, due to a deIay in fabrication. the track and hold is not available for testing. The

esperimental resutts are a more important indicator of what irnprovements neecl to be made, but

nonetheless some modifications to the circuits used in the track and hold are described in the next

few sections.

C'K-4P TER 6. F UTLrRE W0R.K .-\ND CONCL USIONS

6.1.2.1 TRACK AND HOLD SWITCH IMPROVEMENT

The design of the current switch that was used in the track and hotd was presented in Figure 5.18.

The cornmonly used current switch was altered by adding an additionaI current switch in order to

facilitate the design of the track and hold (refer tu Section 5.4.2). A simpler method to implement

this design is shown in Figure 6.1. This circuit eliminates the need for a red~indant current source.

I t also greatly simplifies the layout of the circuit due to the elimination of the extra interconnect

needed by the previous design.

Figure 6.1: Irnproved Ciment Çwitch

6.1.2.3 TRACK AND HOLD FEEDTHROUGH REDUCTION

In the design of the track and hold. it was found that it is difficult to obtain a feedthrough less

tlian ($0 dB. in order to reduce the kedthrough. equation 5.3.5 prcdicts that there are three design

variables under the control of the designer. Two of them are used in the design of the track and hold:

the switch junction capacitance (Cm',,). and the hold capacitance (CH). in order to minimize the

Feedthrough to a greater extent the voltage swing must be decreased. The swing can not be altered

during the track mode. but it can during the hold mode. One way to minimize the voltage swing

is described in a recent paper by Baumheinrich['2rJ. This scheme is shown in Figure 6.2. Through

the use of A3, which has an equal but opposite gain to that of A'L. the voltage a t the terminals of

the load resistors RL is nullified, in the hold mode. The performance improvement achieved in this

approach is limited by the matching between the two gain stages ( A l and X3).

LOAD

Figure 6 . 2 : Feeclthrough Reduction

6.2 CONCLUSION

This thesis has presentecl the theory. design and experimental results of a cornparacor. and the

theory. design and simulation results of a track and hold for use in a 1 GS/s. 10 bit ADC. The

experimental resiilts of the çomparator, and the simulation results of the trnck and holcl inciicate

tliat 8.6 EYOB. with a BER of 10-" is achievnblc ot 2 C;S/s. if the ENOB is ilefined according to

t he T H D . and a 10-"ER is accep~nbiel then I O ENOB c m be açtiieved nt 2 GS/s.

--

'This is suitable for voice communications.

Appendix A

APPENDIX A

PROBABILITY ERROR THE LATCH

It ww seen that for srnall signal levtl.1~. the oiitput of the latch esliibits a randoni hehavior. in tbis

section the probability of error <as a funrtion of the signal to noise ratio will be lookcd at. [ t will

be assunied that the offset can be compensated. Let the initial signal level across the latch be S.

Furthermore 'assume tliat the noise in the systeni can be niodeleci by a Gaussinn ranciom variable

Y. witlz a niean of zero. and power of a'. 'l'he initial voltage ncross the latch (E,') wiil be the linear

superposition of the signal S. and the noise Y. 'ïhere will be an error in the output of the latch if the

noise is large enoiigh to cause the initial voltage to change froni a positive (or negative) voltage to

n riegative (or positive) voltage. Due to the symrrietry of the Gnussinn function it can be assurneci.

without loss of gencrality that the signal is a positive voltage. Thiis the probability of error can be

written as:

The solution to equation A.1 can be written in terms of the Q-function, for which a table of

values exists[lï].

A table of the required Signai to Noise (S/a) ratio. for a desired probability of error is s h o w in

Table A I . The Bit Error Rate (BER) can be used to quantify what is meant by a quoted sensitivity

for a cornparator. For example, a specification could be: The cornparator sensitivity was 2 mV, for

a BER of 10". In order to determine the sensitivity a Bit Error Rate Counter needs to be used.

An oscilloscope can only provide a qualitative measure of the number of errors occurring.

Table A. 1 : Signal to Xoise ratio needecl for n given BER

Appendix B

APPENDIX B

B . l COMPARISON OF SINGLE TONE AND TWO TONE

THIRD ORDER DISTORTION COMPONENTS

This section wil l dernoristrate that s two tone test can provide an estimate to the single tone. third

order harmonic distortion ( H D 3 ) , and to the total harmonic distortion (THD) . C'orisider a system,

whose input-output relationship cari be dcscribed by the following:

If a single tone of amplitude .-\ is appIied to tliis system it can be showri tliat the ratio of the

third harmonic to tliat of the fiindamentcil harrnonic is[l3]:

Sirnilarly, if a two tone test is appliedl with each tone having an amplitude -4' the ratio of the

intermodulation somponents to the original two tones is given by[13]:

In order to obtain a maximum voltage swing of A in a two tone test. the amplitude of the tones

(-4') needs to be A/2. Cising this. the ratio of the two distortion mesures 1s:

'Typically when one appiies a two tone test. the two tones are closely spaced such that the intermodulation products of 2 f2 - fli , 2 f i - f2 are close to the originai two tones of jl and f2.

Rence the intermodulation distortion test provides an optirnistic view of the third order harmonic

ciistortion. but equation B.5 can be used to ;O from the ID3 to the HD3. This is useful because if

an approsimation to the Total Harrnonic Distortion (TAD) is neecied. then the results of a two tone

test can used. The uscfu!ness of this becomcs more apparent in Scction B.?. ivhcn the distortion in

a single track and Iiold is discussed.

B.2 TRACK AND HOLD AND MASTER-SLAVE TRACK

AND HOLD ANALYSIS

.\ f~~nrlaniental block in n data conversion systeni is the sarripling circuit. .-1 sarnpling circuit is

typically used in ari to relax the timirig rec{iiircment[l-l]. The piirpose of tliis section is to

discuss the track 2nd hold ancl nicaster slave track and hold blocks. ïhrough the analysis ttirec pieces

of information will he obtaincd. Tt will showri that ti track arid holci followed by an ideal sampler.

wtiich sarnples only the held valires c m Lie iisecl to obtain the 'THD of the circuit. .i iwtification for

the use of n two tone test in a single track ancl hold. to obtain a n estimate of the TCfD rvill be

givcn, Furthermore. it will he seen how master-slave trrrck and hold rillows for the cxperimcntal

charact.erizat ion of the distort ion present in the systcni.

B.2.1 IDEAL SAMPLER

The ideal sampler consists of n train of impulses. spaced at equal intervals of the sampling period

Ts. The ideal sampler can be represented in the tirne and frequency dornain by the following:

The ideal sarnpler simply replicates the original input signal spectrum at kf,, where f, iis the

sarnpling irequency, and k is an integer. .A block diagram of the ideal sampler is shown in Figure

B. 1. The ideal sampler is not a practical systern to use since it relies on the generation of an ideal

impulse, which is not practical.

Figure B. 1: ideal Sanipler

Figure B.l: Ideal T'rack and Fiold

B.2.2 TRACK AND HOLD

The track and hold is a practicnl renlization of the icleal sarnplcr. The track anci holti circuit. as was

cliscussed iri Chapttrr 5 tracks the input signal for tialf of the dock cycle. ririd for the rernaining half

it t~olcls the signal. 'The ideal track and tiolci circuit can be represented by the block diagram s h o w

in Figure E3.2.

The system shown in Figure 8.2 has two paths, each one active haif of thc time. The fiinetion

s ( t ) represents an in ideal square wave of amplitude 1. and period Ts. The square wave s ( t ) , and

the impulse train p ( l - T s / 2 ) , can be written as:

rvhere:

Figure B.3: The C'haracterizing Functions in an Ideal Track and 1-iolrl

'The hold s t s t e portion of the trnck and hold bloçk can be recognized as t h of n zero-order

hold[32]. The aystem impiilst. response h,, ( l ) is:

The runctions s ( 1 ) . p ( t - T,/'I) and h o ( ! ) are al1 shown in Figure 8.3 .

I t cran be shown that the output y ( t ) in the frequency doninin is given by[L.I]:

Equation B.12 demonstrates that the track and hold replicates the original spectrurn .Y( f ) at

intervals of fs much like the ideal sampler. The key difference between the ideal sampier and the

track and hold, is that the track and hold spectrum has a sine(.) envelope. This precludes the use

of a single tone test since each of the distortion products experience a different attenuation as a

function of frequency from the sine(-) function. A two tonc test, with two tones closely spaced

can be used. since the original tones, and their intermodulation products will experience the same

filtering. bTtilizing the relationship between ID3 and HD3 found in section B.1. and assuming that

Figure B.4: ideal Track and Hold Circuit Followed hy an Ideal Srimpler

the third clistortion term domiriates. then the 'THD distortion cran be estimated. 'i'tiis is usetiil in

cletermining the clistortion prescnt in a track and hold. if a rri-t~r slave architecture is riot available,

[t hcas been shown that in orcler to chnracterize the single track and holcf. n two tone test çan be

iwd. This is usefiil in a practical environment w hcre one tloes not have acccss to an ideal sampler

wliich can ample only the held values of t lie trnck and hold oiitput.' This is not the irase for the

(.onipiitor simulat,ion environment. tn a simutation environment. the output signal c m bc srirnpted

by an idcal digital sampler. Tliis system c m be representecl by nn icleal track and hold. followed by

;in ideal sampler. This is sliown in Figure 6.4.

l t can be shown that the oiitput ut(t) is givcn by:

t~i(t) = ~ ( t ) p ( t - b - Ts/Z) (B. 13)

The t.erm 5 has been inclucled such that the ideal sampler, srimples the lieid signal some tirne

after the transition frorn the track to hold mode is made. This is important in a non-ideai track and

hold. since the circuit needs a finite time to settle to steady state, after the track to hold transition

is made. This last equation demonstrates that the sine(-) distortion created by the track and hold

is not present in this type of configuration. and thus a single tone test can be iitilized to determine

the THD. This system was elctensively utilized during the simdations of the track and hold.

B.2.3 MASTER SLAVE T'RACK AND HOLD

The ba is of the master-slave track and hold has been discussed in the previous section. The ideal

sampler following the track and hold in Figure 8.4 is replaced by another track and hold, operatiog

at half the sarnpling frequency. In this manner an estimate of the held components is obtained in

'This is essentially what the slave in a master-slave architecture is doing

an experimental environment. The difficulty with this configuration is that the slave track and hold

is not an ideal element. and thus a pessimistic view of the distortion of a single track and hold will

be obtained. since it adds to the distortion present. Furthermore, since the second track and tiold is

not an ideal sampler. the output spectrum will have a sine(-) envelope. In order to circumvent this

problem, the input frequency is placed at a frequency fs /2 + Of. where the ma te r and slave track

and hold circuits are sampling nt a frequency of J 3 . and 1 , / 2 respectively[25]. Due to aliasing in the

second track and hold. the out.put t'requency roniponents wilt l ~ e nt. A f. 2A J . :]AI, - - - A n A f . I f

A f is small (i.e., KHz) then the clistortion products will al1 fall within the main lobe of the sine(.)

envelope. Furthcrniore. since the? arc closely spaceci ( A l ) , d l the harmonies will experience the

same atten~iation. and thus their ratios stay the same. An nddeci acivantage of the mater-slave test.,

is tliat the output spectrum will be in the KHz range. and thus a iiighly awiiratt.. audio speçtriim

analyzer can be utilized.

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