a comparison of approaches to carrier generation for...

A Comparison of Approaches to Carrier

Generation for Zigbee Transceivers22nd International Conference on VLSI Design, New Delhi

Leburu Manojkumar

Arun Mohan

Nagendra Krishnapura

Department of Electrical EngineeringIndian Institute of Technology, Madras

Chennai, 600036, India

6 January 2009

Leburu Manojkumar Arun Mohan Nagendra Krishnapura A Comparison of Approaches to Carrier Generation for Zigbee Transceiv

Zigbee transceiver

PA

LNA

Baseband

TX

Baseband

RX bits

bits

fref Frequency

Synthesizer

in

out

I

Q 2.405 to 2.48GHz


Outline

Local oscillator requirements

IQ generation by dividing a double frequency waveform

IQ generation by multiplying half frequency waveforms

Design details

Simulation results

Conclusions


Local oscillator requirements

quadrature

Divider

C1

R1 C2

fref

Programmable

generator

I

Q

VCO/Loop filter

Detector &Phase/Freq.

Charge pump

PA

LNA

Baseband

TX

Baseband

RX bits

bits

fref Frequency

Synthesizer

in

out

I

Q 2.405 to 2.48GHz

2.405-2.48 GHz in 5 MHz steps

Phase noise ≤ −92 dBc/Hz at 3.5 MHz offset

Settling time ≤ 200 µs (to 40ppm accuracy)

Spurs ≤ −20 dBc @ 5 MHz, ≤ −50 dBc @ 10 MHz


Choice of oscillator frequency

PA

LNA

Baseband

TX

Baseband

RX bits

bits

fref Frequency

Synthesizer

in

out

2.405 to 2.48GHz

Tx signal coupling pulls the oscillator and increases jitter

Oscillator frequency should be different from the carrier


Quadrature generation using divide-by-2

Oscillator

at 2f0

D Q

CK

D Q

CK

Master slave flip-flop

divide by two counter

Iout

Qout

qu

ad

ratu

reca

rrie

rs a

t f 0


Quadrature generation using multiplication

+-

+-

+-

+-

+-

+-

+-

+-

0o

-45o

-90o

-135o

Iout

Qoutring oscillator at f0/2

qu

ad

ratu

reca

rrie

rs a

t f 0


Comparison

Oscillator

at 2f0

D Q

CK

D Q

CK



Iout

Qout

quadra

ture

carr

iers

at f 0

Higher frequency

LC oscillator

Lower phase noise

More area

+-

+-

+-

+-

+-

+-

+-

+-

0o

-45o

-90o

-135o

Iout


quadra

ture

carr

iers

at f 0

Lower frequency

Ring oscillator

Higher phase noise

Compact


LC oscillator

Oscillator

at 2f0

D Q

CK

D Q

CK



Iout

Qout

Vdd

Vtune

4nH

Mn1 Mn2

I0

140 µm square spiral

6 turns

6 µm trace width

2.06 µm thick top metal

2 µm spacing

5 section distributed

model for simulations


Master slave divide by two

Dp

clkp

Ibias

Vdd

Dn

QpQn

2.4V

clkn

Oscillator

at 2f0

D Q

CK

D Q

CK



Iout

Qout


Active inductor load

2.4V

1.8V

Cgs

RG

2.4V-VGS

2.4V

1.8V

Cgs

RG

2.4V-VGS

1/gm Cgs

1/gm Cgs

CgsRG/gm RG


LC VCO+divider waveforms

1 1.1 1.2 1.3 1.4 1.5

x 10−8

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

seconds

volts

LC VCO+divider output

Q−signal

I−signal


LC VCO+divider characteristics

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.82.36

2.38

2.4

2.42

2.44

2.46

2.48

2.5

2.52

2.54

2.56x 10

9 VCO tuning curve

control voltage / Volts

div

ider

outp

ut fr

equency / H

z


LC VCO+divider phase noise

102

104

106

108

−160

−140

−120

−100

−80

−60

−40

−20

0

20

40VCO phase noise plot

−117 dBc/Hz at 3.5 MHz (relative)

frequency / Hz

phase n

ois

e [dB

c/H

z]


Trade off phase noise for area/power?

Vdd

I0

2L(diff.)

Vtune

Mn1 Mn2

Rp 2LCeff

Rp: tank loss

(shunt equivalent)

L(f ) ∝1

Rp

Vppd =4

πI0Rp


Ring oscillator delay cell

Pbias

in+ in-

Vdd

+

-

vtune

ituneitune/2

vref

fix_cur fix_curfix_gm fix_gm

vtune

Replica bias Delay cell

M1 M2

M3 M4

M5M6M7M8

M9

M10

Itail/2 = 180uA Itail = 360uA

1.3 V

n1 n2

+-

+-

+-

+-

+-

+-

+-

+-

0o

-45o

-90o

-135o

Iout



Frequency doubler

Xn

Xp Xp

Yn

Ibias

Vdd

out+out-

Gilbert

RL RL

X

Y cell

GilbertX

Y cell

A

B

out

Yp

Vbias Vbias

+-

+-

+-

+-

+-

+-

+-

+-

0o

-45o

-90o

-135o

ring oscillator at f0/2 Qout

Iout


Voltage to current converter

Vdd

Vtune

vcm

vctrl

Vtune

10uA

I1

I0+I2

I2

I0+I1+I2

vb vb1vb2

M1 M2M3 M4

M5

M6

M7

M12I0

Itune


Ring VCO with a constant current biasing

0 10 20 30 40 50 60 70 802.1

2.2

2.3

2.4

2.5

2.6

2.7x 10

9

Temperature (celsius)

Fre

qu

en

cy

( H

z)

Process and Temperature variations of the Oscillator

Process = TT

Process = SS

Process = FF

2.674 GHz

2.119 GHz


Ring VCO with a constant gm biasing

0 10 20 30 40 50 60 70 802.3

2.35

2.4

2.45

2.5

2.55

2.6x 10

9


Fre

qu

en

cy

( H

z)


Process = TT

Process = FF

Process = SS

2.562 GHz

2.331 GHz


Ring VCO with mixed biasing

0 10 20 30 40 50 60 70 802.34

2.36

2.38

2.4

2.42

2.44

2.46

2.48

2.5

2.52x 10

9


Fre

qu

en

cy

( H

z)


Process = TT

Process = FF

Process = SS

2.515 GHz

2.3511 GHz


Ring VCO+doubler output waveforms

9.2 9.25 9.3 9.35 9.4 9.45 9.5

x 10−8

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

Time (sec)

Am

plitu

de (

V)

Ring VCO + mixers output

Q−signal

I−signal310 mV


Ring VCO+doubler characteristics

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.81.50.3

2.3

2.4

2.5

2.6

2.7

2.48

X: 0.3402Y: 2.4e+09

X: 0.7319Y: 2.48e+09

X: 0.6615Y: 2.4e+09

X: 1.027Y: 2.48e+09

X: 0.9553Y: 2.4e+09

X: 1.482Y: 2.48e+09

Tuning Voltage (V)

Fre

qu

en

cy

(G

Hz)

Tuning of the VCO over Temperature and process

Fast case [ process = FF Temp =80]

Slow case[process=SS Temp =80]

Typical case [ process = TT temp = 27]


Ring VCO+doubler phase noise

103

104

105

106

107

−120

−100

−80

−60

−40

−20

0

20

Relative frequency (Hz)

Ph

ase N

ois

e(d

Bc / H

z )

Phase noise for different corners

Worst case [FF ,80] Phase noise = −96.45 dBc/Hz

Typical case [TT,27] Phase noise = −97.2bBc/Hz

Best case [SS,0] Phase noise = −97.97dBc/Hz

−97.2 dBc/Hz at 3.5 MHz


Quadrature generator layouts

140um

360um140um

160um

Ring VCO & mixers LC VCO & divider


VCOs: Performance summary

LC osc. + divider Ring osc. + doubler

VCO 1 mA 1.44 mA

Bias circuit — 0.355 mA

V-I converter — 0.1 mA

Divider 1.8 mA —

Multipliers — 0.45 mA each

Buffers 0.7 mA each 0.83 mA each

Total current 4.2 mA 4.455 mA (nom.)

6 mA (max.)

Phase noise -117dBc/Hz -97dBc/Hz

Area 360µm x 140µm 160µm x 140µm

Kvco 200MHz/V 220MHz/V

Technology 0.18 µm CMOS


Frequency synthesizer

quadraturePhase

Divider

C1

R1 C2

fref

Programmable

generator

I

Q

vctl VCO/

Dummyload

frequencydetector

Icp

Icp

Kvco = 200 MHz/V

Loop bandwidth = 53 kHz

zero: 9 kHz

high freq. pole: 293 kHz


Frequency synthesizer layout

400um

310umLeburu Manojkumar Arun Mohan Nagendra Krishnapura A Comparison of Approaches to Carrier Generation for Zigbee Transceiv

Frequency synthesizer: Performance summary

Programmable divider 1.09 mA

Differential to single ended converter 22 µA

Phase frequency detector 23 µA

Charge pump 20 µA

Bias generation circuits 350 µA

Total current 1.5mA

Settling time 110µs

Area 400µm x 310µm

Reference feedthrough -39dBc (5MHz)

-50dBc (10MHz)

Technology 0.18 µm CMOS


Conclusions

Ring oscillator based synthesizer

Meets Zigbee specifications

Consumes 40% higher power than an LC oscillator

Occupies 2.25× smaller area than an LC oscillator

LC oscillator based synthesizer

Phase noise much better than Zigbee requirements

Area (quality factor) and power limited by amplitude

Comparison valid for finer geometries as well

No significant advantage for oscillators

Dividers, multipliers benefit from scaling


References

“Wireless medium access control (MAC) and physical layer (PHY) specifications for low rate wireless

personal area networks (LR-WPANs)”, IEEE 802.15.4, available for download athttp://standards.ieee.org/getieee802/download/802.15.4-2003.pdf

Behzad Razavi, RF Microelectronics, Prentice Hall, 1997.

M. Tiebout, Low power VCO design in CMOS, Springer, 2006.

A. S. Porret et al., “Design of High-Q Varactors for Low-Power Wireless Applications Using a Standard

CMOS Process”, IEEE Journal of Solid-state Circuits, pp. 337-345, vol. 35, no. 3, March 2000.

E. Sackinger and W. C. Fischer, “A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers”, IEEE

Journal of Solid-State Circuits, pp. 1884-1888, vol. 35, no. 12, Dec. 2000.

Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, August 2000.

J. Craninckx and M. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer”, IEEE Journal of

Solid State Circuits, vol. 33, no. 12, pp. 2054-2065, 1998.

C. Vaucher et al., “A family of low-power truly modular programmable dividers in standard 0.35 um CMOS

technology,” IEEE Journal of Solid-state Circuits, vol. 35, no. 7, pp. 1039-1045, 2000.


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