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DOI: 10.1002/adma.200703210

A Doping-Free Carbon Nanotube CMOS Inverter-BasedBipolar Diode and Ambipolar Transistor**

By Sheng Wang, Zhiyong Zhang, Li Ding, Xuelei Liang,* Jun Shen, Huilong Xu,

Qing Chen, RongLi Cui, Yan Li, and Lian-Mao Peng*

Single-walled carbon nanotubes (SWCNTs) have been

extensively studied since they were discovered by Iijima in

1991,[1] and in particular many SWCNT-based electrical

devices have been fabricated and evaluated.[2,3] These devices

include field-effect transistors (FETs)[4–8] and diodes.[9–14]

When contacted with Pd and Sc,[7,15] it has been shown that

carriers can be injected, barrier-free, into the valence band

(p-FET)[7] and conduction band (n-FET),[15] respectively,

forming the basis for doping-free carbon nanotube (CNT)-

based ballistic complementary metal-oxide semiconductor

(CMOS) technology.[15] Similar to Si-based CMOS,[16] the

CNT-based CMOS inverter (Fig. 1a) forms the simplest and

most fundamental unit for more complex CMOS circuits. In

this Communication we show, in addition to the usual CMOS

inverter functions, that this basic device unit can also be readily

configured to function as an effective ambipolar FET[17] and a

new type of diode: the barrier-free bipolar diode.

Several CNT-based diodes have been developed. These

include p–n junction diodes formed by chemical doping[9] and

split gates,[10] and Schottky diodes based on intramolecular

junctions[11] and metal–CNT junctions.[12–14] While the

functioning of the p-n junction diode relies on the diffusion

of minority carriers in the device, which limits its high-speed

applications,[14] the presence of the Schottky barrier (SB) in

the Schottky diode significantly reduces the maximum current

that may be achieved. In general, the conventional diode may

[*] Prof. X.-L. Liang, Prof. L.-M. Peng, Dr. S. Wang, Dr. Z.-Y. Zhang,L. Ding, J. Shen, H.-L. Xu, Prof. Q. Chen, R.-L. Cui, Prof. Y. LiKey Laboratory for the Physics and Chemistry of NanodevicesPeking UniversityBeijing 100871 (P. R. China)E-mail: liangxl@pku.edu.cn; lmpeng@pku.edu.cn

Prof. X.-L. Liang, Prof. L.-M. Peng, Dr. S. Wang, Dr. Z.-Y. Zhang,L. Ding, J. Shen, H.-L. Xu, Prof. Q. ChenDepartment of ElectronicsPeking UniversityBeijing 100871 (P. R. China)

R.-L. Cui, Prof. Y. LiCollege of Chemistry and Molecular EngineeringPeking UniversityBeijing 100871 (P. R. China)

[**] This work was supported by the Ministry of Science and Technology(Grant No. 2006CB932400), and National Science Foundation ofChina (Grant Nos. 10434010, 90606026 and 60571002).Supporting Information is available online from Wiley InterScienceor from the authors.

� 2008 WILEY-VCH Verlag Gmb

be regarded as unipolar involving only one type of carrier, that

is, either electrons or holes.

In an earlier report,[15] we demonstrated that a CMOS

inverter can be fabricated readily by depositing two Pd

electrodes and two Sc electrodes side-by-side on a single CNT

lying on the surface of a SiO2 gate oxide. As shown in

Figure 1a, when the two Pd electrodes are used as the source

(S) and drain (D), the field effect of the device is characteristic

of a p-type FET (see Supporting Information Fig. S1a). When

the Sc electrodes are used, the device is characteristic of an

n-type FET (see Fig. S1b). When all four electrodes are used,

with VOUT¼V2¼V3 and VIN¼V5, the device functions as a

CMOS inverter (see Fig. S1c).

It should be noted that in the Si-based CMOS inverter the

conduction channel of the n-FET is isolated from that of the

p-FET.[16] In the CNT-based inverter shown in Figure 1a, both

p- and n-FETs share the same conduction channel, that is, the

CNT. The n-FET can be isolated from the p-FET readily by

cutting or etching away the CNT segment between the V2 and

V3 electrodes, but Figure S1 demonstrates clearly that even

though we did not disconnect the n-FET and p-FET we still

obtained a high-performing CMOS inverter with a voltage gain

of more than 10 and room temperature Ion/Ioff ratios of more

than 105 for both the p-and n-FETs. More than 30 devices were

fabricated on the same CNT, and all of the devices showed

almost the same I–V characteristics. The on-state resistance of

the p-FET (Fig. S1a) is ca. 300 kV at Vgs¼�20V, and that of

the n-FET (Fig. S1b) is ca. 200 kV at Vgs¼ 10V. The linear Ids–

Vds curves shown in Supporting Information Figure S1a and b

suggest that the contacts between the CNT and Pd and Sc are

Ohmic at room temperature. Similar measurements carried

out at low temperature confirmed that this Ohmic behavior

persists down to very low temperatures (e.g., 4.3K), indicating

barrier-free injection of both electrons and holes into the

CNT.[7,15]

In addition to the basic function of the CMOS device unit of

Figure 1a as an inverter, we found that in this unit the CNT

segment between the p-FET and n-FET (or between the V2

and V3 electrodes) is not only does not compromise device

performance but is also useful, and can be exploited to form

a high-quality diode. Figure 1b shows that the diode exhibits a

typical diode rectifying I–V characteristic, that is, it allows a

large current of more than 2.7mA for forward bias (V¼Vds,

with V3 being the S and V2 being the D electrodes) and a small

reverse current of only ca. 3 nA for small reverse bias.

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Figure 1. A CNT CMOS inverter-based bipolar diode. a) Schematic topview of the device unit. b) I–V characteristic of the segment of the CNTbetween V2 and V3, showing rectifying diode characteristics. c) Energy banddiagrams corresponding, to the four points A, B, C, and D of (b),respectively. The diameter of the CNT is ca. 1.5 nm, and all channeldistances between electrodes (Pd–Pd, Pd–Sc, Sc–Sc) are 4mm.

Figure 2. Experimental and fitted I–V curves obtained from the asymme-trically contacted barrier-free bipolar diode using the usual diode Equation1 for two CNTs with d¼ 1.7 nm and L¼ 2mm (red curve), and d¼ 3.5 nmand L¼ 4mm (blue curve).

However, the reverse current increases with increasing reverse

bias, and reaches ca. 200 nA at Vds¼�2V.

The I–V characteristic of a conventional diode may be

described by a modified diode equation:

I ¼ ðV � IRsÞ=Rsh þ Is exp½ðqðV � IRsÞ=nkTÞ � 1� (1)

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where the current I¼ Ids is the source–drain current, Is is the

reverse saturation current, Rs is the effective series resistance

of the device, the bias V¼Vds¼V2�V3, Rsh is the shunt

resistance, q is the electron charge, k is the Boltzmann

constant,T is the temperature, and n denotes the ideality factor

of the diode.[16] For an ideal diode, n¼ 1, but for real diodes n

takes a value between 1 and 2. Shown in Figure 2 are fits of I–V

curves of two typical diodes with different CNT diameters and

the current being shown in absolute magnitude. For the device

with a smaller CNT diameter d¼ 1.7 nm and a channel length

L¼ 2mm, we have n� 1.08. This value is very close to the ideal

value of n¼ 1. For the larger CNT device, with d¼ 3.5 nm and

L¼ 4mm, the ideality factor n� 1.3. Although the fitting

between the experimental and calculated I–V curves is

reasonably good (Fig. 2), it should be noted that the diode

Equation 1 is applicable only when one type of carrier is

dominating and when either a p–n junction or a SB is involved.

However, our device shown in Figure 1a involves both types of

carriers, that is, electrons and holes, and contains neither a p–n

junction nor a SB. The device is therefore a new type of device

that operates on a different principle, as is illustrated by the

schematics of Figure 1c.

To maximize the performance of the diode, intrinsic

SWCNTs without intentional doping were used in this work.

The CNT channel is electron-rich near its contact to Sc because

the Fermi level of Sc aligns in a basically barrier-free manner

with the conductance band of the CNT. The channel becomes

hole-rich near its contact with Pd, where the valence band of

the CNT aligns in a barrier-free manner with the Fermi level of

Pd. The electron (n-) and hole (p-) regions are separated by an

intrinsic region in which the Fermi level of the CNT is basically

flat (for zero bias) lying at the middle of the band gap.

In general, there exists no sharp p–n junction in our diode

device.

When a large forward bias is applied (schematic A of

Fig. 1c), both electrons and holes may be injected into the CNT

barrier freely. This diode therefore acts as a barrier-free

bipolar diode (BFBD). At zero or very small bias, for example,

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Figure 3. Effects of gate voltage on diode I–V characteristics. a) I–Vcharacteristics for an asymmetrically contacted Pd–CNT–Sc diode (thesame device as used for obtaining Figs. 1b–d and 2a) at different gatevoltages. b) Gate transfer characteristics for the same diode, showingambipolar field effect characteristic. c) The effects of the gate voltage on theenergy bands of the CNT.

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as shown in schematic B of Figure 1c, the current is dominated

by thermionic electrons and holes current. The potential

barrier for both types of carriers is basically equal to the band

gap of the CNT,Eg. The current of the diode depends therefore

exponentially on Eg near zero bias. Because the band gap of a

CNT is inversely proportional to its diameter, that is, Eg � 1/d,

a larger CNT is therefore expected to exhibit a larger current

under low bias than a smaller CNT. This general trend is well

shown in Figure 2, where the low-bias current minimum for the

CNT with d¼ 3.5 nm is ca. 10�10 A, while for the CNT with

d¼ 1.7 nm this current reduces to well below 5� 10�12 A.

When the bias is increased beyond V � Eg, the current is no

longer limited by the potential barrier near the Pd contact for

electron injection and that near the Sc contact for hole

injection. Instead the electron (hole) injection is now limited by

a barrier of ca. Eg/2 near the Sc (Pd) contact (see schematic B

of Fig. 1c). For reverse bias (schematic C of Fig. 1c), the reverse

current is first dominated by thermionic current over the

potential barrier of ca. Eg near Pd (Sc) contact for electrons

(holes). At larger reverse bias, the barrier for carrier injection

is thinned and tunneling current starts to dominate at point D

(schematic D of Fig. 1c) of Figure 1b with V<�1.5V.

The I–V characteristics of the diode (Figs. 1b and 2) also

depend on gate voltage Vgs, providing additional possibility to

further improve the diode characteristics. Shown in Figure 3a

are three distinct I–V curves measured, respectively, with

gate voltage Vgs¼ 10, �5, �20V, showing good rectification at

large positive Vgs¼ 10V and negative Vgs¼�20V. The diode

appears to be in an off-state for both forward bias and reverse

bias at Vgs¼�5V. The field-transfer characteristic (Fig. 3b)

shows that the device is indeed an ambipolar FET with a

threshold voltage Vth��2.5V. The majority carriers are holes

(p-type) with Vgs��20V and electrons (n-type) with

Vgs� 10V. The ambipolar transport under forward bias means

that both electrons and holes can be injected into the CNT

channel effectively with appropriate gate voltage. This

ambipolar transport of the diode is different from the normal

p-type and n-type CNT FETs (see Fig. S1a and c) where only

one type of majority carriers (either p-type or n-type) is

present. Under large forward bias, such asVds¼ 1V, this device

exhibits a large Ion/Ioff ratio of more than 105 at room

temperature for both types of carriers and an on-state current

of more than 2mA. The ambipolar transport characteristics of

our barrier-free asymmetric contact (Pd and Sc) transistor

shows better FET performance than that based on Ti contacts

where a large SB exists at the interface between the CNT and

Ti.[2] In our case the on-state resistance of the device is

typically less than 500 kV (e.g., Fig. 3b) while the same

resistance is much larger for SB transistors.[18]

The effects of Vgs on Ids (Fig. 3a) can be explained by the

band diagrams of Figure 3c. At large negative gate voltage

(with Vgs<Vth, e.g., Vgs��20V) the energy band is shifted

upward (Fig. 3c), which enhances hole current via lowering the

potential barrier near the Pd contact under the forward bias

and reducing the tunneling barrier near the Sc contact under

reverse bias. The small bias Ids–Vds curve (the red curve of

www.advmat.de � 2008 WILEY-VCH Verlag GmbH &

Fig. 3a) is therefore dominated by hole current. On the other hand,

at a large positive gate voltage (withVgs>Vth, e.g.,Vgs� 10V),

the energy band of the CNT is shifted downward (Fig. 3c),

which enhances electron current via lowering the potential

barrier near the Sc contact for electron injection under forward

bias and reducing the tunneling barrier near the Pd contact

under reverse bias. The small bias Ids–Vds curve (the green

curve of Fig. 3a) is then dominated by electron current. At

Vgs��5V, the transistor is basically in its off-state (Fig. 3b).

The potential barriers for carrier injections are either too high

(for thermionic current) or too thick (for tunneling current) for

both forward bias and reverse bias, leading to basically zero

current in the diode (blue curve of Fig. 3a). When a very large

forward bias is applied, transport of both types of carriers

contributes effectively to the total current regardless of Vgs

(schematic A of Fig. 1c).

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Figure 4. CNT based CMOS inverter based bipolar diode and ambipolarfor a CNT diameter of � 1.5 nm and a channel length L � 4mm. a) Diodecharacteristic (Ids–Vds) showing the absolute magnitude of the draincurrent as a function of the drain bias when the gate and drain electrodesare connected together as shown in the insert. b) Transfer characteristic ofthe device, showing that the device is an ambipolar FET.

We now consider the breakdown current. At very small

reverse bias, the current is determined by the potential barrier

of ca. Eg near the Pd (Sc) electrode for electron (hole)

injection. The barrier width reduces with increasing reverse

bias. At very large negative bias (schematic D of Fig. 1c) the

barrier can become thin enough to allow tunneling current to

pass through it. ButVgs can significantly reduce this breakdown

voltage. Consider the green curve of Figure 3a, which is

obtained at large Vgs¼ 10V>Vth, the corresponding energy

band of the CNT is shifted downward and electron current is

significantly enhanced byVgs (see Fig. 3c). At moderately large

reverse bias (e.g., at Vds��1.2V) the potential barrier for

electrons becomes thin enough to allow for a significant

tunneling, leading to a large reverse current of about 200 nA at

Vds¼�1.2V. The I–V curve obtained for Vgs¼�20V,

however, does not show the large reverse current for the

same bias range. This is because the device is in the

accumulation mode for electrons (see Fig. 3b), that is, at

Vgs¼ 0 the CNT channel is electron-rich and the energy band is

shifted downward. By decreasing Vgs to �20V, the energy

band shift is switched from downward to upward accompanied

with an increasing barrier width for electron injection from the

Pd contact and a decreasing barrier width for hole injection

from the Sc contact (Fig. 3c). However, Figure 3a suggests that

even at Vgs¼�20V the potential barrier for hole injection is

still not thin enough to allow for a large reverse current for the

red curve of Figure 3a.

An ideal diode should have a large current for forward bias

and zero current for reverse bias. For our bipolar diode, since

both carriers contribute to the current under large forward

bias, the key to improve the diode characteristics is to reduce

the reverse current, in particular the breakdown voltage at

which a large increase in the reverse current occurs (schematic

D of Fig. 1c). To a large extend the diode characteristics as

shown in Figures 1b and 3a can be significantly improved by

connecting together the Pd (drain) and gate electrodes (letting

Vds¼Vgs) as shown in the inset of Figure 4a while grounding

the Sc (source) electrode. It should be noted that for the

transistor used for obtaining Figure 4, Vth is smaller than zero

(ca. �4V), and for the bias range shown in Figure 4a [�5V,

þ5V] the transistor is basically n-type (Fig. 4b). At zero bias

the energy band of the CNT is shifted downward, reducing the

potential barrier for thermionic electron injection from the Sc

contact to the Pd contact and enhancing the current at small

forward bias. At forward bias, the increasing Vgs¼Vds shifts

the energy band further downward, leading to a further-

enhanced electron current of about 13mA at Vds¼ 5V.

When the bias is reversed, Vgs is also reversed. With

decreasing Vgs the downward energy-band shift is reduced

(when Vgs>Vth) and even reversed to become upward for

Vgs<Vth. This reduces electron current in the CNT channel.

For the whole bias range shown in Figure 4a, the reverse

current is dominated by the electron thermionic injection over

the potential barrier of the order of Eg at the Pd/CNT interface

(see schematic C of Fig. 1c) and reverse bias increases the

barrier width, blocking the tunneling electron current from Pd

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to CNT. For hole injection the barrier is at the Sc/CNT

interface, and the barrier height is basically the same as that for

electrons, that is,Eg. In principle, at very large negative bias the

large negative Vgs may reduce the barrier width for holes (but

not for electrons) to such an extent that tunneling hole current

may begin to contribute to the total current. The transfer

characteristic of the ambipolar transistor (Fig. 4b) shows,

however, that it would require a Vgs of at least ca. �20V to

have a significant hole current. Comparing with the I–V

characteristics shown in Figures 1–3, where the reverse current

increases exponentially with reverse bias and reaches up to a

few hundreds of nanoamperes before Vds¼�2V, Figure 4a

shows that the simple device configuration provides an almost

ideal diode, having little reverse current of about 22 nA up to

Vds¼ –5V. At large forward bias (e.g., at Vds¼ 5V), the

current reaches 12.5mA. This diode gives therefore a

rectification ratio of about 550 within [�5V, 5V], while the

same ratio is less than 10 for Figure 1b within a much narrower

bias range [�2V, 2V]. Because the reverse dark current is

determined mainly by Eg of the CNT, the reverse current may

be further reduced exponentially by using a smaller CNT with

larger Eg.

In conclusion, a barrier-free bipolar diode and an ambipolar

FET have been fabricated based on a doping-free CNT CMOS

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inverter, which consisted of two Pd and two Sc electrodes

fabricated side-by-side on a single CNT. It is shown that the

two Pd (Sc) electrodes can make almost perfect contact to the

valence (conduction) band of the CNT segment between them,

leading to barrier-free hole (electron) injection into the CNT

and p-FET (n-FET). In addition, the asymmetrically contacted

CNT segment between the Pd and Sc electrodes may be

utilized to function as a high-quality bipolar diode and

ambipolar FET. At large forward bias, both electrons and

holes are injected in a barrier-freemanner into the CNT, giving

a large forward current, and at reverse bias the reverse current

is initially limited by thermionic carrier injection overcoming a

potential barrier of the order of the band gap Eg of the CNT

and then for very large reverse bias by the tunneling current

through the barrier. The I–V characteristics of the bipolar

diode are found to depend also on the gate voltage Vgs and the

threshold voltage Vth of the ambipolar FET, and may be

further improved by connecting the drain and gate electrodes

via a linear or more-complex mode.

Experimental

The carbon nanotubes used in this work were SWCNTs of a fewhundred micrometers in length, which were directionally grown onheavily n-doped silicon substrate covered with a layer of insulatingSiO2 (500 nm) via catalytic chemical vapor deposition [19]. The siliconsubstrate was used as the back gate with the SiO2 being the gatedielectric. Pd contacts were patterned using electron beam lithography,and evaporated with a nominal thickness of 50 nm at a rate of 2 As�1

under a base pressure of 10�8 Torr (1Torr¼ 1.333� 102 Pa) followedby a standard lift-off process. These procedures were followed by thegrowth of 15 nmHfO2 thin film through atomic layer deposition (ALD)in 403K and 150 cycles with the ALD instrument (CambridgeNanotechnology Inc.). Sc contacts were then prepared in a mannersimilar to that for fabricating Pd contacts. Semiconducting SWCNTswere identified via electrical field-effect measurements. The diametersof the SWNTs were measured by atomic force microscopy. All

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electrical transport measurements were carried out with Keithley 4200semiconductor analyzer and in vacuum at room temperature.

Received: December 27, 2007Revised: February 12, 2008

Published online: July 14, 2008

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