332

[71

[81

[91

[101

[111

[121

[131

P. R. Gray, “A 15-W monolithic power operational ampli-fier,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 474-480,Dec. 1972.J. E. Solomon, W. R. Davis, and P. L. Lee, “A self com-pensated monolithic op amp with low input current and highslew rate,” in ISA’(2C Dig. Tech. Papers, 1969, pp. 14–15.B. A. Wooley, S. Y. J. Wong, D. O. Pederson, “A com-putor-aided evaluation of the 741 amplifier,” IEEE J. Solid.State Circuits, vol. SC-6, pp. 357-366, Dec. 1971.J. E, Solomon and G. R. Wilson, “A highly desensitized,wide-band monolithic amplifier,” IEEE J. Solid-State Cir-cuits, vol. SC-1, pp. 19-28, Sept. 1966.K. R. Stafford, R. A. Blanchard, and P. R. Gray, “A com-pletely monolithic sample,/hold amplifier using compatiblebipolar and silicon gate FET devices,” in IJSSCC Dig. Tech..Papers, 1974, pp. 190-191.J. E. Solomon and R. W. Russell, “Transconckrctance re-duction using multiple collector PNP transistors in an opera-tiomd amplifier,” U.S. Patent 3801923, Mar. 1974.See also, as a general reference:P. R. Gray and R. G. Meyer, ‘(Recent advances in mono-

IEF,EJOURNAL OF SOLID-STATECIRCUITS, VOL. SC-!), NO. 6, D!3CICMBiTR1974

James E. Solomon (S’57–M’61) was born inBoise, Idaho, on July 20, 1936. He rcceivcdthe B.S. and M.S. degrees in electrical engi-neering from the University of California,Berkeley, in 1958 and 1960, respectively.

In 1960 he joined the Motorola SystemsResearch Laboratory, Riverside, Calif.,where he participated in the design of radarreceivers, S band ECM equipment, missile

<: ;-.*. control systems, wide-band and IF ampli-

fiers. He transferred to the SemiconductorProducts Division of Motorola, Phoenix, Ariz., in 1963, to doresearch in silicon microelectronics. From 1963 to 1971, he heldthe positions of Project Engineer, Manager of Linear IntegratedCircuits R & D, and Manager for Consumer Integrated CircuitsDevelopment and Production. In 1971 he moved to NationalSemiconductor, Santa Clara, Calif., where he is presently respon-sible for linear standard product development and applicationsengineering. His efforts have resulted in the introduction of over25 linear IC products, 17 issued patents, and the publication ofnumerous ~a~ers.

lithic operational amplifier design,” IEEE Tram. Circuits Mr. Solo”m~n is a member of Eta. Kappa Nu, Tau Beta Pi, andand Syst., vol. CAS-21, pp. 317-327, May 1974. Phi Theta Kappa.

A Fast-Settling Monolithic Operational AmplifierUsing Doublet Compression Techniques

RUSSELL J. APFEL AND PAUL R. GRAY, MEMBER, IEEE

Absfract—A new high-speed monolithic operational amplifier isdescribed which uses an improved feedforward circuit configurationto achieve a total acquisition time (slewing plus settling) of 650 nswith a 1O-V input step without compromising dc performance orrequiring costly nonstandard processing.

I. INTRODUCTION

U NTIL recently, the poor frequency response oflateral p-n-p transistors in level shift circuits hadseriously limited the bandwidth and slew rate

obtainable in low cost, general purpose monolithic opera-tional amplifiers. This limitation has been overcome inseveral recently reported operational amplifier circuitsby including within the amplifier a parallel, ac coupled

signal path around the p-n-p level shift stage which by-

passes the stage at high frequencies. As a result, theunity-gain frequency of the amplifier is not limited byexcess phase shift in the lateral p-n-p stage, and stableunity-gain bandwidths of up to 50 MHz [ 1] and slew

Manuscript received May, 31, 1974; revised August 1, 1974. Thispaper was presented at the International Solid-State CircuitsConference, Philadelphia, Pa., February 1974.

R. J. Apfel is with Fairchild Semi~onductor, Mountain View,Calif. 94040.

P. R. Gray is with the Department of Electrical Engineeringand Computer Science, University of California, Berkeley, Calif.94720.

rates of up to 120 V/ps [2] have been achieved in lowcost amplifiers fabricated with a conventional bipolar IC

process,

While feed forward techniques have yielded great im-provements in stable bandwidth and slew rate, the im-

provement in amplifier settling time to high accuracieshas not been correspondingly great. The settling time

parameter is of great importance in certain classes ofapplications such as analog data. acquisition and conver-sion systems [3]. The relatively poor settling time per-formance of these amplifiers results in part from impre-cise cancellation of the pole associated with the rolloff ofthe p-n-p level shift stage, and the zero associated withthe ac coupled feedforward stage, giving nonuniform

open-loop response [4]. This paper will describe a n~ono-

lithic operational amplifier which uses an improved feed-forward technique to achieve a uniform open-loop fre-

quency response, a total acquisition time (slewing plussettling) of 650 ns to 0.01 percent with a 1O-V input step,and dc performance which is superior to most general-purpose operational amplifiers [5].

In Section II, the effects of pole-zero pairs in the open-loop frequency response on settling time in operational

amplifiers are discussed. In Section 111, an improvedfeedforward level shift configuration is described, and in

Section IV the complete amplifier is described and ex-perimental results presented.

APFEL AND GSAY: FAST-SETTLINGOPERATIONALAMPLIFIER 333

=EllByjJ-’-u~INPuT STAGE LEVEL SHIFT

COMPENSATION

EPK3 $-

FEEDFORWARO 1 ‘&

ki ~,Ill,1,1,1141!,11,

w~4J. < ,. ,./’/f’ ,

LJz, _./’;,7, /,,/ ,

%--f. ,~z2 .-, /’

UP2 --/’

Fig. 1. Block diagram of a conventional feedforward operationalamplifier, and an example of the resulting open-loop frequencyresponse in the presence on inexact pole-zero cancellation.

II. EFFECTS OF OPEN-k• P POLE-ZERO PAIRS (DOUBLETS)ON OPERATIONALAMPLIFTER TRANSIENT PERFORMANCE

A block diagram of a typical feed forward operational

amplifier in the nonslewing region of operation is shown

in Fig. 1. The high-frequency poles near and beyond the

crossover frequency have been neglected, and only thoseassociated with the level shift circuit, the feed forward

circuit, and the compensation capacitor have been in-

cluded. Under these assumptions, the small signal trans-fer function of the amplifier becomes:

Glji4

I

“,N~..uT~QID&wP

IT HAS BEEN ASSUMED FOR SIMPLICIT7 THAT

%2 = Wpz

Fig. 2. Closed-loop response of a typical feedforward operationalamplifier with inexact pole-zero cancellation.

the simple approach of Fig. 1. The pole-zero mismatch

factor will be of the same order as the mismatch in K,z

and K3 and Wzand 03. The effect of open-loop pole-zeropairs on the closed-loop response of a linear system hasbeen treated in the literature [6]. A slow-settling com-ponent is introduced in the step response whose time con-stant is the inverse of the doublet frequency, and whosemagnitude is proportional to the open-loop doublet mis-

match factor, the inverse of the loop gain at the doublet

frequency, and the effective input step amplitude. An

example of such an output transient is shown in Fig. 3.

While the block diagram of Fig. 1 approximately rep-resents the behavior of the amplifier in the nonslewingregion at frequencies well below the crossover frequency,it is not adequate to accurately predict the magnitude ofthe slow-settling components which will occur in a closed-loop operational amplifier in response to a large stepinput. Under this condition, the input stage saturates and

the amplifier slews for a period before the linear region

is entered. The magnitude of the slow-settling compo-

nents in the output depend not only on the behavior inthe linear region, but also on the initial conditions within

the level shift and feed forward stages which are built upduring the slewing period. This problem has been treatedelsewhere [7] with the conclusion that the magnitude

,(,)=~%]~*1of the slow-settling components in the output are pro-portional to the actual input step amplitude applied to

the amplifier. Thus, the simple expressions shown in

Fig. 3 may be applied even though the input stage is

or, in factored form

1 + :Z;“1!11 + &—. ,

1+: 1+:D v

A typical example of such a transfer function has been

plotted in Fig. 1.For the particular case of K2 ‘= K3and mz = 03, the two poles cancel the two zeros and a

uniform response results. For any other case, either one

or two pole-zero pairs (doublets) will appear in the open-loop frequency response. A typical example of the re-

sulting closed-loop response in the linear region is shownin Fig. 2. In the presence of uncorrelated variations inintegrated circuit capacitance and resistance values, pre-cise cancellation of these pole-zero pairs is difficult using

saturated during part of the transient. For example, in

a voltage follower operational amplifier circuit with a

crossover frequency of 10 MHz, and a doublet at 1 MHzwith a separation factor (o./oP) of 0.8, a 1O-V inputstep would give a slow settling component of 200 mV anda time constant of 160 ns. Such an amplifier might beexpected to settle to within 1 mV (0.01 percent) in about350 ns in the absence of a doublet. With the doubletpresent, a minimum of 870 ns after entry into the non-

slewing region would be required for the slow-settling

component to fall below 1 mV.

HI. IMPROVEDF’EEDFORWARDCONFIGURATIONS

Several approaches can be used to smooth the fre-quency response for amplifiers of the type shown inFig. 1. For example, the pole and zero locations withinthe feedforward/level shift stage can be made to depend

334 IEEE JOURNAL OF SOLID-STATECIRCUITS, DECEMBER1974

L’-FAST. SETFLING COMPONENT

-4_____vn/7E ‘EspONsE

— ———

!v

[o.t=vin I-kl’:-b’21,,=1-

Wco

,2=1-

‘2=;%[-lv”*l----------------------_.--

SLOW-SETTLING COMPONENT/

Fig.3. Transient response inthenondewingr egionof theexample circuit of Fig.2.

DOUBLET COMPRESSION LEVEL SHIFT~——————

d%

B

FEED-FORWARD

PATH

L–––___l

Fig. 4. Block diagram of doublet compression level shift ampli-fier.

on external components which can be selected or ad-justed to achieve optimum settling. The required pre-cision external components make this approach unde-

sirable. Another possibility is to include the level shift

and feedforward path within the feedback loop formed

by the pole splitting compensation capacitor [8]. Be-cause of the limited loop gain available within this feed-back circuit., this technique does not result in sufficientdoublet compression to optimize the settling time tomillivolt accuracies, although settling time to coarseraccuracies is improved.

A more desirable approach is to choose a feedforward

level shift circuit configuration which inherently resultsin precise pole-zero cancellation independent of varia-

tions in circuit component values. This was accomplished

by including a broad-band shunt-series feedback path

around the feedforward level shift stage as shown inblock diagram form in Fig. 4 [1]. The additional cir-cuitry has the effect of both reducing the pole-zero mis-match factor by an amount equal to the loop gain at the

doublet frequency, and of broadbanding the currenttransfer ratio of the level shift circuit. The circuitrealization used is shown in Fig. 5; the capacitor Ct by-passes the p-n-p transistor at high frequency, and thefeedback path is provided through the collector of Q3to the input summing node. This feedback configurationprovides low input impedance and high output im-pedance.

Fig. 5. Circuit realization of doublet compression level shiftcircuit.

The behavior of this circuit as a function of frequencycan be intuitively understood by first considering theopen-loop case as shown in Fig. 6. Here the collector of

Q3 has been grounded and no feedback takes place. Thebehavior of the circuit can be represented by the simpli-

fied small-signal equivalent circuit of Fig. 7, in which

only the diffusion capacitance of the p-n-p and the feed-

forward capacitor Cf have been considered. It is apparentthat this circuit has a nonuniform frequency response;at low frequencies the current gain is @[g,~.s(Rz IIr=a)

+ 1], while at high frequencies, when both capacitorsmay be considered to be shorted, the current gain is

P [9,,,3 (RI] IRzI l~m) + 1]. A detailed analysis of thisequivalent circuit shows that in the range between thesetwo extremes the behavior is described by a two-pole,

two-zero transfer function. The positive feedback con-

tributed by large values of Cf can give rise to complexpoles while too small a value of Cf causes a dip in thefrequency response to a value below the high-frequencyvalue. Between these extremes lies an optimum value ofCf which results in cancellation of one of the pole-zeropairs and a smooth transition between the high and lowfrequency values of the gain. Since the circuit is enclosed

within a feedback loop of loop gain of about 104, smallnonuniformities in the open-loop response of this circuit

caused by the pole-zero pairs are not observed in the

closed-loop current transfer ratio for values of Cf in theproper range.

APFEL AND GRAY: FAST-SETTLING OPERATIONAL AMPLIFIER

TCF

(12

a 3

$ iou~

.= v

Fig. 6. Doublet compression level shift in open-loop form.

9m3

Fig. 7. Small signal equivalent circuit of open-loop doublet com-pression level shift circuit.

IV. CIRCUIT DESCRIPTION AND EXPERIMENTAL

RRSULTS

While the fine-scale frequency response in the non-slewing region can be smoothed by using a feedbacklevel shift circuit, rapid settling also requires a high

slew rate to minimize time spent in the slewing portion

of the transient. In most operational amplifiers, slew lim-iting occurs when the differential input voltage exceeds

a threshold value causing the input stage to saturate, so

that no further current can be delivered to the compensa-tion capacitor, It can be shown [10], [11] that in opera-tional amplifiers for which this is true, the slew rate isdirectly proportional to the product of the unity-gainbandwidth and the input threshold voltage, or range.Thus, for a given bandwidth dictated by the high-frequency phase shift in the circuit, the slew rate can

be improved by increasing this input range. Note that

this input range is not the maximum differential inputvoltage beycmd which damage to the circuit will occur,but is simply the range over which the input stage pro-vides gain. The former is on the order of 7–50 V andoften appears on data sheets; the latter is typically 100mV–1 V. Because of component mismatches, the input

3.36

offset voltage of the amplifier tends to increase in direct

proportion to the voltage range, and as a result a princi-

pal tradeoff in high speed amplifier design is that between

dc input offset voltage and slew rate. In some reported

work this tradeoff [9], [12 ] has been eased by usingnonlinear circuitry to provide large charging currents

under slewing conditions. These techniques’ extend theinput range without the accompanying degradation in

offset. However, in amplifiers made with standard low-cost processing where no high speed complementary de-vice is available, the parasitic capacitance and switching

transients contributed by the rather complex circuitry

required make the value of such an approach open to

question where minimum overall settling time to highaccuracies is the objective.

Since the obtainable input offset voltage for a givenbandwidth and slew rate is directly related to compo-nent matching within the input stage, (in the absence ofnonlinear range extender circuitry), the approach taken

in this amplifier is to use conventional emitter degenera-tion in the input stage to increase the input range suffi-

ciently so that the slewing time is a relatively small por-tion of the total settling time to 0.01 percent. The offset,,voltage was then held to a mmimum by causing it todepend primarily on resistor matching, and using com-puter aided layout techniques and common centroidgeometries to achieve the best possible matching in thoseresistors. Using this approach, it has been possible to

achieve a typical input offset of 2 mV, while maintaining

a slewing time with a 10:V step of only ’150 ns out of atotal settling time to 0.01 percent of 600 ns.

Input Amplifier

The input amplifier of the circuit, shown in Fig. 8,combines the input differential gain stage, a level shift-ing stage, and a differential to single ended converter.Transistors QI and Q, are input emitter followers thatserve to lower the input bias and offset currents, andbuffer the input stage for large source impedances, They

are biased by constant current sources 11 and 11’ apd .

therefore the input bias and offset currents are inde-pendent of input differential voltage. The input amplifier

is the emitter degenerated pair Q2 and Qs which areloaded by current sources 12 and 1,’. This feeds a dif-ferential feedforward stage consisting of Q1l–QIG, ~8–~llj

Ctrl and Cf$z. The output of the level shift stage feedsa differential current converter 1A and 1A’. Examiningthis stage from a current standpoint it can be seen thatthe inputs to the level shift stage are IZ – lc~z and 12’ –IcQ3, and since that stage has unity current gain 1A and

14’ are both equal to IZ’ – lc~s, and the output current

is just equal to IcQz – Ic~3 (assuming 12 = 12’). Thedifference between ICQ2 and IPQa is set by the input dif-ferential voltage and R,E; note that in the linear regionof operation the output current is approximately equalto the differential input voltage divided by RE. Themaximum input voltage range for linear operation is

336 IEEE JOURNAL OF SOLID-STATECIRCUITS. DECEMBER1974

6 “.

Fig. 8. Input amplifier and level shift circuitry.

approximately equal to I~R~. The level shifting operationis done in the differential mode in order to improve the

common mode and power supply rejection ratios. Itshould be noted that the level shifting circuitry presentslow impedance load to the input stage so that the voltageswings and voltage gain in the input stage are small,Diodes D, and D2 are high breakdown diodes to protectthe circuit against large differential input voltages. Asdiscussed earlier, the limiting factor on slew rate is thetradeoff with input offset voltage; the input offset volt-age in turn is due to many factors. For zero output volt-

age, we essentially require IOut to be equal to zero, and

the difference voltage at the input required to achievethis will be affected by the following factors:

1) mismatches between QI and Q4, Q,z and Qa, andD1 and Dz;

Z) mismatches in R~l and R~Z (multiplied by ~3~2) ;

3) mismatches in 12 and Ii and I, and I,’ (both m~l-tiplied by ~B). The last two factors will tend to belinearly related to IaR~, the input range, and as this

product is increased these factors will be increased. Theycan be minimized, to some extent, by improving resistor

and current source matching. Current source matchingcan be improved by using emitter degenerated current

sources whose matching then depends on the degenerationresistor matching, and by using special p-n-p geome-

tries to improve ~ matching.

Second Stage (High Gain) Amplifier and Bias Circuit

The’ second amplifier is a, high gain darlington com-mon emitter stage as shown in Fig. 9. The input tran-sistor provides a high input impedance and the currentsource active load helps achieve high gain. The output

stage is a class All stage with QZA and Q2G providingbuffering between the gain stage and the output stage

QU providestheproper biasing for the output stage.

v+

IOUT

OUTPUT

bv-

Fig. 9. Second stage amplifier,

Compensation is accomplished with an internal capacitorCc, and resistor Rc provides a high frequency zero toimprove the phase margin.

The bias circuit is shown in Fig. 10. The main Qbjective

of this circuit is to provide bias current in such a

way that the product of I~R~ is constant over the

operating voltage and temperature range. This is neces-sary becauae the offset voltage is proportional to thisproduct and a change in this product will appear as achange in the offset voltage or drift, This constant pro-duct is achieved by establishing a constant voltage acrossRS, since the bias current is Vl~~/R8. The constantvoltage is obtained from a zencr connected transistorQ,,, biased by an n-channel FET. Diodes D, and D7provide compensation for Q:~ and Qa~ over temperature.

The total amplifier (excluding bias circuit) is shown in

Fig. 11. The input stage collectors are clamped by bias-

ing of Q13 and Q14 to be 3VBH from the positive supply,

APFEL AND GRAY: FAST-SETTLING OPERATION.4LAMPLIFIER

& FET-1

Q35

Q33

T

b v-

Fig. 10. Bias circuitry,

+Vcc

Y

L

I

hJ ‘8 “ 1=21C3

# [al 3 014

11T-l I

+ +

R1O

337

TO BIASCIRCUIT

‘vEE

Fig. 11. Complete amplifier circuit excluding bias circuit.

thus ensuring a large common mode input voltage range. The amplifier has been ciesigned to have a nominalAll current sources have emitter degeneration resistors unit gain crossover frequency of 12.5 MHz. This allowsto improve current source matching. The output stage for a worst case crossover frequency of about 18 MHz,uses conventional short circuit protection techniques to taking into account resistor and capacitor tolerancesprotect against overloads. Fig. 12 shows a photomicro- over temperature and productiori variations. The maxi-graph of the integrated circuit. The die size is 64 x 91 mum input voltage range is 825 mV, and the slew rateroils. (theoretical) is 66 V/ps.

338 IEEE JOURNAL OF SOLID-STATECIRCUITS, DECEMBER1974

V. AMPLIFIER

Fig. 12. Microphotograph of operational amplifier die.

\ 4 I ) I 1 1 I 1 \ 1 1 I \ 11) 1 1 1 I 1 Ill 1 11}

o

-25

I )111 111! 1111 // ‘1, I

\

\

A 10M

o — — — — —

10 100 *k 10 k 100k Ih

-175

-200

FREQUENCY – Hz

Fig. 13. Experimentally observed open-loop frequency response.

PERFORMANCE

‘The experimentally observed open-lciop gain and phase

shift versus frequency are shown in Fig. 13. No feed-

forward doublets can be observed. The amplifier has a

unit gain crossover frequency of 12.5 MHz with 65° ofphase margin. The large signal transient response is

shown in Fig. 14. The slew rate is about 65 V/&s in both

inverting and noninverting configurations. The over-

shoot observed results from a transistor coming out of

saturation and does not degrade the stability of the

circuit. Fig. 15 shows the fine-scale setting time for a

1(3-V input step. This response was measured using aquasi-summing point method and shows 0.01 pwrcent

(settling to within a 1 mV of final value) settling timeof 650 ns (0.1 percent settling time is about 450 ns).The small signal transient response is shown in Fig. 16.A rise time of 35 ns and a 5 percent overshoot are ob-served. Table I summarizes the ac performance of this

amplifier. Overload recovery time is defined as the delay

between Lhe removal of an input overload conditionand the beginning of the amplifier response and is im-

portant in situations where the amplifier is overdrive.The circuit’s dc performance is summarized in Table II.

APFEL ANDGRAY: FAST-SETTLINGOPERATIONALAMPLIFIER 339

m vERTICAL 5 V/di.

HORIZONTAL200 ns/di.

Fig. 14. Large signal transient response.

mVERTICAL1 rnV/div

HORIZONTAL200 ns/div

Fig. 15. Fine+cale transient response with a 1O-V input step,These data were taken with a dummy summing point tech-nique; 1 mV error at the amplifier output corresponds to 0.5mV on this photograph.

VERTICAL100 rnV/dw

HORIZONTAL100 ns/di.

Fig. 16,

TABLE I

Amplifier small signal unity gain step response.

TYPICAL PERFORMANCE; DOUBLET COMPKWSSION AMPLIFIER

V.S = +15 V, TA = 25°C—

AC Characteristics

Unity gain bandwidth 12.5 hIHzUnity gain slew rate 65 V/psUnity gain settling time to 1 percent 450 ns

(CLoa~ = 100 pF)Unity gain settling time to 0.01 650 ns

percent (C~o~ = 100 pFSmall signal rise time 35 nsLarge signal bandwidth 1 MHzOverload recovery time <100 ns

The parameters are comparable with or superior to

general-purpose monolithic operational amplifiers.

VI. CONCLUSIONS

A new monolithic operational amplifier has been de-scribed which uses a new circuit approach to achievea significant improvement in settling time performance

while using standard low cost technology and main-taining good dc performance.

TABLE II

TYPICAL PERFORMANCE llOUBLET COMPRESSION AMPLIFIERVS = +15 V, TA = 25°C

DC Characteristics

Input offset voltage 2 mVInput offset voltage 10 pv/”cTemperature coefficientInput bias current 150 nAInput offset current 20 nAOpen-loop gain, RL = 2 k~ 110 dBCommon mode rejection ratio 95 dBPower sLlpply rejection ratio 100 dBOutput voltage +13 vQuiescent current drain 5 mA

ACKNOWLEDGMENT

The contributions of G. Cobanoglu and J. Butler to

the design, breadboarding, and testing of the circuits,and those of B. Apfel to the mask layout, are gratefullyacknowledged.

REFERENCES

[11 R. J. Van De Plassche, ‘(A wide-band operational amplifierwith a new output stage and a simple frequency compensa-

IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. s;-9, NO. 6, DECEMBER1974340

[21

[31

[41

[51

[61

[71

[81

[91

[101

[111

tion,” IEEE J. Solid-State Circuits, vol. SC-6, pp. 347-352,Dec. 1971.LM118 Operational Amplifier Data Sheet, National Semi-conductor, Santa Clara, Calif., June 1973.Analog-Digital Conversion Handbook, Analog Devices. Inc.,June 1972:

.

M. Nakajima and H. Sasaki, “A high speed, high precisionmonolithic folding amriifier for PCM svstems. ” in ISSCCDig. Tech. Paperxy 1973, pp. 2@21. “ ‘R. J. Apfel and P. R. Gray, “A fast-settling monolithic feed-forward operational amplifier using doublet compressiontechniques,” in I&!7CC Dig. Tech. Papers, 1974, pp. 134–135.F. D. Waldhauer, “Analog integrated circuits of large band-width,” in 1963 IEEE Conu. Rec., part 2, pp. 200–207.B. Y. Kamath, B,. G. Meyer, and P. R. Gray, “Relationshipbetween frequency response and settling time of operationalamplifiers,” this issue, pp. 347–352.Y. Nishikawa and J. E. Solomon, “A general purpose wide-band operational amplifier,” in ISSCC Dig. Tech. Papers,Feb. 1973, pp. 144-145.P. C. Davis and V. R. Saari, ‘(High slew rate monolithicoperational amplifier using complimentary compatiblePNP’s,” in ISSCC Dig. Tech. Papers, 1974, pp. 132-133.J. E. Solomon, W. R. Davis, and P. L. Lee, “A self-com-pensated monolithic operational amplifier with low inputcurrent and high slew rate, “ in IJSSCC Dig. Tech. Papers,1969, pp. 14-15.P. R. Gray and R. G. Meyer, “Recent advances in mono-lithic ope~ational amplifier” design,” IEEE Trans. Circuitsand S~st., vol. CAS-21, pp. 317–327, May 1974.

[121 W. E. Hearn, “Fast slewing monolithic operational ampli-fier,” IEEE J. Solid-State Circuits, vol. SC-6, pp. 20-24,Feb. 1971.

Russell J. Apfel was born in New York,N.Y., on April 11, 1949. He received theB.S.E.E. degree from the Massachusetts In-stitute of Technology, Cambridge, in 1969,and the M .S.E.E. degree from the Univer-sity of Santa Clara, Santa Clara, Calif., in1971. He is presently working towards thePh.D. degree at the University of California,Berkeley:

In 1969 he joined Fairchild Semiconduc-tor, Mountain View, Calif. working on the

development of new liriear integrated circuits. He is presentlyManager of Linear Microcircuits Engineering, responsible for thedesign and development of new industrial and interface linearintegrated circuits.

Paul R. Gray (S’65-M’69),see p. 313 of this issue.

for a photograph and biography, please

High Slew Rate Monolithic Operational AmplifierUsing Compatible Complementary P-N-P’s

PAUL C. I)AVIS, MEMBER, IEEE, STANLEY F. MOYER, AND VEIKKO R. SAARI, MEMBER, IEEE

Abstract—An internally compensated monolithic operationalamplifier, fabricated using only junction-isolated bipolar processing,slews in excess of 500 V/Ws, and settles to within 0.1 percent in200 ns as a pulse inverter. Performance in the noninverting mode isonly slightly degraded in comparison with the inverting mode. Inaddition, the following performance levels have been achieved:50-MHz unity-gain bandwidth with 96-dB open-loop gain, 30-mWquiescent power at +,J V, *50-mA output current capability, andoutput voltage to within 0.5 V of either supply.

In order to achieve the above performance, the following innova-tions were %ade: 1) a process for junction-isolated compatiblecomplementary p-n-p transistors with low collector series resistance,2) a high-speed class-B output. stage, 3) push-pull middle stages,4) driven internal reference voltages locked to the noninvertinginput, and 5) very small voltage drops across large internal shapingcapacitors which permit use of high-capacitance @nctions.

Manuscript received May 29, 1974; revised August 14, 1974.This paper was presented at the International Solid-State Cir-cuits Conference, Philadelphia, Pa., February 1974.

P. C. Davis and S. F. Moyer are with Bell Laboratories, Read-ing, Pa. 19604.

V. R. Saari is with Bell Laboratories, Holmdel, N.J. 07733.

I. INTRODUCTION

THIS PAPER deals with an internally compensatedmonolithic op amp believed to be the fastest sofar achieved using only junction-isolated bipolar

processing. As a unity gain pulse inverter or summing

amplifier, it slews in excess of 500 V/,Ws and settles towithin 0.1 percent in 200 ns. Compared with previousdiscrete component or hybrid circuit approaches, thiscircuit offers a low cost path to precision, high-speeddifferential amplification. Excellent speed is maintainedfor output swings to within a few tenths of a volt of thesupplies and up to *5O mA. The amplifier maintains a

bandwidth of 25 MHz when the supply voltages arereduced %0 ~3 V, which corresponds to 30 mW ofquiescent power dissipation.

Designed especially for use in fast coding circuits as

a summing amplifier with diode-coupled feedback net-

works, the amplifier has a common-emitter output con-figuration. While it is intended for application at lowimpedance levels ( 100–300 Q), high impedance load and