A few research topics A few research topics

Mike KishinevskyMike Kishinevsky

5 July 20055 July 2005

Introduction to SCLIntroduction to SCL

www.intel.com/research/silicon/scl

Technology & Manufacturing Technology & Manufacturing Digital HealthDigital Health

DigitalEnterprise

DigitalEnterprise

CAD R&DCAD R&D

MobilityMobility DigitalHomeDigitalHome

Major Focus: CPUs

Opportunistic: Chip Sets, Communication

OrganizationOrganization

What we doWhat we doMission

Research in CAD to invent design technologies that will be vital to Intel

Research Directions• Integrated Design and VerificationIntegrated Design and Verification• Layout-aware synthesisLayout-aware synthesis• Formal property verificationFormal property verification• Physical and Electrical Design and AnalysisPhysical and Electrical Design and Analysis• Emerging technologies Emerging technologies

(latency-tolerance, variations, CMP)(latency-tolerance, variations, CMP)

Academic CollaborationAcademic Collaboration

Blue Badge Employees SCL Funded Research Mentored DSTC Research Mentored SRC Research

SCAz

UT

UCB

CMU

UCLA

Chicago

UCSD

UCB

Michigan

UU

MAOR

ChalmersOxford

UBC

Warwick

PSU

UPC

Columbia

Wisc

Minn

Waterloo

OGI

BYU

Oxford

UT

Wis

UCSB)

UCI

UIUCUIUC

UWUW

PurduePurdue

CMUCMU

MichiganMichigan

UIUCUIUC

TsingHua

MS

SteklovIMVS

Collaborationwith UPC

(Barcelona)

~40 “blue badge” researchers~40 “blue badge” researchersMentoring research at 26 different universitiesMentoring research at 26 different universities

From Rob Aslett

A few research topicsA few research topics

Transistor Logic OperationTransistor Logic Operation

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF

Transistor (90 nm technology)Transistor (90 nm technology)

From Mark Bohr

DNA strand ~ 10nm

Wires (65nm process)Wires (65nm process)8 layers of Metal (Cu)8 layers of Metal (Cu)

4 in X, 4 in Y direction4 in X, 4 in Y direction

Vias connect layersVias connect layers

Wire delay determined Wire delay determined by C and R by C and R

Higher layer – bigger wire Higher layer – bigger wire - smaller delay- smaller delay

Width can be controlledWidth can be controlled

From Mark Bohr

Boolean Function (NAND Gate)Boolean Function (NAND Gate)

A

B

C

Y = not ( A and B and C) A

A

B

C

CB Y

Flip-flopFlip-flop

D Q

clk

D

clk

Qevery clock_edge Q := D

Microprocessor (Pentium IV, 90nm)Microprocessor (Pentium IV, 90nm)

Dual core microprocessor Dual core microprocessor (Montecito, 90nm)(Montecito, 90nm)

From Microprocessor Report

1.72 * 10^9 transistors

596 mm^2

Process scalingProcess scalingHigh Volume High Volume

ManufacturingManufacturing20042004 20062006 20082008 20102010 20122012 20142014 20162016 20182018

Technology Node Technology Node (nm)(nm)

9090 6565 4545 3232 2222 1616 1111 88

Integration Capacity Integration Capacity (BT)(BT)

2 4 8 16 32 64 128 256

Delay = CV/I scalingDelay = CV/I scaling 0.70.7 ~0.7~0.7 >0.7>0.7 Delay scaling will slow downDelay scaling will slow down

Energy/Logic Op Energy/Logic Op scalingscaling

>0.35>0.35 >0.5>0.5 >0.5>0.5 Energy scaling will slow downEnergy scaling will slow down

Bulk Planar CMOSBulk Planar CMOS High Probability Low ProbabilityHigh Probability Low Probability

Alternate, 3G etcAlternate, 3G etc Low Probability High ProbabilityLow Probability High Probability

VariabilityVariability Medium High Very HighMedium High Very High

ILD (K)ILD (K) ~3~3 <3<3 Reduce slowly towards 2-2.5Reduce slowly towards 2-2.5

RC DelayRC Delay 11 11 11 11 11 11 11 11

Metal LayersMetal Layers 6-76-7 7-87-8 8-98-9 0.5 to 1 layer per generation0.5 to 1 layer per generation

From Pat Gelsinger

Moore’s Law and its costs Moore’s Law and its costs

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1960 1970 1980 1990 2000 2010

$/M

IPs

$ per MIPS$ per MIPS

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1960 1970 1980 1990 2000 2010

$/T

ran

sist

or

$ per Transistor$ per Transistor

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1980 1990 2000 2010

Test

Cap

ital

($) Per Chip

Based on SIA roadmap

Test CapitalTest Capital

$1

$10

$100

$1,000

$10,000

1960 1970 1980 1990 2000 2010

Fab

Co

st

($M

)

www.icknowledge.com

FAB CostFAB Cost

Implications of scalingImplications of scaling

Fast power growth Fast power growth

Slower wiresSlower wires

Too many transistors => multi-processorsToo many transistors => multi-processors

Variations Variations

Less reliable componentsLess reliable components

Validation: more complex system on a dieValidation: more complex system on a die

TestingTesting

Software model for multi-processors, multi-threads Software model for multi-processors, multi-threads

Design flow (construction)Design flow (construction)

Instruction Set Architecture

Performance model

Floorplan

Register Transfer Level Model

Schematic Synthesis(manual/automatic)

Placement

Routing

Chip Assembly Mask design

Fabrication

ConstraintsProduct

Technology

Design flow (validation)Design flow (validation)

Instruction Set Architecture

Performance modelSimulation

uA validation

FloorplanAnalysis

RTL Simulation, Verification

SchematicSimulation,Verification

PlacementTiming analysis

RoutingElectrical verification

Timing & Noise analysis

Chip AssemblyRule checking

Mask Validation

Fabrication

ConstraintsProduct

Technology

Testing

Platform Validation

Magic [unreachable] design flowMagic [unreachable] design flow

Instruction Set Architecture

ConstraintsProduct

Technology

Testing

Platform Validation

Magic design tool

Mask Design

Fabrication

Two abstractions of the nightTwo abstractions of the night

Kuindzhi, “Noche del Moonlit”, 1898Malevich, “Cuadrado Negro”, 1923

An abstraction for a theoreticianAn abstraction for a theoreticianTheorem. The first order suprematic night is damn dark

An abstraction for an engineerAn abstraction for an engineerDebugging this system can keep me busy until retirement …, but I need to deliver it in two months

Part of the flowPart of the flow

Register Transfer Level

Schematic

Layout (polygons)

Logic Synthesis

Placement

Abstraction in Logic SynthesisAbstraction in Logic Synthesis

Literals in factored form

&

&

&

&

a

b

c

d

&

& &

&

ab c

ed

e

Do not capture delay

Abstraction in Logic SynthesisAbstraction in Logic Synthesis

Logic depth and literals in factored form

& &

&

a b c d

Do not capture fanout load, wire delay, congestion

&

&

e f

& &

&

a b c d

&

&

e f

How to conquer: How to conquer: to divide or not to divide?to divide or not to divide?

Part.

Flat

Part: partition and use aggressive synthesis for smaller blocksFlat: solve the whole problem at once, but use less powerful methods

Problem: Algorithm for synthesis of large circuits using partitioning

Placement for optimized logic Placement for optimized logic synthesis resultsynthesis result

Placement gravitated to the EastLong wires to the WestMore buffers, timing violations

Partitioning taking into account Partitioning taking into account layout infolayout info

Partition into blocks based on pin locationOptimize within blocksMore gates, same delay before placementLess area better delay after placement

Abstraction in placementAbstraction in placement

Register Transfer Level

Schematic

Layout (polygons)

Logic Synthesis

Placement Manhattan distance[ISPD2005 competition]

Manhattan route and real routeManhattan route and real route

From Nikolay Rizhenko

Due to congestion [other cells not shown] and more critical wires

Abstraction in placementAbstraction in placement

Register Transfer Level

Schematic

Layout (polygons)

Logic Synthesis

Placement Manhattan distance + Congestion estimate +Wire and gate delay estimate

Placement techniques Placement techniques (e.g. quadratic placement)(e.g. quadratic placement)

Reduce discrete problem to a continuous Reduce discrete problem to a continuous [approximate] space[approximate] spaceOptimize for the approximate [incorrect] cost functionOptimize for the approximate [incorrect] cost functionMap “optimal” continuous solution back to legal Map “optimal” continuous solution back to legal discrete spacediscrete spaceIterateIterateProblems:Problems: InstabilityInstability Incremental changes may lead to large changes in layoutIncremental changes may lead to large changes in layout Wire delay prediction requires congestion estimate and Wire delay prediction requires congestion estimate and

possibly layer assignmentpossibly layer assignment

Can we do better abstraction in Can we do better abstraction in synthesis?synthesis?

Register Transfer Level

Schematic

Layout (polygons)

Placement-aware logic synthesis

Placement with logic resynthesis

Why Software Abstraction is “Easy”Why Software Abstraction is “Easy”

Physics is not involvedPhysics is not involved

Productivity is more important than optimization Productivity is more important than optimization (do we care what is the size of Windows binary?)(do we care what is the size of Windows binary?)

In design: late bugs are more expensive than early In design: late bugs are more expensive than early ones, but fixing them requires the same ones, but fixing them requires the same technologytechnology

In the customer field: bugs are allowed In the customer field: bugs are allowed [not for safety critical] and can be fixed with [not for safety critical] and can be fixed with relatively low costrelatively low cost

Why Hardware Abstraction is HardWhy Hardware Abstraction is Hard

Physics changes every two years Physics changes every two years Some changes are disruptiveSome changes are disruptiveOptimization is equally important as productivity, Optimization is equally important as productivity, because design problem is highly constrainedbecause design problem is highly constrainedIn design: late bugs require different and In design: late bugs require different and expensive technology. “Binaries” should be expensive technology. “Binaries” should be human understandable. Will illustrate by Esterel.human understandable. Will illustrate by Esterel.In the customer field: bugs are unacceptable. In the customer field: bugs are unacceptable. Design abstraction is limited by what can be Design abstraction is limited by what can be verified verified

Some research directionsSome research directionsDesign methodsDesign methods

Bridging abstraction gapBridging abstraction gapSeparate timing and functionality: latency-toleranceSeparate timing and functionality: latency-tolerance

Balance between optimality and abstraction complexityBalance between optimality and abstraction complexityPlacement-aware logic synthesis and synthesis-aware placementPlacement-aware logic synthesis and synthesis-aware placementPartitioning and hierarchical methods vs flat methods Partitioning and hierarchical methods vs flat methods

Verification beyond combinational equivalenceVerification beyond combinational equivalence Protocol verificationProtocol verification Transaction-level (extending equivalence)Transaction-level (extending equivalence) Powerful decision procedures Powerful decision procedures Sequential verificationSequential verification

Design and verification in lock-step Design and verification in lock-step Fault-tolerance at low granularityFault-tolerance at low granularity