A Flow Graph Technique for DFT Controller Modification

Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram Riahi*,Fabrizio Lombardi*,Zainalabedin Navabi

Electrical and Computer Engineering, University of Tehran, Iran*ECE Department, Northeastern University, USA

Agenda

Motivation, Objectives and Contributions

Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

Agenda

Motivation, Objectives and Contributions

Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

Motivation and Objectives

Test generation at the gate-level • produces high-quality tests But in the case of large systems• It is computationally expensive

Motivation

We propose a DFT algorithm to •Reducing test generation time•Reducing test application time

Objectives

Our Contributions

Realize and utilize existing path of the datapath by changing controller

Previous work Increase the testability of an RTL module Use datapath as search space to find test paths

But, we Increase testability; decrease test application time. Use the CDFG as search space to find test paths

Advantages of Our Algorithm

Reduce test application time Using pre-computed test vector Reducing test generation effort Very small area overhead on controller No timing penalty of critical path (in the

datapath)

Agenda

Motivation, Objectives and Contributions

Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

CDFG and Synthesis

*1 +2 *3

*4 +5

*6 *7

*8

-9

a b c d e f g

z1 z2 z3

z4

z5

z6

z7

z8

y

5

3

CLK1

CLK2

CLK3

CLK4

CLK5

*1

The behavioral description of a circuit is usually provided using a hardware description language like VHDL. This description is compiled into a control/data flow graph (CDFG), which is a directed graph with operation vertices, data variable arcs, conditions, and loops.

CDFG can be used for extracting control and data information during synthesis steps

Scheduling

Binding

Datapath & Controller

s1 s2 s3 s5s1

s2

s3

s4

0 0 0 0 0

m1 m2 m3 m4 m5 m6 m7

0 0

1 2 0 0 1 1 0

1 1 2 2 0 0 0

0 0 2 1 0 0 0

(a) (b)

L1

1

1

1

0

L2 L3

1 1

0 1

1 0

1 0s5 0 0 0 0 0 0 1 1 0 0

s4

* * + -

z1,z4,z6,y z3,z7,z8

m1 m2 m3 m4

L1 L2z2,z5

a b c df g

0 01 1 2 0 0 11m5 m6

m7

L3

0 01 1

0 1

e3

2 2

5

Group 1 Group 3Group 2 Group 4

R1 R2 R3

Test-Path in the Datapath

z1, z4, z6, y z3, z7, z8 z2, z5

a b 3 f g 5 c e d

Group 1

* * + -Group 2 Group 3 Group 4

Module Under Test(Pre-computed test vectors are

available)

A Problem!!! This Test-Path is not

supported by the controller!!!

Using the CDFG as the search space, a controller supported Test-Path can be found

Agenda

Motivation, Objectives and Contributions

Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

Test-Path in CDFG The role of a controller is to map

the CDFG of a circuit to its datapath. Consequently, All paths in a CDFG exist in the

datapath of a circuit. However, there may be additional

paths in a datapath that do not necessarily exist in a CDFG that the datapath is generated from.

Test-Path in CDFG controller-supported paths: paths in a

datapath can be activated for passing data by the existing controller of the circuit.

controller-unsupported paths : paths of the datapath that are not specified by the CDFG and are not activated by the existing controller

To recognize and thus utilize these paths, changes may be needed in the circuit’s controller.

Faulty Operator in the CDFG If a module in the RTL is faulty, all

operators in its group of the CDFG became faulty. This means that multiple faults appear in the CDFG. To avoid this scenario, only one operator is considered as a victim operator as faulty and the CDFG is pruned by deleting all other operators in the group as well as all their connecting nodes.

Victim

A victim is an existing/new operator that

1. Receives its inputs from outside of its group and

2. Propagates its output to outside of its group, and

3. Pruned CDFG corresponding to the victim operator must have at least a primary output of the original CDFG.

Victims

Group i

ab

c

VictimVictim

Group i

ab

c

c

ba Victim

Group i

ab

c

c

ba

Test Time Reduction

Test application time can be reduced using two techniques

Finding best victim when a victim has alternatives

Removing unnecessary states in the Pruned CDFG (Explained in the example)

Agenda

Motivation, Objectives and Contributions

Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

Group 1

z1, z4, z6, y z3, z7, z8 z2, z5

a b 3 f g 5 c e d

Group 1

* * + -Group 2 Group 3 Group 4

Group 1 Victim

*1 +2 *3

*4 +5

*6 *7

*8

-9

a b c d e f g

z1 z2 z3

z4

z5

z6

z7

z8

y

5

3

CLK1

CLK2

CLK3

CLK4

CLK5

z1 and y are mapped in the same register in the

Datapath

*1

Victim

Group 1

Group1 Testing

*1

a b

CLK1 *1

y

Pruned CDFG

Just one clock cycle is enough to apply each pre-computedtest vector to this RTL module

Group2

z1, z4, z6, y z3, z7, z8 z2, z5

a b 3 f g 5 c e d

Group 1

* * + -Group 2 Group 3 Group 4

z7

z8

Group 2 Victim

*1 +2 *3

*4 +5

*6 *7

*8

-9

a b c d e f g

z1 z2 z3

z4

z6

z5

y

5

3z1 and z6 are mapped in the

same register in the Datapath

z3 and z8 are mapped in the same

register in the Datapath

Victim

*v

S1 S2 S3 S5S4

Group 2

Group 2 Testing

*1 *3

-9

a b f g

y

CLK1

CLK5

S1 S2 S3 S5S4

Just two clock cycles are enough to apply each pre-computedtest vector to this RTL module

Group4

z1, z4, z6, y z3, z7, z8 z2, z5

a b 3 f g 5 c e d

Group 1

* * + -Group 2 Group 3 Group 4

Group4 Victim

*1 +2 *3

*4 +5

*6 *7

*8

-9

a b c d e f g

z1 z2 z3

z4

z6

z5

z7

z8

y

5

3

CLK1

CLK2

CLK3

CLK4

CLK5

*1

VictimGroup 4

Group 4 has only one member, so it is a compulsory victim operator. The DFG for this victim is the same as the original CDFG . This CDFG can be reduced by the elimination of clocks 2, 3 and 4.

Reducing the CDFG Graph of Group 4

*1 +2 *3

*4 +5

*6 *7

*8

-9

a b c d e f g

z1 z2 z3

z4

z6

z5

z7

z8

y

5

3

*1

z1(1,1)

z4(2,2)

z6(3,4)

y(5,5)

z3(1,2)

z7(3,3)

z8(4,4)

1 2 34

The utilization of shared registers of the datapath are the basic principle for reducing the test application time. Using a bipartite graph the obtained CDFG is reduced

Group 4 Testing

*1 *3

-9

a b f g

y

CLK1

CLK5

S1 S2 S3 S5S4

Just two clock cycles are enough to apply each pre-computedtest vector to this RTL module

Agenda

Motivation, Objectives and Contributions

Preliminaries and Our Idea CDFG Testability and Victim An Example Experimental Results

Experimental Results

Paulin

Tseng

Diffeq

Avenhause Filter

1

0

2

5

# of Extra Transition in the Controller

0

0

0

2

# of Extra States in the Controller

5

5

5

7

# of Original Controller States

0.1%

0%

0.16%

0.47%

Gate Overhead

Questions!