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UNIVERSITY OF NAIROBI
FINAL YEAR PROJECT
DEPARTMENT OF ELECTRICAL AND INFORMATION ENGINEERING
A FOUR QUADRANT CMOS ANALOGUE MULTIPLIER
PROJECT NO: 001
By
TAYABALI JUZER MURTAZAALI
REG. NO: F17/39567/2011
SUPERVISOR: PROF. ELIJAH MWANGI
EXAMINER: MR SAYYID
A PROJECT REPORT SUBMITTED TO THE DEPARTMENT OF ELECTRICAL AND
INFORMATION ENGINEERING IN PARTIAL FULFILLMENT OF THE
REQUIREMENTS OF BSc. ELECTRICAL AND ELECTRONIC ENG. OF THE
UNIVERSITY OF NAIROBI
16th
May, 2016
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DECLARATION OF ORIGINALITY
FACULTY/ SCHOOL/ INSTITUTE: Engineering
DEPARTMENT: Electrical and Information Engineering
COURSE NAME: Bachelor of Science in Electrical & Electronic Engineering
NAME OF STUDENT: JUZER MURTAZAALI TAYABALI
REGISTRATION NUMBER: F17/39567/2011
COLLEGE: Architecture and Engineering
WORK: A 4 QUADRANT CMOS ANALOGUE MULTIPLIER
1) I understand what plagiarism is and I am aware of the university policy in this regard.
2) I declare that this final year project report is my original work and has not been submitted
elsewhere for examination, award of a degree or publication. Where other people‟s work or my
own work has been used, this has properly been acknowledged and referenced in accordance
with the University of Nairobi‟s requirements.
3) I have not sought or used the services of any professional agencies to produce this work.
4) I have not allowed, and shall not allow anyone to copy my work with the intention of passing
it off as his/her own work.
5) I understand that any false claim in respect of this work shall result in disciplinary action, in
accordance with University anti-plagiarism policy.
Signature: ………………………………………………………………………………………
Date: ……………………………………………………………………………………………
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ACKNOWLEDGEMENT
First and foremost, I wish to thank the God for guiding me and being by my side throughout my
studies.
I acknowledge the input by my supervisor, Prof. Elijah Mwangi, for the useful comments and
suggestions which have led to the improvement of this project and for the guidance and moral
support that he granted unto me during the development of this project.
An assemblage of this nature could never have been attempted without reference to and
inspiration from the works of others whose details are mentioned in reference section. I also
acknowledge all of them.
Last but not the least to all of my friends and classmates who were patiently extended all sorts of
help for accomplishing this undertaking.
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ABSTRACT
In this project, a four quadrant analogue multiplier based on the 0.18 micron CMOS technology
has been presented. It is based on the square law characteristics of the MOS transistor drain
current, operating in saturation. The multiplier design combines the features of both, the
differential structure of the flipped voltage follower cell, and source follower. This design will
improve the multiplier bandwidth by reducing the power dissipation, with low power supply.
Simulation results are obtained using PSPICE 16.6 for 0.18μm CMOS process with supply
voltage of 0.9Vdc.
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TABLE OF CONTENTS
DECLARATION OF ORIGINALITY…………….……………………………….……………ii
ACKNOWLEDGEMENT……………………………..………………...…………..………….iii
ABSTRACT…………………………………………………….………………….....……...….iv
TABLE OF CONTENTS………………………………….……………………….…..…..…....v
LIST OF FIGURES ……………….………………………….…………………………….….viii
LIST OF TABLES ……………..…………………………………………………………….…ix
LIST OF ABBREVIATIONS ANDACRONYMS………………………………………………x
1 CHAPTER 1- INTRODUCTION ........................................................................................... 1
1.1 BACKGROUND: ................................................................................................................ 1
1.2 PROBLEM STATEMENT .................................................................................................. 3
1.3 OBJECTIVES ...................................................................................................................... 3
1.4 PROJECT SCOPE ............................................................................................................... 3
2 CHAPTER 2-LITERATURE REVIEW ................................................................................. 4
2.1 INTRODUCTION ............................................................................................................... 4
2.2 STRUCTURE AND PHYSICAL OPERATION OF THE ENHANCEMENT-TYPE
MOSFET [1] ................................................................................................................................... 5
2.2.1 DEVICE STRUCTURE ................................................................................................... 5
2.2.2 OPERATION OF A MOSFET [1] ................................................................................... 7
2.2.2.1 OPERATION WITH ZERO GATE VOLTAGE ..................................................... 7
2.2.2.2 OPERATION WITH A GATE VOLTAGE ONLY ................................................. 7
2.2.2.3 APPLYING A SMALL VDS ................................................................................... 11
2.2.2.4 OPERATION AS VDS IS INCREASED ................................................................ 14
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2.3 DERIVATION OF THE ID-VDS RELATIONSHIP .......................................................... 15
2.4 COMPLEMENTARY MOS OR CMOS ........................................................................... 19
2.5 THE DEPLETION-TYPE MOSFET [1] ........................................................................... 20
2.6 PREVIOUS PROJECTS .................................................................................................... 23
3 CHAPTER 3-METHODOLOGY AND DESIGN ................................................................ 25
3.1 INTRODUCTION ............................................................................................................. 25
3.2 SOURCE FOLLOWER ..................................................................................................... 25
3.3 FVF DIFFERENTIAL STRUCTURE (DFVF) ................................................................. 26
3.4 THE COMPLETE MULTIPLIER ..................................................................................... 27
3.5 TRANSISTOR PARAMETERS [4] .................................................................................. 30
4 CHAPTER 4- COMPUTER SIMULATION RESULTS ...................................................... 33
4.1 INTRODUTION ................................................................................................................ 33
4.2 BIAS POINT ANALYSIS ................................................................................................. 33
4.3 DC TRANSFER CHARACTERISTICS ........................................................................... 36
4.4 TRANSIENT ANALYSIS................................................................................................. 38
4.5 PSPICE COMMAND FILE ............................................................................................... 41
4.6 DISCUSSION .................................................................................................................... 43
4.6.1 HAND CALCULATIONS ............................................................................................. 43
4.6.2 COMPUTER SIMULATION RESULTS ...................................................................... 43
5 CHAPTER 5-CONCLUSION AND RECOMMENDATION .............................................. 45
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5.1 CONCLUSION .................................................................................................................. 45
5.2 RECOMMENDATION ..................................................................................................... 46
6 REFERENCES ...................................................................................................................... 47
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LIST OF FIGURES
FIGURE 1-1: BLOCK DIAGRAM OF MULTIPLIER OPERATION ......................................... 1
FIGURE 2-1: PHYSICAL STRUCTURE OF THE ENHANCEMENT-TYPE NMOS
TRANSISTOR: (A) PERSPECTIVE VIEW; (B) CROSS-SECTION. .................................. 5
FIGURE 2-2: (A) CIRCUIT SYMBOL FOR THE N-CHANNEL ENHANCEMENT-TYPE
MOSFET. (B) MODIFIED CIRCUIT SYMBOL (C) SIMPLIFIED CIRCUIT SYMBOL ... 6
FIGURE 2-3: OPERATION WITH ZERO GATE VOLTAGE.................................................... 7
FIGURE 2-4: OPERATION WITH A GATE VOLTAGE ONLY ................................................ 8
FIGURE 2-5: ATTRACTION OF ELECTRONS FROM THE N+ SOURCE AND DRAIN
REGIONS INTO THE CHANNEL. ....................................................................................... 9
FIGURE 2-6: FORMATION OF AN N-CHANNEL BETWEEN THE SOURCE AND THE
DRAIN REGIONS. ............................................................................................................... 10
FIGURE 2-7: AN NMOS TRANSISTOR WITH VGS > VT AND WITH A SMALL VDS
APPLIED ............................................................................................................................... 12
FIGURE 2-8: ID–VDS CHARACTERISTICS OF THE NMOS ................................................... 13
FIGURE 2-9: OPERATION AS VDS IS INCREASED................................................................ 14
FIGURE 2-10: ID VERSUS VDS FOR AN ................................................................................... 15
FIGURE 2-11: DERIVATION OF THE ID–VDS.......................................................................... 16
FIGURE 2-12: CROSS-SECTION OF A CMOS INTEGRATED CIRCUIT ............................. 19
FIGURE 2-13: CIRCUIT SYMBOL FOR AN N-CHANNEL DEPLETION MOSFET ............ 21
FIGURE 2-14: DEPLETION NMOS TRANSISTOR WITH CURRENT AND VOLTAGE
POLARITIES INDICATED .................................................................................................. 21
FIGURE 2-15: ID–VDS CHARACTERISTICS FOR A DEPLETION NMOS ............................ 22
FIGURE 2-16: THE RELATIVE LEVELS OF TERMINAL VOLTAGES OF A DEPLETION-
TYPE. .................................................................................................................................... 22
FIGURE 2-17: THE ID–VGS CHARACTERISTIC IN SATURATION. ..................................... 23
FIGURE 2-18: 45NM MODEL PARAMETERS......................................................................... 24
FIGURE 3-1: SCHEMATIC OF THE SOURCE FOLLOWER CIRCUIT ................................. 26
FIGURE 3-2: SCHEMATIC OF THE FVF DIFFERENTIAL STRUCTURE CIRCUIT ........... 26
FIGURE 3-3: THE COMPLETE FOUR QUADRANT MULTIPLIER CIRCUIT ..................... 28
FIGURE 3-4: PSPICE MODEL EDITOR FOR NMOS .............................................................. 32
FIGURE 4-1: BIAS VOLTAGES ................................................................................................ 34
FIGURE 4-2: BIAS CURRENTS ................................................................................................. 35
FIGURE 4-3: DC TRANSFER CHARACTERISTICS ............................................................... 36
FIGURE 4-4: TRANSIENT ANALYSIS ..................................................................................... 38
FIGURE 4-5: INPUT AND OUTPUT WAVEFORMS ............................................................... 39
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LIST OF TABLES
TABLE 1-1: TYPES OF MULTIPLIERS, THEIR INPUT AND OUTPUT RANGE…………1
TABLE 3-1: LENGTHS AND WIDTHS FOR TRANSISTORS .............................................. 29
TABLE 3-2: VALUES OF DIFFERENT CIRCUIT PARAMETERS ...................................... 29
TABLE 3-3: 0.18µ MOSFET MODEL PARAMETER ............................................................. 30
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LIST OF ABBREVIATIONS AND ACRONYMS
MOSFET- METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR
NMOS- N-CHANNEL METAL OXIDE SEMICONDUTOR
PMOS- P-CHANNEL METAL OXIDE SEMICONDUCTOR
FET- FIELD EFFET TRANSISTOR
JFET- JUNCTION FIELD EFFECT TRANSISTOR
PSPICE- PERSONAL COMPURER SIMULATION PROGRAM WITH INTEGRATED
CIRCUIT EMPHASIS.
BJT- BIPOLAR JUNCTION TRANSISTOR
FVF-FLIPPED VOLTAGE FOLLOWER
VC- COMMON MODE VOLTAGE
VDS-DRAIN TO SOURCE VOLTAGE
VGS-GATE TO SOURE VOLTAGE
Vt-THRESHOLD VOLTAGE
W- WIDTH
L- LENGTH
VDD- DC DRIVING VOLTAGE
g/K’- TRANSCONDUCTANCE
VDsat- SATURATION DRAIN VOLTAGE
IC – INTEGRATED CIRCUIT
I – CURRENT
V – VOLTAGE
R – RESISTANCE
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1 CHAPTER 1- INTRODUCTION
1.1 BACKGROUND: An analog multiplier is a device having two input ports and an output port. The signal at the
output is the product of the two input signals. If both input and output signals are voltages,
the transfer characteristic is the product of the two voltages multiplied by a scaling factor, K,
as shown below in figure 1.1, which has the dimension of voltage. Typical types of different
multiplier realizations have been shown in the table 1.1 below.
Table 1-1 type of multipliers, their input range and output range
V1
V2 Vout=K *V1*V2
K=CONSTANT
From a mathematical point of view, multiplication is a "four quadrant" operation that is to say
that both inputs may be either positive or negative, as may be the output. Some of the circuits
used to produce electronic multipliers, however, are limited to signals of one polarity. If both
signals must be unipolar, we have a "single quadrant" multiplier, and the output will also be
TYPE VX VY VOUT
SINGLE QUADRANT UNIPOLAR UNIPOLAR UNIPOLAR
TWO QUADRANT BIPOLAR UNIPOLAR BIPOLAR
FOUR QUADRANT BIPOLAR BIPOLAR BIPOLAR
Figure 1-1: Block diagram of multiplier operation
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unipolar. If one of the signals is unipolar, but the other may have either polarity, the multiplier is
a "two quadrant" multiplier, and the output may have either polarity (and is "bipolar"). All the
types of the multiplier have been shown in table 1 above.
4 quadrant multiplier is a very useful building block in many circuits such as adaptive filters,
frequency shifters and modulators. These applications are required to operate in low voltage
environment for improving their power efficiency and incorporating with mixed signal systems
to be used in portable applications.
In this project, I have discussed a 4 quadrant analog multiplier circuit which is based on CMOS
technology. This multiplier relies on the quadratic drain current/gate voltage characteristics of
MOS transistors operating in saturation.
The design has been simulated in SPICE simulating software-PSPICE by using model parameter
0.18 micron technology CMOS process.
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1.2 PROBLEM STATEMENT
Recently only a few CMOS multiplier designs have been proposed. To bridge this gap and
to familiarize with designs related to MOS technology the following project has been
realized.
1.3 OBJECTIVES
The project has the following objectives;
1. To investigate a CMOS 4 quadrant analogue multiplier
2. To familiarize with the pspice simulation software.
3. To make comparison between simulation and paper and pencil calculations.
1.4 PROJECT SCOPE
This project entails the following;
Developing a circuitry that shows the implementation of a 4 quadrant multiplier realized
in CMOS technology.
Simulating the design in PSPISE to verify the calculations done by hand.
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2 CHAPTER 2-LITERATURE REVIEW
2.1 INTRODUCTION The FET (field effect transistors) is another type of transistors in the family of transistors. We
have the BJT as one type and the FET as the other. The FET is further divided into the
MOSFET,JFET and the MESFET.
Although the basic concept of the FET has been known since the 1930s, the device became a
practical reality only in the 1960s. Since the late 1970s, a particular kind of FET, the metal oxide
semiconductor field effect transistor (MOSFET), has been extremely popular [1].
Compared to the BJTs, MOS transistors can be made quite small (that is, occupying a small
silicon area on the IC chip), and there, manufacturing process is relatively simple. Furthermore,
digital logic and memory functions can be implemented with circuits that use only MOSFETs.
For these reasons, most very large scale integrated (VLSI) circuits are made at the present time
using MOS technology. Examples include microprocessor and memory chips.
MOS technology has also been applied extensively in the design of analog integrated circuits
and in integrated circuits that combine both analog and digital circuits.
There are two types of MOSFETs;
1. Enhancement type
2. Depletion type
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2.2 STRUCTURE AND PHYSICAL OPERATION OF THE ENHANCEMENT-TYPE
MOSFET [1] The enhancement type MOSFET is the most widely used field effect transistor. In the discussion
below its structure and physical operation is discussed. Also its current voltage characteristics
will be discussed.
2.2.1 DEVICE STRUCTURE The figure 2.1 below shows the physical structure of the n-channel enhancement type MOSFET.
The transistor is fabricated on a p-type substrate, which is a single crystal silicon wafer that
provides physical support for the device. Two heavily doped n-type regions ,indicated in the
figure as the n+ source and n
+ drain regions, are created in the substrate. A thin (0.02 to 0.1µm)
layer of silicon dioxide (SiO2), which is an excellent electrical insulator, is grown on the surface
of the substrate, covering the area between the source and drain regions. Metal is deposited on
top of the oxide layer to form the gate electrode of the device. Metal contacts are also made to
the source region, the drain region, and the substrate, also known as the body. Thus 4 terminals
are brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and the
substrate or body terminal (B).
Figure 2-1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view;
(b) cross-section.
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Figure 2-2: (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit
symbol (c) Simplified circuit symbol
From the figure 2.1(b) it is also observed that the substrate forms p-n junctions with the source
and drain regions. In normal operations, these p-n junctions are kept reversed biased at all times.
Since the drain will be at a positive voltage relative to the source, the two p-n junctions can be
effectively cut-off, by simply connecting the substrate terminal to the source terminal. Thus,
here, the substrate will be considered as having no operation on the device operation, and the
MOSFET will be treated as a three terminal device, having gate(G), source(S), and drain(D).
Note: we shall assume this to be the case in all our descriptions of NMOS, and substrate
terminal connected to dc drive voltage (Vdd) for all PMOS.
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2.2.2 OPERATION OF A MOSFET [1]
2.2.2.1 Operation with zero gate voltage With zero voltage applied to gate, two back-to-back diodes exist in series between drain and
source as shown in the figure 2.3 below. “They” prevent current conduction from drain to source
when a voltage VDS is applied, yielding very high resistance (1012
Ω)
Figure 2-3: Operation with zero gate voltage
2.2.2.2 Operation with a gate voltage only Here we ground the source and the drain, and apply a voltage at the gate terminal with respect to
the source which is at ground potential, hence the name VGS . The positive voltage on the gate
causes a positive build-up of positive charge along the metal electrode. This “build up” causes
free holes to be repelled from region of p-type substrate under gate as shown in the figure 2.4
below.
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Figure 2-4: Operation with a gate voltage only
This “migration” results in the uncovering of negative bound charges, originally neutralized by
the free holes. The positive gate voltage also attracts electrons from the n+ source and drain
regions into the channel as shown in figure 2.5 below.
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Figure 2-5: Attraction of electrons from the n+ source and drain regions into the channel.
Once a sufficient number of “these” electrons accumulate, an n-region is created connecting the
source and drain regions. This provides path for current flow between D and S, as shown in the
figure 2.6 below.
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Figure 2-6: formation of an n-channel between the source and the drain regions.
Correspondingly, the MOSFET in the figure 2.6 shown above is called an n-channel MOSFET
or, alternatively, NMOS transistor. Note that an n-channel MOSFET is formed in a p-type
substrate: the channel is created by inverting the substrate surface from p-type to n-type. Hence
the induced channel is also called an inversion layer.
The value of VGS at which a sufficient number of mobile electrons accumulate in the channel
region to form a conducting channel is called the threshold voltage and is denoted Vt. Obviously,
this induced channel is also known as an inversion layer
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Vt for an n-channel FET is positive. The value of Vt is controlled during device fabrication and
typically lies in the range 1V to 3V.
A p-channel enhancement type MOSFET (PMOS) is fabricated on an n-type substrate with p+
regions for the drain and source, and has holes as charge carriers. The device operates in the
same manner as the n-channel device except that VGS and VDS are negative and the threshold
voltage Vt is negative. Also, the current iD enters the source terminal and leaves through the drain
terminal.
The gate and body of the MOSFET form a parallel plate capacitor with the oxide layer acting as
the capacitor dielectric. The positive gate voltage causes positive charge to accumulate on the top
plate of the capacitor (the gate electrode). The corresponding negative charge on the bottom plate
is formed by the electrons in the induced channel. An electric field thus develops in the vertical
direction. It is this field that controls the amount of charge in the channel, and thus determines
the channel conductivity and, in turn, the current that will flow through the channel when a
voltage VDS is applied.
2.2.2.3 Applying a small VDS Having induced a channel, we now apply a positive voltage VDS between drain and source, as
shown in the figure 2.7 below. The voltage VDS causes a current iD to flow through the induced n
channel. Current is carried by free electrons travelling from source to drain. The magnitude of iD
depends on the density of electrons in the channel, which in turn depends on the magnitude of
VGS. Specifically as VGS=Vt the channel is just induced and the current conducted is still
negligibly small. As VGS exceeds Vt, more electrons are attracted into the channel. We may
visualize the increase in charge carriers in the channel as an increase in channel depth. The result
is a channel of increased conductance or, reduced resistance. In fact, the conductance of the
channel is proportional to the excess gate voltage (VGS-Vt) also known as effective voltage, or
overdrive voltage. It follows that the current iD will be proportional to (VGS-Vt ) and, of course,
to the voltage VDS that causes iD to flow.
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Figure 2-7: An NMOS transistor with VGS > Vt and with a small VDS applied
The figure 2.8 below shows a sketch of iD verses VDS for various values of VGS. It is observed
that the MOSFET is operating as a linear resistance whose value is controlled by VGS. The
resistance is infinite for VGS≤Vt, and its value decreases as VGS exceeds Vt.
The description above indicates that for the MOSFET to conduct, a channel has to be induced.
Then, increasing VGS above the threshold voltage Vt enhances the channel; hence the name
enhancement-mode operation and enhancement type MOSFET. Finally, we note that the current
that leaves the source (iS) is equal to the current that enters the drain terminal (iD), and the gate
current iG=0.
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Figure 2-8: iD–VDS characteristics of the NMOS
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2.2.2.4 OPERATION AS VDS IS INCREASED
Figure 2-9: Operation as VDS is increased.
For this section VGS is held constant at a value greater than Vt, as VDS is increased. The voltage
between the gate and the points along the channel decreases from VGS at the source end to VGS-
VDS at the drain end. Since the channel depth depends on this voltage, we find that the channel is
no longer of uniform depth; rather the channel will take the tapered form as shown in the figure
2.9 above being deepest at the source end and shallowest at the drain end. As VDS is increased,
the channel becomes more tapered and its resistance increases correspondingly. Thus the iD-VDS
curve does not continue as a straight line but bends as shown in figure 2.10 below. Eventually,
when VDS is increased to the value that reduces the voltage between the gate and channel at the
drain end to Vt: that is, VGS-VDS=Vt or VDS=VGS-Vt; the channel depth at the drain end decreases
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to almost zero, and the channel is said to be pinched off. Increasing VDS beyond this point has no
effect to the channel shape, and the current remains constant. The drain current thus saturates at
this value, and the MOSFET is said to have entered the saturation region of operation. The
voltage VDS at which saturation occurs is denoted VDSsat,
……………………………..(2.1)
The region of the iD-VDS characteristic obtained for VDS< VDSsat is called the triode region.
Figure 2-10: iD versus VDS for an
NMOS transistor operated with VGS > Vt.
2.3 DERIVATION OF THE ID-VDS RELATIONSHIP The above description can be used to derive an expression for the iD-VDS relationship depicted in
the figure 2.10 above
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Assuming that a voltage VGS is applied between gate and source with VGS>Vt, and a voltage VDS
is applied between drain and source. First considering operation in the triode region; that is, let
VDS< VGS-Vt. The channel will have the tapered shape as shown in figure 2.11 below.
Consider an infinitesimal portion of the channel of length dx at a point x from the source, and let
the voltage at this point be V(x). The voltage between gate and this point in the channel, [VGS-
V(x)], obviously must be greater than the threshold voltage Vt, and the electron charge dq(x) in
this infinitesimal portion of the channel can be expressed as
………………… (2.2)
Figure 2-11: Derivation of the iD–VDS
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Where Cox is the capacitance per unit area of the parallel plate capacitor formed by the gate
electrode and the channel. The oxide layer forms the dielectric of this capacitor, thus
…………………………… (2.3)
where ƐOX is the permittivity of the silicon oxide and tOX the thickness of the oxide layer.
The voltage VDS produces an electric field along the channel in the negative x-direction. At point
x, this field can be expressed as:
…………………………… (2.4)
The electric field E(x) causes the electron charge dq(x) to drift towards the drain with a
velocity
,
………………………….. (2.5)
……………………….. (2.6)
where µn is the electron mobility in the channel. The resulting drift current can now be found by
multiplying the charge per unit length
, obtained from eqt. (2.1), by the drift velocity in eqt.
(2.6) .
…………………………………. (2.7)
Although evaluated at a particular point in the channel, the current i must be constant at all points
along the channel, and thus i must be negative of the drain to source current iD, giving
……………………………. (2.8)
This can be rearranged in the form:
……………………… (2.9)
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Integrating both sides of this equation for x=0 to x=L, and correspondingly for V (0) =0 to V (L)
=VDS
∫ ∫
………………………… (2.10)
Gives
(Triode region)………………........ (2.11)
This is the expression for iD-VDS characteristic in the triode region.
The expression in the saturation region can be obtained by substituting VDS=VGS-Vt, resulting in
(Saturation region)……………………….. (2.12)
In the expression eqt. (2.11) and (2.12), µnCOX is a constant determined by process technology
used to fabricate the MOS transistor. It is known as the process trans-conductance parameter. It
determines the value of the MOSFET transconductance, and is denoted by k’n and has the
dimension of A/V2.
…………………………………. (2.13)
Observe that the drain current is proportional to the ratio of the channel width W to the channel
length L, known as the aspect ratio of the MOSFET.
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2.4 COMPLEMENTARY MOS OR CMOS
Figure 2-12: Cross-section of a CMOS integrated circuit
As the name implies, complementary MOS technology employs MOS transistors of both
polarities. Although CMOS circuits are more difficult to fabricate than NMOS, the availability of
complementary devices makes possible many powerful circuit-design possibilities. CMOS
technology is rapidly taking over many applications that just a few years ago were possible only
with bipolar devices [1].
The figure 2.12 above shows a cross section of a CMOS chip illustrating how the PMOS and
NMOS transistors are fabricated.
p-type semiconductor provides the MOS body (and allows generation of n-
channel) n-well is added to allow generation of
p-channel
SiO2 is used to isolate NMOS from
PMOS
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2.5 THE DEPLETION-TYPE MOSFET [1] The depletion type MOSFET is similar to that of the enhancement type MOSFET with one
important difference: the depletion type has a physically implanted channel. Thus an n-channel
depletion-type MOSFET has an n-type silicon region connecting the n+ source and the n
+ drain
regions at the top of the p-type substrate. Thus if a voltage VDS is applied between drain and
source, a current iD flows for VGS=0. In other words, there is no need to induce a channel, unlike
the case of the enhancement MOSFET.
The channel depth and hence its conductivity can be controlled by VGS in exactly the same
manner as in the enhancement type device. Applying a positive VGS enhances the channel by
attracting more electrons into it. Here, however we can also apply a negative VGS, which causes
electrons to be repelled from the channel: and thus the channel becomes shallower and its
conductivity decreases. The negative VGS is said to deplete the channel of its charge carriers, and
this mode of operation (negative VGS) is called depletion mode.
As the magnitude of VGS is increased in the negative direction, a value is reached at which the
channel is completely depleted of charge carriers and iD is reduced to zero even though VDS may
still be applied. This negative value of VGS is the threshold voltage of the n-channel depletion-
type MOSFET.
The iD-VDS characteristics are similar to those for the enhancement device except that Vt of the
n-channel depletion device is negative.
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The figure 2.13 below shows the circuit symbol for the n-channel depletion MOSFET.
Figure 2-13: circuit symbol for an N-channel depletion MOSFET
The iD-VDS characteristics of a depletion type n-channel MOSFET for which Vt=-4V and
k’n(W/L)=2mA/V2 are shown in figure 2.14,2.15, 2.16 below. Although these characteristics do
not show the dependence of iD on VDS in saturation, such dependence exists and is identical to
the case for the enhancement type device. It should be noted that since Vt is negative, the
depletion NMOS will operate in the triode region as long as the drain voltage does not exceed
the gate voltage by more than |Vt|. For it to operate in saturation, the drain voltage must be
greater than the gate voltage by at least |Vt| volts.
Figure 2-14: depletion NMOS transistor with current and voltage polarities indicated
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Figure 2-15: iD–VDS characteristics for a depletion NMOS
The figure 2.16 below shows the relative levels of the terminal voltages of the depletion NMOS
transistor for the two regions of operation.
Figure 2-16: The relative levels of terminal voltages of a depletion-type.
Fig 2.17 below shows the iD-VGS characteristics in saturation, indicating both the depletion and
Enhancement modes of operation.
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Figure 2-17: the iD–VGS characteristic in saturation.
The current- voltage characteristics of the depletion type MOSFET are described by the same
equations for the enhancement device except that, for an n-channel depletion device, Vt is
negative.
A special parameter for the depletion MOSFET is the value of drain current obtained in
saturation with VGS=0. This is denoted IDSS and is shown in the figure above, it is also shown
that,
…………………………. (2.14)
2.6 PREVIOUS PROJECTS Many projects and papers have been done and written respectively on the 4 quadrant analogue
multiplier. Previous works have been mainly based on the multiplier with regard to the gilbert
cell and the BJT.
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Acording to [2], there are several means to realize a 4 quadrant analog multiplier and it is also
suggested by [3] that using saturated MOSFET in strong inversion is more practical than any
other means. Recently, based on a square-law relation of saturated MOSFET, various compact
multiplier architectures which are constituted by a circuit cell called a “flipped voltage follower
(FVF)” [4] , have been chronologically proposed in [5], [6]. Most of them feature wide input
range, high operating frequency and low power consumption which are resulted from excellent
manipulations of the square law function in high compactness structures [7].
Latest work to be done in the MOSFET realm was proposed by [8] the technology used was
45nm MOSFET technology, with the topology of a square rooting circuit operated under 1.5V
single supply. This was an improvement from previous designs which required more than 3V for
supply voltage, which was not sufficiently low for modern analog design.
The transistor model parameters were used as shown in figure 2.18 below;
Figure 2-18: 45nm model parameters
In this project, I have improved on the multiplier circuit based on [4] by using 0.18µm model
technology.
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3 CHAPTER 3-METHODOLOGY AND DESIGN
3.1 INTRODUCTION Four-Quadrant analog multipliers are very useful building blocks in many circuits such as
adaptive filters, frequency shifters, and modulators. These applications are required to operate in
low voltage environment for improving their power efficiency and incorporating with mixed
signal systems to be used in portable applications. A four quadrant analog multiplier can be
realized in many ways however, using saturated MOSFET in strong inversion is more practical
than any other means. A design based on a square-law relation of saturated MOSFET, compact
multiplier architectures has been proposed [9].
In this project, we implement a four-quadrant analog multiplier circuit which is based on the
square law characteristics of the MOS transistor, which has been realized in CMOS technology.
This multiplier relies on the quadratic drain-current/ gate-voltage characteristics of MOS
transistors operated in saturation. The proposed multiplier has been simulated in PSPICE by
using model parameter for 0.18μ CMOS process.
The design comprised of two main parts;
1. Source follower
2. Differential flipped voltage follower (square rooting circuit).
3.2 SOURCE FOLLOWER
The figure 3.1 below shows the source follower, where the current through transistor M1 is held
constant, and does not depend on the output current. This circuit is known as the „flipped voltage
follower (FVF)‟. Neglecting body effect and short channel effect, VGSM1 is held constant, and
voltage gain is unity. Circuit is able to source a large amount of current, but its sinking capability
is limited by the biasing current source Ib, due to the low impedance at the output node.
……………………… (3.1)
Where gm1 and gm2 are the transconductance of the transistor M1 and M2 respectively, and r01 is
the output resistance. [4]
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Figure 3-1: schematic of the source follower circuit
3.3 FVF DIFFERENTIAL STRUCTURE (DFVF)
Figure 3-2: schematic of the FVF differential structure circuit
The differential structure based on the FVF cell can be built by adding an extra transistor
connected between M1 and M2 as shown above in figure 3.2 it will be called the differential
FVF structure (DFVF). The circuit consists of an MOS transistor (M3) and the flipped voltage
M1
M2
M3Ib
VDD
Vo
V1
VSS
M1
M2
Vo
VDD
VSS
V1
Vb
M1
M2
Ib
VDD
V1
VSS
M3
IDM3
V3
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follower (M1 and M2). The transistor M3 is used as a simple current to voltage converter. When
the source terminal voltage of M3 is equal to -Vtn then, the current [4];
…………………………………. (3.2)
Where,
…………………………… (3.3)
3.4 THE COMPLETE MULTIPLIER The figure 3.3 below shows the complete four quadrant analog multiplier based on the FVF cell
consisting of the combination of common source amplifier with a differential voltage controlled
square rooting circuit.
The multiplier circuit is formed by common source amplifiers M1-M4 connected to pair of
differential flipped voltage followers (DFVF), M5-M7 and M8-M10.
All the transistors work in the saturation region, and hence the drain currents of M1-M4 are;
…………………….. (3.4)
……………………… (3.5)
……………………… (3.6)
………………………. (3.7)
From (3.4) and (3.5), we find;
ID1=ID2………………………… (3.8)
And from (3.6) and (3.7),
ID3=ID4…………………………. (3.9)
R1
4k
R2
4k
R3
4kR4
4k
R5
4k
R6
4k
M1
Mbreakp
M2
Mbreakp
M3
MbreakP
M4
Mbreakp
M5
MbreakP
M6
MbreakP
M7
MbreakN
M8
MbreakN
M9
MbreakN
M10
Mbreakn
0
V5
0.9Vdc
0
Vc2
0.12Vdc
Vc1
0.7Vdc
Vc
0.35Vdc0
0
0
Vo2
Vo1
V8
0.9Vdc
V12
FREQ = 25KVAMPL = 0.6VOFF = 2vAC = 1v
V34
FREQ = 300MEG
VAMPL = 0.6
VOFF = 2v
AC = 1v
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Figure 3-3: The complete four quadrant multiplier circuit
Where KN is the transconductance parameter, Vtn is the threshold voltage for each n-channel
MOSFET, and the input biasing circuit voltage,
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………………………… (3.10)
………………………... (3.11)
So,
√ √ √ √ √ ……………… (3.12)
Where V12 is the differential input voltage with DC common mode VC1. The non-linear relation
can be removed by injecting the output current into the square rooting circuit, which ID1 is
injected from bias current of the differential-FVF (DFVF).
Similarly, the bias current of the DFVF M8-M10 is obtained by injecting ID4 into M8. This
results in ID5= ID4 and ID8=ID4.
In the DFVF, which operates as a voltage controlled square rooting circuit, we observe that;
……………………….. (3.13)
By applying the square law relation of a p-channel MOSFET, so drain current is;
| | …………………. (3.14)
And input biasing circuit voltage
………………… (3.15)
…………………. (3.16)
Considering the output nodes, the differential output voltage is;
…………………… (3.17)
Where,
……………. (3.18)
…………….. (3.19)
Where V0 is the reference common mode output voltage and R are the load resistors.
Hence;
√ (√ √ ) ………………… (3.20)
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At last substituting (3.12) into (3.20) we get;
√ ………………… (3.21)
Thus voltage gain can be adjusted by the load resistor and transconductance parameters.
Where;
…………………… (3.22)
…………………… (3.23)
3.5 TRANSISTOR PARAMETERS [4]
Proper transistor parameters for the MOS technology must be chosen as per the 0.18µ
technology. The table-3.1 below shows the lengths and widths of the transistor used and the
table-3.2 below shows the different parameters used.
Table 3-1: Lengths and widths for the transistors
TRANSISTOR W(µm) L(µm)
M1-M4 0.5 0.5
M5,M6,M8,M9 17.8 2
M7-M10 110 2
Table 3-2: values of different circuit parameters
PARAMETER VALUE
1. VC=V0 0.35
2. VC1 0.70
3. VC2 0.12
4. R1-R6(KΩ) 4
5. RN, RP (KΩ) 20
6. VDD 0.9
The table 3.3 below shows the values of LEVEL 1 0.18µ MOSFET model parameters for the
two CMOS technologies as used in PSPISE.
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Table 3-3: 0.18µ MOSFET model parameters
Parameter NMOS PMOS
LEVEL 1 1
TOX 4.08e-09 4.08e-09
UO 291 102
LAMBDA 0 0
GAMMA 0.3 0.3
VTO 0.5 -0.45
PHI 0.84 0.8
LD 10e-09 10e.9
JS 8.38e-6 4.00e-07
CJ 1.60e-03 1.00e-03
MJ 0.5 0.45
CJSW 2.04e-10 2.04e-10
MJSW 0.2 0.29
PB 0.9 0.9
CGBO 3.80e-10 3.50e-10
CGDO 3.67e-10 3.43e-10
CGSO 3.67e-10 3.43e-10
The figure 3.4 below shows how the PSPISE MOSFET model was implemented in the instance
menu editor.
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Figure 3-4: PSPICE model editor for NMOS
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4 CHAPTER 4- COMPUTER SIMULATION RESULTS
4.1 INTRODUTION The circuit was simulated with the simulation software cadence ORCAD capture and PSPISE
16.6 lite version.
The simulation software being a powerful tool for design simulation, 3 different analysis was
taken into account;
1. Bias point analysis
2. Dc transfer characteristics
3. Transient analysis
4.2 Bias point analysis Here the circuit was simulated to find the dc bias voltages and currents at the various points in
the circuit. It was also done to verify that the circuit was in saturation, as shown in fig 4.1 and 4.2
below;
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Figure 4-1: bias voltages
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Figure 4-2: bias currents
From the bias point details, it was also verified that all transistors operated in saturation;
VGS1= VGS2= V1= 0.8V > 0.5V (VTO)
VGS3= VGS4= V2= 0.6V > 0.5V (VTO)
VSG6-VSG5 = V3-V4
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V3= 0.22V > -0.5V
V4=0.02V > -0.5V
4.3 DC transfer characteristics The dc transfer characteristics of the multiplier based on the FVF cell was obtained when V12 is
the input voltage was varied from -0.1V to 0.1V with increment of 0.01V, and V34 was varied
from -.008V to 0.08V with increment of 0.1V. The resulting figure 4.3 shown below of the dc
transfer characteristic of the multiplier is shown below.
Figure 4-3: DC transfer characteristics
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OUTPUT FILE
** Creating circuit file "trial_3.cir"
*Analysis directives:
.DC LIN V_V14 -2V 2V 1V
+ LIN V_V13 -0.2V 0.2V 0.05V
.OPTIONS ADVCONV
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source MULTIPLIER DESIGN 1
R_R1 N00738 N00122 4k TC=0,0
R_R2 N00731 N00122 4k TC=0,0
R_R3 N00126 N00780 4k TC=0,0
R_R4 N00126 N00798 4k TC=0,0
R_R5 VO2 VO2 4k TC=0,0
R_R6 VO2 VO1 4k TC=0,0
M_M1 N00410 N00890 N00605 N00605 MbreakP + L=2u + W=110u
M_M2 N00890 N00738 N00410 N00605 MbreakP + L=2u + W=17.8u
M_M3 VO1 N00731 N00378 N00605 MbreakP + L=2u + W=17.8
M_M4 N00378 N00382 N00605 N00605 MbreakP + L=2u + W=110u
M_M5 N00382 N00738 N00378 N00605 MbreakP + L=2u + W=17.8
M_M6 VO2 N00731 N00410 N00605 MbreakP + L=2u + W=17.8u
M_M7 N00890 N00780 0 0 MbreakN + L=0.5u + W=0.5u
M_M8 VO2 N00780 0 0 MbreakN + L=0.5u + W=0.5u
M_M9 VO1 N00798 0 0 MbreakN + L=0.5u + W=0.5u
M_M10 N00382 N00798 0 0 MbreakN + L=0.5u + W=0.5u
V_V5 N00605 0 0.9Vdc
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V_Vc2 N00122 0 0.12Vdc
V_Vc1 N00126 0 0.7Vdc
V_Vc VO2 0 0.35Vdc
V_V13 N00738 N00731 DC 0Vdc AC 1Vac
V_V14 N00780 N00798 DC 1Vdc AC 1Vac
**** RESUMING trial_3.cir ****
.END
4.4 Transient analysis The application of the four quadrant multiplier as a balance modulator is performed when the
input voltage Vid1 is 0.6V, 300MHz sinusoidal which is the carrier signal, and is multiplied with
another signal which is the modulating signal Vid2 which is 0.6V, 250MHz. Both the input
Signals have been shown below in figure4.4 and 4.5, and their output also shown.
Figure 4-4: transient analysis
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Figure 4-5: input and output waveforms
Output file
*Analysis directives:
.TRAN 0 3ms 0 3m
.OPTIONS ADVCONV
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source MULTIPLIER DESIGN 1
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R_R1 N00738 N00122 4k TC=0,0
R_R2 N00731 N00122 4k TC=0,0
R_R3 N00126 N00780 4k TC=0,0
R_R4 N00126 N00798 4k TC=0,0
R_R5 VO2 VO2 4k TC=0,0
R_R6 VO2 VO1 4k TC=0,0
M_M1 N00410 N00890 N00605 N00605 Mbreakp+ L=2u + W=110u
M_M2 N00890 N00738 N00410 N00605 Mbreakp + L=2u + W=17.8u
M_M3 VO1 N00731 N00378 N00605 Mbreakp + L=2u + W=17.8
M_M4 N00378 N00382 N00605 N00605 Mbreakp + L=2u + W=110u
M_M5 N00382 N00738 N00378 N00605 Mbreakp + L=2u + W=17.8
M_M6 VO2 N00731 N00410 N00605 MbreakP + L=2u + W=17.8u
M_M7 N00890 N00780 0 0 Mbreakn + L=0.5u + W=0.5u
M_M8 VO2 N00780 0 0 MbreakN + L=0.5u + W=0.5u
M_M9 VO1 N00798 0 0 MbreakN + L=0.5u + W=0.5u
M_M10 N00382 N00798 0 0 Mbreakn + L=0.5u + W=0.5u
V_V5 N00605 0 0.9Vdc
V_Vc2 N00122 0 0.12Vdc
V_Vc1 N00126 0 0.7Vdc
V_Vc VO2 0 0.35Vdc
V_V6 N00780 N00798 +SIN 0 0.4 25K 0 0 0
V_V7 N00738 N00731 +SIN 0 -0.4 1K 0 0 0
**** RESUMING trial_3.cir ****
.END
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4.5 PSPICE COMMAND FILE .subckt fvf350 11 18 17 2 13 5 6 15
E1 17 16 9 8 1E4
E2 16 18 9 8 1E4
m1 3 2 15 0 n w=0.97u l=0.97u NMOS
m2 8 2 15 0 n w=0.97u l=0.97u NMOS
m3 9 13 15 0 n w=0.97u l=0.97u NMOS
m4 12 13 15 0 n w=0.97u l=0.97u NMOS
m5 3 5 4 11 p w=48.06u l=3.88u PMOS
m6 8 6 4 11 p w=48.06u l=3.88u PMOS
m7 4 3 11 11 p w=297.05u l=3.88u PMOS
m8 12 5 10 11 p w=48.06u l=3.88u PMOS
m9 9 6 10 11 p w=48.06u l=3.88u PMOS
m10 10 12 11 11 p w=297.05u l=3.88u PMOS
*sinwave
*R1 1 2 4k
*R2 1 13 4k
*R3 7 5 4k
*R4 7 6 4k
*R5 14 8 4k
*R6 14 9 4k
*Rn 17 8 20k
*Rp 18 9 20k
.ends fvf350
X1 11 18 17 2 13 5 6 15 fvf350
*transis
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R1 1 2 4k
R2 1 13 4k
R3 7 5 4k
R4 7 6 4k
R5 14 8 4k
R6 14 9 4k
Rn 17 8 20k
Rp 18 9 20k
vdd 11 0 1.5v
vss 15 0 0v
VCM 16 0 DC 1 ac 0 0
vc 14 0 DC 0.35 ac 0 0
vc1 1 0 DC 0.70 ac 0 0
vc2 7 0 DC 0.12 ac 0 0
*vx 2 13 DC 1 ac 1 0
*vy 5 6 DC 0 ac 1 0
.DC vx -2 2 1 vy -0.2 0.2 0.5
.DC vx -0.1 0.01 0.1 vy -0.08 0.1 0.08
.Print dc v(8)
*sinwave
v1 2 13 sin(0v 1v 25k)
v2 5 6 sin(0v -0.4v 1k)
.tran 0.1m 1m
.probe
.plot tran v(2) v(5) v(8) v(9)
.END
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4.6 DISCUSSION The results for the hand calculations and simulation were compared for the multiplier and the
results below were obtained;
The output of the multiplier is given as;
√ (√ √ ) ……………………………….. (4.1)
Where VID2 is differential input voltage V3-V4
Also,
√ √ √ √ √ ………………………. (4.2)
Thus
√ √ …………………………….. (4.3)
4.6.1 Hand calculations
For NMOS, K‟n = 246µA/v2 and Vt= 0.5v
For PMOS, K‟p = -86.1µA/v2
and Vt = -0.5v
Hence;
V1-V2=0.2V
V3-V4=0.2V
Inserting the values,
√ √
= 0.0475V
4.6.2 COMPUTER SIMULATION RESULTS
………………………………… (4.4)
VO1=350mV
V02=324.2mV
Hence; =350 - 324.2mV
=25.8mV
=0.0258V
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Difference = calculated – simulated
= 0.0475 – 0.0258
= 0.0217
= 45.68%
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5 CHAPTER 5-CONCLUSION AND RECOMMENDATION
5.1 Conclusion The project was aimed at designing and simulating a four quadrant analogue multiplier in 0.18
micron CMOS technology. The design of the circuit was then created in comparison with the
gilbert cell design for an analogue multiplier, and was simulated in PSPICE simulation tool.
The objectives of the project were met accordingly although not to the required standard needed
due to some flaws in the design and also because of limitations in the properties of the
MOSFETS in the design. Hand calculations were compared to the simulation results, and an
error of 45.68% was obtained.
However, the 4 quadrant CMOS analogue multiplier were investigated and it was found the
resulting multiplier circuit is improved to be more compact than the gilbert cell. As a result, the
proposed multiplier provides low noise, low delay and low static power consumption. Simulation
results are given to verify the multiplier circuit performances.
The objectives also entailed the familiarization of the simulation tool PSPICE which was done
accordingly as required, however there is still more to learn and investigate yet in the software.
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5.2 Recommendation
Although this project went a long way in designing a 4 quadrant analogue multiplier, the
objectives of the project were not meant up to its full requirements. It would be recommended to
the department and also to the student‟s body as a whole to put more effort in researching about
the MOSFETS and its applications and also to try more projects using the FET transistor, which
is trending at the moment in the world.
It is also recommended for more usage of the simulation software PSPICE to get accurate results
which can be compared to the hand calculations done in the lab, and also to familiarize with the
tool.
A new square rooting circuit can be used for realizing a better CMOS four-quadrant analog
multiplier, to have better output results for the multiplier. Also a design can be performed in the
triode and sub-threshold region and be compared to the results obtained in the saturation region.
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6 REFERENCES
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[2] G.HAN AND E. SANCHEZ-SINENCIO, "CMOS TRANSCONDUCTANCE
MULTIPLIERS: A TUTORIAL," IEEE TRANS, CIRCUITS SYST II, VOL. 45, NO. 12, PP.
1550-1563, DECEMBER 1998.
[3] B. MAUNDY AND M. MAINI, "A COMPARISON OF THREE MULTIPLIER BASED ON
THE VGS TECHNIQUE FOR LOW VOLTAGE APPLICATION," IEEE TRANS.
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TRANSCONDUCTOR/SQUARER AND FOUR QUADRANT MULTIPLIER FOR
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[6] R.G.CARVAJAL AND J. MARTINNEZ-HEREDIA J. RAMIREZ- ANGULO, "1.4V
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[7] W.NGAMKHAM, W. KIRANON N. KIATWARIN, "A COMPACT LOWVOLTAGE MOS
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[8] SUPRIYO SRIMANIi, PROF. BANSIBADAN MAJI SARADINDU PANDA, "HIGH
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[9] KLAAS BULT AND HANS WALLINGA, "A CMOS FOUR QUADRANT ANALOG
MULTIPLIER," TWENTE UNIVERSITY OF TECHNOLOGY, TWENTE, IEEE
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