IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERINGIEEJ Trans 2012; 7: 74–80Published online in Wiley Online Library (wileyonlinelibrary.com). DOI:10.1002/tee.21698

Paper

Common-Mode Gain Reduction Technique and its Applications

Nawatt Silawan∗, Non-member

Nicodimus Retdian∗∗, Member

Shigetaka Takagi∗a, Member

This paper proposes a common-mode gain reduction technique and a new approach for a balanced-type system design. Twodesign examples of a balanced-type operational transconductance amplifier and a balanced-type filter are given. The proposedscheme employs the proposed common-mode gain reduction technique together with the common-mode feedback (CMFB)network, which is used only to set a bias, to meet requirements of common-mode rejection. Compared with the conventionalmethod, which uses the CMFB that has a higher gain than the one used in the proposed scheme, the proposed method showsreduction in design complexities and relaxation of the stability conditions. 2011 Institute of Electrical Engineers of Japan.Published by John Wiley & Sons, Inc.

Keywords: balanced-type system, operational transconductance amplifier (OTA), filter, common-mode feedback (CMFB)

Received 16 March 2010; Revised 18 October 2010

1. Introduction

Conventionally, a balanced-type system uses a common-modefeedback (CMFB) circuit to lower an undesirable common-modegain. However, the technique leads to many problems includingcomplexities in design and stability issues.

To relax design complexities, the common-mode gain reductiontechnique proposed by our group [1]–[3] is applied for systemimplementation to achieve low common-mode gain over a desiredfrequency range, while the DC bias setting is attained by theCMFB, which has a low gain. This CMFB gain does not needto be high since it is not aimed for common-mode gain rejectionbut only for DC bias setting.

To show the effectiveness of the proposed technique, firstthe technique is applied for a balanced-type operational trans-conductance amplifier (OTA) implementation, and then thedesigned OTA is employed in a balanced-type OTA-C filterrealization.

Section 2 states the problems of the balanced-type system designusing a CMFB. To relax those problems, the common-mode gainreduction technique is derived in Section 3. Section 4 shows designexamples of a balanced-type OTA and a balanced-type OTA-Cfilter. Finally, Sections 5 and 6 summarize simulation results andconclusions.

2. Complexities in Design Using CMFB

Consider the balanced-type system operating with common-mode inputs shown in Fig. 1. To reduce undesirable common-mode output signals, a CMFB is employed. Let the transferfunction of the main system in the CMFB path be HCM(s) and

a Correspondence to: Shigetaka Takagi. E-mail: takagi@ec.ss.titech.ac.jp

* Department of Communications and Integrated Systems, Tokyo Instituteof Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550, Japan

** Global Edge Institute, Tokyo Institute of Technology, 2-12-1 Ookayama,Meguro-ku, Tokyo 152-8550, Japan

the transfer function of the CMFB be HCMFB(s). These transferfunctions are approximated by first-order transfer functions as

HCM(s) =ACM

(1 − s

ωZ

)

1 + s

ωCM

(1)

HCMFB(s) = ACMFB

1 + sωCMFB

(2)

The zero in HCM(s) is caused by a parasitic capacitor connectedbetween the feedback path input of the main system and the output,and is usually the cause of instability since it contributes a negativephase shift [4]. For stability, the loop gain of this feedback mustbe considered, and it is written as

HCM(s)HCMFB(s) =ACM ACMFB

(1 − s

ωZ

)(

1 + s

ωCM

) (1 + s

ωCMFB

) (3)

The open-loop gain determines the common-mode gain reduc-tion of the system. To achieve a low common-mode gain output,the loop gain should be high. Also, an open-loop phase marginneeds to be high enough to confirm stability [5] despite some mis-match effects are included. As a result, both the gain and bandwidthof the CMFB must be properly chosen.

To relax the design complexities, the proposed common-modegain reduction technique described in Section 3 is used to decreasethe common-mode gain instead of the high-gain CMFB while theDC bias setting is achieved by the CMFB that has low gain asshown in Fig. 2. Note that the word ‘low-gain CMFB’ will beused for this kind of CMFB throughout this paper.

3. Common-Mode Gain Reduction Technique

In this analysis, we are interested only in the common-modegain due to a common-mode signal. Consider a differential pairand its common-mode half circuit as shown in Fig. 3.

2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

COMMON-MODE GAIN REDUCTION TECHNIQUE AND ITS APPLICATIONS

Fig. 1. Balanced-type system with a CMFB

Fig. 2. Balanced-type system using the common-mode gain reduc-tion technique with the low-gain CMFB

Fig. 3. Differential pair and its common-mode half circuit

Before going to the next step, a small-signal model ofa metal–oxide–semiconductor field-effect transistor (MOSFET)should be considered.

Based on the voltage–current relationship of a MOSFET in thesaturation region, i.e.

iDS = K (vGS − VTH)2(1 + λvDS) (4)

where K = µn CoxW /2L and λ is the channel length modulationcoefficient, the small-signal representation of the MOSFET can bemodeled by a voltage-controlled current source with a conductancebetween drain and source terminals as shown in Fig. 4.

The body effect is neglected in this derivation. Practically, thetriple-well process can be used, or the use of PMOS transistorsinstead of NMOS transistors can eliminate the body effect problem.The small-signal parameters in Fig. 4 can be derived using (4) andtheir values are

gm = 2IDS

VGS − VTH(5)

gd ≈ λIDS (6)

Use of this model changes the common-mode half circuit inFig. 3 into the small-signal represention shown in Fig. 5(a). The

Fig. 4. Small-signal model of the MOSFET operating in thesaturation region

Fig. 5. Differential pair (a) small signal equivalent circuit (b)Thevenin’s equivalent circuit representation

Fig. 6. Common-mode signal cancellation

circuit in Fig. 5(b) is equivalent to the circuit in Fig. 5(a), and itimplies that the common-mode output is caused by the couplingof the input signal to the output by the voltage-controlled voltagesource.

Assume that an additional voltage source can be inserted inseries to the former but in the opposite direction as shown inFig. 6 where the voltage source is enclosed by the dashed line.The insertion will result in no coupling path from the input signalto the output when the circuit operates in the common mode.

To realize this idea, consider Fig. 7. The representation inFig. 7(a) can be transformed into Fig. 7(b) where gds and gmC

are equal to gdy + gdc and gds gmX /gdX , respectively.

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N. SILAWAN, N. RETDIAN, AND S. TAKAGI

Fig. 7. Common-mode gain reduction technique derivation

Fig. 8. Realization of the common-mode gain reduction technique

It is apparent from the small-signal model in Fig. 4 that thecircuit in Fig. 7(b) can be implemented using MOSFETs as shownin Fig. 8 where subscripts X, C, and Y refer to those of the maintransistor, the compensating transistor, and the tail current-sourcetransistor.

From the derivation, the condition for common-mode signalcancellation is

gmC = gmX (gdC + gdY )

gdX(7)

Substitution of (5) and (6) into (7) gives

IDSX

IDSC= λX − λC − λY

λY(8)

where IDS stands for a drain-to-source bias current. Also, the designparameter for the tail current source is changed from gdS to gdY .

The overall circuit of the differential pair with the common-mode gain reduction technique circuitry is presented in Fig. 9without loading for generalization.

Equation (8) shows that the technique is more or less dependenton the parameter mismatches. However, the reduction of common-mode gain is still achieved at some level even if parametermismatches occur.

4. Applications

4.1. Balanced-type OTA An example of a balanced-type OTA design is presented. The OTA using the DC bias offset

Fig. 9. Differential pair using the common-mode gain reductiontechnique

Fig. 10. OTA using the DC bias offset technique

technique [6,7] shown in Fig. 10 is chosen as the basic cell formodification.

Note that M1 –M4 have the same channel width and channellength. To consider the operation principle of this OTA, it isassumed that λvDS << 1 in (4). As a result, iDS becomes

iDS = K (vGS − VTH)2 (9)

From (9), the relationship between a differential output currentand a differential input voltage of the circuit in Fig. 10 can bewritten as

iO+ − iO− = Gm (vIN+ − vIN−) (10)

where Gm = 2KVB and VB is the offset voltage inserted betweengate terminals of two transistors. Transconductance of the OTAcan be tuned by varying the value of VB .

To implement the common-mode gain reduction technique intothis basic OTA, consider (8). The right-hand side of this equationis dependent on the characteristics of the transistors only whilethe opposite side is the current ratio, which can be changed bythe tuning voltage VB . Therefore, to design the compensationpart, which can maintain the current ratio despite the changes ofVB , two compensation transistors are used. Figure 11 shows thecommon-mode half circuit of the OTA with its common-modegain reduction technique circuitry. MC1 and MC4 are designedto have the same channel width and channel length. Equation(8) now can be modified by substituting IDSX = IDS1 + IDS4 andIDSC = IDSC1 + IDSC4.

However, the design in Fig. 11 is not compact, and theadditional circuit for common-mode gain reduction results inhigher power consumption. To compromise this problem, assumethat the tuning voltage VB and its tuning range are small comparedto the biased gate-to-source voltage. By this assumption, the effectof the tuning voltage on the current ratio is low, and can beneglected. Thus, only one transistor can be used to compensate forthe common-mode signals of M1 and M4. The improved balanced-type OTA circuit is shown in Fig. 12.

76 IEEJ Trans 7: 74–80 (2012)

COMMON-MODE GAIN REDUCTION TECHNIQUE AND ITS APPLICATIONS

Fig. 11. Common-mode half circuit of the OTA with the common-mode gain reduction technique circuitry

Fig. 12. Balanced-type OTA using the common-mode gain reduc-tion technique

4.2. Balanced-type OTA-C filter Figure 13 shows atypical balanced-type second-order low-pass filter structure. Thedashed line in Fig. 13 indicates the CMFB network. Gm ’s inFig. 13 represent transconductance cells, and their differentialinput–output conversion is shown in Fig. 14.

Each transconductance cell can be realized using the OTAsin Section 4.1. By connecting each output port of OTAs in

Fig. 13. Filter structure

Fig. 14. Transconductance cell

Fig. 15. Transconductance cell using the basic OTA

Fig. 16. Transconductance cell using the balanced-type OTA withthe common-mode gain reduction technique circuitry

Figs 10 and 12 to a fixed-biased PMOS transistor with anotherPMOS transistor that is used for the CMFB, the resulting circuitsare shown in Figs 15 and 16, respectively.

By using all transconductance cells with the same value Gm , thefilter transfer function is given by

Hdiff(s) = (Gm/CL)2

s2 + s(Gm/CL) + (Gm/CL)2(11)

The transfer function shows the characteristic of the second-orderlow-pass filter which has unity quality factor and a bandwidth ofGm /CL.

To implement the balance-type OTA-C filter, conventionally theOTA in Fig. 15 is used for all transconductance cells in Fig. 13with the the CMFB circuits that have high DC gains. However, asmentioned in the Section 2, the CMFB circuit may cause designproblems including design complexities and stability issues.

To reduce complexities in design, the balanced-type OTAs usingthe common-mode gain reduction technique are used for the inputand output stage transconductance cells of the filter instead of thebasic OTAs. The resulting circuit is shown in Fig. 17.

Since the common-mode gain is reduced by the common-modegain reduction technique circuitry, the CMFBs with high gain arenot required. The only requirement of the CMFB circuit is settingthe DC bias. Thus, the low-gain CMFBs are used. Consequently,the design complexities and the stability conditions due to theCMFB can be relaxed.

5. Simulation Results

A 0.18-µm CMOS BSIM3 model was used in the simulations,and the triple-well process was assumed. The supply voltage wasset to 2.5 V.

5.1. Balanced-type OTA The conventional OTA inFig. 10 and the proposed OTA in Fig. 12 were designed using theparameters as shown in the Tables I and II, respectively. Thesetwo OTAs were designed to have the same total current flow-ing in the main transistors M1 to M4, which is 109.5 µA. The

77 IEEJ Trans 7: 74–80 (2012)

N. SILAWAN, N. RETDIAN, AND S. TAKAGI

Fig. 17. Balanced-type filter using the proposed scheme

Table I. Design parameters of the OTA in Fig. 10

Transistor L (µm) W (µm)

M1,2,3,4 (Fig. 10) 0.18 1MS 1.25 10.23

Table II. Design parameters of the OTA in Fig. 12

Transistor L (µm) W (µm)

M1,2,3,4 (Fig. 12) 0.18 1MC 1 1MY 1.25 12

total current drawn by two compensation transistors in Fig. 12 isequal to 19.0 µA or around 17.4% of the total current in the maintransistors.

5.1.1. Linearity The linearity is evaluated in terms of thelinearity error defined as

Error = Gm(vIN+ − vIN−) − (iO+ − iO−)

Gm (vIN+ − vIN−)× 100% (12)

where Gm is the transconductance of the OTAs.By connecting the output terminals of each OTA to the

appropriate voltage sources for probing the output current whenOTAs operate in a differential mode, the results show thatboth types of OTA have approximately the same differentialcharacteristics, that is, linearity errors of both OTAs are lessthan 1% over ±80 mV input range and their Gm ’s are equal to1.467 × VB [mS] while VB can be tuned from 0.05 to 0.08 V. Notethat the small value of the tuning voltage VB can be achieved bythe circuit shown in Fig. 18.

5.1.2. Common-mode gain To observe the common-mode gain of OTAs, 20-k� resistors were used as loads connectedto the output terminals of OTAs in Figs 10 and 12 while VB ’s in

Fig. 18. Circuit used to synthesize small offset voltage

0

–20

–40

–60

–10.0

–30.0

–50.0

dB

1 10 100 1k 10k 100k 1M 10M 100M 1G

f(Hz)

24.77dB

Conventional

Proposed

OTA common-mode gain Amplitude (dB) : f(Hz)Conventional

Proposed

Fig. 19. Common-mode gain compared between the OTA usingthe common-mode gain reduction technique and the conventional

OTA

both OTAs were set to 0.08 V. The common-mode gains are plot-ted in Fig. 19 along with comparisons between the conventionalOTA and the proposed OTA. The results show an improvementin common-mode gain reduction of about 24.77 dB from low fre-quencies to around 1 MHz, and this difference gradually decreasesto zero at around 100 MHz.

5.1.3. Effects of Mismatches To show the effects of mis-matches, a Monte Carlo analysis was carried out for the proposedOTA in Fig. 12 with 20 k� resistors attached to its outputs. Inthis analysis, channel lengths and channel widths of all transistorsin Fig. 12 were set to be varied independently and each variablehad a uniform distribution. The Monte Carlo analysis was run with100 iterations.

The results show that the common-mode gain reduction ischanged from 24.77 to 12.87 dB and 4.02 dB for 1 and 5%variation, respectively, for the worst case.

5.2. Balanced-type OTA-C filter The conventionalapproach and the proposed scheme were used for filter implemen-tation as suggested in Section 4.2 to make comparisons betweentheir performances.

5.2.1. Differential mode response Second-order low-passfilters with a 100-MHz cut-off frequency and a unity qualityfactor were designed by setting all transconductance and CL’sin Figs 13 and 17 to 117.4 µS and 187 fF, respectively. Fromsimulation results shown in Fig. 20, all filters have more orless the same characteristic in the differential mode. Extractedfrom the simulation data, the conventional filter has 101.4 MHzbandwith with a quality factor of 0.66, while the proposed filter has99.2 MHz bandwith with a quality factor of 0.67. The degradationof the quality factor and the shift of the cutoff frequency are dueto the finite output resistance of OTAs and parasitic capacitance atthe OTAs’ output.

5.2.2. Common-mode response The circuit in Figs 21and 22 are used for the CMFBs in the conventional filter and thelow-gain CMFBs in the proposed filter, respectively.

At DC bias, the circuit in Fig. 22 acts like a voltage shifterthat shifts the output voltage at the node “FB” from the voltage atinputs by a constant value. When it is used in a feedback topologywith transconductance cells in Figs 15 or 16, it gives a voltageshift between a transconductance cell output and a CMFB node.Hence, the DC bias level at the output of the transconductance cellcan be justified, and a reference voltage is not required. For thecommon-mode signal, the circuit in Fig. 22 will make the feedback

78 IEEJ Trans 7: 74–80 (2012)

COMMON-MODE GAIN REDUCTION TECHNIQUE AND ITS APPLICATIONS

0

–800°

–20.0

–40.0

–60.0

–100.0

–200.0

1meg

dBde

g

10M 100M 1G f(Hz)

180°

Filter characteristic (dBV) : f(Hz)Conventional

Proposed

Conventional

Proposed

(deg) : (Hfz)

Fig. 20. Differential mode response of the conventional and pro-posed filters

Fig. 21. CMFB topology

Fig. 22. Low-gain CMFB topology

transistors of the transconductance cells act like diode-connectedPMOS transistors, which lower the circuit’s common-mode gain.In the opposite way, these PMOS transistors operate as currentsources in a differential mode. Thus, the circuit’s differential gainis still high.

To make fair comparisons between the conventional and pro-posed methods, two filters were designed with the same powerconsumption and DC common-mode gain. To guarantee the sta-bility of the filters, phase margin of each controlled loop in thefilters is required to be at least 45◦ or more.

The designed conventional filter consumes 489 µA of total cur-rent. Stability is justified by the open-loop gains of CMFB loops,which determine the common-mode levels of internal and outputnodes of the filter. Each CMFB loop consists of a CMFB amplifierand a PMOS feedback transistor. The open-loop gains of internaland output nodes’ CMFB loops are 32.84 and 33.50 dB, while

–30

–60

–40.0

–50.0

–70.0

–80.0

–100.0

–110.0

–90

–1201 10 100 1k 10k 100k 1M 10M 100M 1G

f(Hz)

(dBV) : f(Hz)Conventional

Proposed

Filter common-mode gain

Conventional

Proposed

dB

Fig. 23. Common-mode gains compared between the filters usingproposed and conventional methods

their unity gain frequencies are 8.41 and 3.13 MHz, respectively.Phase margins of both CMFB loops are about 45◦.

The proposed filter consumes 490 µA of total current. Theopen-loop gains of internal and output nodes’ CMFB loops are16.91 and 15.00 dB, while their unity gain frequencies are 66.17and 28.77 MHz, respectively. Furthermore, phase margins ofinternal and output nodes’ CMFB loops are 53.58◦ and 82.33◦,respectively.

Note that the bandwidth of CMFBs in the conventional filterhave to be limited by inserting CB as shown in Fig. 21 owing tothe conditions of phase margin, desired DC common-mode gain,and limitation in current consumption.

The simulation results in Fig. 23 show the comparison betweenthe common-mode gain of the conventional and proposed filters.

With the same power consumption, the proposed techniqueshows advantages over the conventional approach by providinga wider frequency band of common-mode gain regulation. Inaddition, the proposed scheme is easier to be designed since thestability condition for CMFB design is relaxed.

6. Conclusions

A common-mode gain reduction technique has been proposed.The derivation of the proposed technique has been presented indetail and two applications have been given.

The balanced-type OTA using the common-mode gain reductiontechnique shows the advantage over the conventional circuitwith an improvement in the common-mode gain reduction about24.77 dB from low frequencies to around 1 MHz, and the gapgradually decreases to zero at about 100 MHz. Monte Carlosimulation shows the effects of variations in channel lengths andchannel widths of the transistors on the common-mode rejection.A variation of 1% in the parameter reduced the improvement incommon-mode gain from 24.77 to 12.87 dB for the worst case.

For balance-type OTA-C filter design, the proposed schemecan help in reducing design complexities and stability problemssince a low-gain CMFB and additional compensating transistorsare used instead of a high-gain CMFB, which may easily causeinstability. Also the proposed scheme shows the advantage overthe conventional approach as suggested in the design examplein Section 5.2; that is, for the same power consumption andDC common-mode gain, the proposed scheme shows a widerfrequency range of common-mode gain regulation.

Compared to a conventional cascade structure used for common-mode gain reduction, the proposed technique can serve the samepurpose without effects on an output swing.

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However, there are some issues to be discussed. First, linearityof the OTA used in this paper is limited to the small-input rangesince the OTA struture has been derived using the Square Lawwhile the short-channel device does not perfectly follow thischaracteristic. However, this issue does not strongly affect theperformances derived by our proposed technique. Alternatively,other techniques for highly linear OTA implementation based ona differential pair can be used. Second, realization of the offsetvoltage VB using the circuit in Fig. 18 may have some problemsfrom the variation of threshold voltages of both PMOS and NMOStransistors since the requied offset voltage is very low. However,this can be solved by an alternative structure of OTA without offsetvoltage insertion.

For the future work, the effects due to mismatches on theproposed technique should be improved, and the use of theproposed technique in other circuit blocks should be considered.

Acknowledgments

This work was supported by the VLSI Design and Education Cen-ter(VDEC), University of Tokyo, in collaboration with Synopsys, Inc.

References

(1) Uehara K, Retdian N, Takagi S. Common-mode noise rejection tech-niques in mixed-signal SoC. IEEJ The Papers of Technical Meetingon Electronic Circuits 2009; 51:79–84.

(2) Silawan N, Retdian N, Takagi S. Balanced-type OTA using common-mode gain reduction technique. IEEJ The Papers of Technical Meetingon Electronic Circuits 2009; 65:13–18.

(3) Silawan N, Retdian N, Takagi S. Balanced-type filter using common-mode gain reduction technique. Proceedings of the 2009 (12th) IEEJInternational Analog VLSI Workshop 2009;107–112.

(4) Razavi B. Design of Analog CMOS Integrated Circuits. McGraw-Hill: Singapore; 2001.

(5) Nise NS. Control Systems Engineering. 4th ed. John Wiley & Sons(Asia) Pte. Ltd: 2004.

(6) Bult K, Wallinga H. A class of analog CMOS circuits based on thesquare-law characteristic of an MOS transistor in saturation. IEEEJournal of Solid-State Circuits 1987; 3:357–365.

(7) Wang Z, Guggenbuhl W. A voltage-controllable linear MOStransconductor using bias offset technique. IEEE Journal of Solid-State Circuits 1990; 25(1):315–317.

Nawatt Silawan (Non-member) was born in Bangkok, Thailand,in 1983. He received the B.E. degree (first classhonours) from Chulalongkorn University, Thai-land, in 2006. In the same year, he joined as a co-researcher in the biosensor project for peritonealdialysis machine at the Institute of BiomedicalEngineering, Imperial College, London. Since

2009, he has been pursuing the Master’s degree at the TokyoInstitute of Technology, Japan. His main research interests includeanalog integrated circuits and low power biomedical electronics.

Nicodimus Retdian (Member) was born in Malang, Indonesia,on March 3, 1976. He received the B.E., M.E.,and Doctor of Engineering degrees from theTokyo Institute of Technology, in 2000, 2002and 2005, respectively. From 2005, he workedas an Assistant Professor in the Departmentof Communications and Integrated Systems, the

Graduate School of Science and Engineering, Tokyo Institute ofTechnology, and since 2009 is with The Global Edge Institute ofthe same university. His main research interests include analogintegrated circuits. Dr Nicodimus is a member of the Institute ofElectrical and Electronics Engineers.

Shigetaka Takagi (Member) was born in Tokyo. He received theB.E., M.E., and Doctor of Engineering degreesfrom the Tokyo Institute of Technology, in 1981,1983, and 1986, respectively. Then he becamea Research Associate at the Tokyo Institute ofTechnology, where he is now a Professor in theDepartment of Communications and Integrated

Systems. In 1998, he was a Visiting Associate Professor at OsakaUniversity, Japan. His main research interests include analogintegrated circuits. He is the author of Analog MOS ElectronicCircuits, Linear Circuit Theory, and Analog Electronic Circuits,as well as a co-author of Introduction to Digital IntegratedCircuits (in Japanese). Prof. Takagi is a member of the Instituteof Electronics, Information and Communication Engineers andthe Institute of Electrical and Electronics Engineers. He receivedthe Best Paper Awards in 1996 and 2001 from the Institute ofElectronics, Information, and Communication Engineers, Japan.

80 IEEJ Trans 7: 74–80 (2012)