a harvesting circuit for flexible thin film piezoelectric ...fand.kaist.ac.kr/attach/562.pdfflexible...

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2020.3044782, IEEETransactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Abstract— A novel energy harvesting (EH) interface for flexible thin film piezoelectric generator (FPEG) is proposed for EH from irregular human motion. Traditional thick PEG-based kinetic EH circuits are designed for continuous and sinusoidal inputs from cantilever-based structures and are not suitable for EH from irregular human motion. The proposed EH interface circuit significantly enhances energy extraction with a load screening scheme, which minimizes load capacitance to maximize PEG output voltage up to 102 V while using standard voltage 0.18-μm process. An energy-aware wake-up controller is designed to (monitor and) detect the FPEG deformation to assure that the harvesting interface is only activated when enough energy is available for EH. When the FPEG voltage peaks, energy is transferred to the battery through an inductor with single-cycle buck-converter-like operation, allowing input voltage and frequency-independent EH operation. The measurement results show the proposed EH interface successfully harvests energy from irregular pulsed inputs with 562% improvement compared with a full bridge rectifier.

Index Terms—Energy harvester, harvesting interface, thin film piezoelectric generator, load screening.

I. INTRODUCTION

ITH ever-increasing interest in wearable electronics, many wearable applications such as smart watches,

smart jackets, and wearable medical diagnostics sensors have been introduced recently. Since the wearability of these devices limits the volume and weight of the electronics, their battery capacity is limited. Therefore, frequent recharging or replacing of batteries may be required, degrading user experiences. Ambient energy harvesting (EH) [1]–[5] is an attractive option for such wearable electronics because it could decrease the battery recharging or replacement frequency or potentially eliminate the need for battery replacement altogether by achieving energy autonomy. Due to the characteristics of wearable electronics and high power-density of the generator,

This work was supported by Basic Research Lab Program through

the National Research Foundation of Korea (NRF) (2020R1A4A2002806) and MOTIE (No. N0001883). The EDA tool supported by IDEC, Korea.

M.B. Khan and Yoonmyung Lee are with the Sungkyunkwan University, South Korea. ([email protected])

D.H. Kim, J.H. Han, D.J. Joe, K.J. Lee are with KAIST, South Korea. D.J. Joe is with KRISS, South Korea. H. Lee, Y. Lee, and E. Jang are with Samsung Electronics, South

Korea. M. Kim is with LG Electronics, South Korea. H. Saif is with NUCES, Islamabad, Pakistan.

kinetic EH using a piezoelectric generator (PEG) [6]–[8] is an attractive solution for powering wearable electronics.

The most common form of PEG-based kinetic energy harvesting sources is the cantilever-based PEG [9], illustrated in Fig. 1(a). As an external force is applied on the free end, the electromechanical resonance of the mass and piezoelectric material generates periodic sinusoidal output voltage, converting kinetic energy to electric energy. Recently, a new type of PEG, a flexible thin film piezoelectric generator (FPEG) [10] as shown in Fig. 1(b), was introduced, which could be potentially attached to clothing or skin to harvest energy from joint or limb motion, thanks to its reduced thickness (170 μm) and flexibility. Unlike the traditional rigid and thick piezoelectric materials, which are hard to attach to and bend with the human body, the FPEG can be made in a body-friendly patch-like form. When attached to clothing, these patches can be bent during human action that involves joint bending or limb motion, allowing energy to be harvested from human motion. However, due to irregular human motion, flexible PEG generates an irregular pattern of energy with aperiodic pulses and varying magnitudes. Therefore, to harvest energy from a FPEG, a harvesting interface circuit that can handle irregular pulse inputs is required. Although some prior works have attempted to harvest energy generated by applying non-sinusoidal input to the FPEG [11], [12], they only used simple circuits with discrete components to evaluate harvesting performance and did not present an integrated circuit design optimized for such conditions.

To efficiently transfer PEG-generated energy to the storage (battery/capacitor), various EH interface circuit schemes have been adapted by the circuit research community. Some of the

A Harvesting Circuit for Flexible Thin Film Piezoelectric Generator Achieving 562% Energy

Extraction Improvement with Load Screening Muhammad Bilawal Khan, Dong Hyun Kim, Jae Hyun Han, Hassan Saif, Hyeonji Lee, Yongmin Lee, Minsun

Kim, Eunsang Jang, Daniel Juhyung Joe, Keon Jae Lee, and Yoonmyung Lee, Senior Member, IEEE

W

Fig. 1. (a) Cantilever-based piezoelectric generator. (b) Flexible thin film piezoelectric generator (FPEG). (c) PEG electrical model. (d) Output waveform characteristics of conventional cantilever-based harvesting system. (e) Output waveform characteristics of FPEG-based harvesting system.

Authorized licensed use limited to: Korea Advanced Inst of Science & Tech - KAIST. Downloaded on January 05,2021 at 11:56:11 UTC from IEEE Xplore. Restrictions apply.




most popular and widely adapted integrated circuit (IC)-based PEG EH schemes include synchronous electric charge extraction (SECE) [13]–[15], energy investing [16], and synchronous switch harvesting on inductor (SSHI) [17]–[21]. The PEG damping strength can be increased by increasing its voltage [16]. SSHI-based harvesting circuits utilize an inductor to flip the PEG voltage at the end of every half-cycle of sinusoidal input. However, these harvesting circuits utilize large buffer capacitors, which limit the PEG generated voltage and hence decrease the PEG’s electrical damping force [16], resulting in lower energy extraction. SECE utilizes an inductor to transfer PEG-generated energy at the peak of the PEG-generated voltage. A bulky fly-back transformer is utilized in [13] to down convert high voltage (100 V). For example, the harvesting circuits in [14], [15], [22] were designed for limited input voltage (15 nF, which is much higher than that of FPEGs and allows the use of a buffer load capacitor for temporary charge storage. However, with FPEGs, using a large buffer capacitor significantly degrades energy extraction due to the unique characteristics (discussed later) of FPEGs. Therefore, the capacitive loading seen by a FPEG should be minimized to maximize energy extraction under the same mechanical input conditions.

In this paper, an EH interface circuit optimized for FPEGs is proposed to scavenge energy from irregular human motions. By avoiding the use of a buffer capacitor and minimizing the load capacitance by hiding most of the parasitic capacitive load during energy extraction, an improvement of up to 562% in energy extraction is observed compared with full bridge rectifier (FBR)-based harvesting circuits. For such improvement, the FPEG output voltage is increased to 102 V, and the harvesting interface circuit is carefully designed to handle such high voltage with standard voltage process and a few discrete components while keeping standby current very low (0.38 nA) to efficiently manage sporadic energy inputs.

The rest of this paper is organized as follows. In Section II, the characteristics of piezoelectric materials and the principles of conventional PEG EH interfaces are explained, and the key approach of the proposed harvesting interface is described. In Section III, top level and detailed sub-circuit implementation of the proposed harvesting interface are presented. The test setup and measurement results are demonstrated in Section IV. Section V concludes the paper.

II. PEG CHARACTERISTICS AND HARVESTING INTERFACE DESIGN APPROACHES

A PEG can be represented as an electrical model as shown in Fig. 1(c) [24], where a current source is placed in parallel with an internal capacitor (CP) and an internal resistor (RP). Our analysis will be based on this electrical PEG model.

A. Cantilever-based PEG versus Flexible Thin-Film PEG

With a cantilever-based PEG [25], [26], periodic energy output is expected due to the electromechanical resonance of the cantilever structure, as shown in Fig. 1(d). Peak voltages VA and VB are expected to be the same or slowly decay with damping, and the overall waveform will be continuous sinusoidal. To optimize the EH process and maximize energy extraction, the impedance at the resonance frequency should be matched with EH circuits. Another variation of continuous excitations are shock excitations (Fig. 1(d)) [15], [18], [20], which are basically decaying sinusoidal excitations.

Meanwhile, for a FPEG, the energy output is no longer continuous sinusoidal since it generates energy from random human motion rather than from mechanical resonance. Therefore, the output will be aperiodic with random peak voltages with random polarity, as shown in Fig. 1(e). In this waveform, peak voltages VP1 and VP2 (with random time interval Td2) are determined by the intensity of the motion, and the polarity is determined by the direction of the motion. Due to the nature of human motion, the output will be aperiodic and sporadic. Therefore, impedance matching is not applicable, and a new harvesting circuit with a proper optimization strategy is required in order to utilize the FPEG.

B. Capacitive Loading and Energy Extraction

One of the key principles is that, for a given amount of deformation on piezoelectric material, the amount of extractable energy changes with the capacitive load seen by the PEG during the deformation process. The amount of charge (Q) generated by the current source (Ip in Fig. 1(c)) is determined by the amount of deformation on the PEG [27]. Therefore, for a given PEG bending displacement, the amount of generated energy can be represented as

E =1

2CV� =

1

2

Q�

C (1)

where V is the final voltage at the load capacitor after deformation, and C is the total load capacitance (C = CLoad + CP, where CLoad is the explicit load capacitance). This implies that for a given Δd and corresponding Q, the extracted energy can be maximized by minimizing the load capacitance seen by the PEG [28] (a conclusion supported by our measurement results shown later in Fig. 2). This is because with a lower load capacitance, the output voltage increases faster as charges are accumulated, and more energy is required for the PEG to dump more charge at the capacitor when it is already at high voltage.

For conventional PEGs, the internal capacitance CP is

relatively high, typically >15 nF (for 2.540.381 cm2 rectangle

[14], [16], [20], 42.08 cm2 rectangle [15], 300 mm2 disk [21], [23]), which is much higher than that of thin film PEGs (~500 pF for 3×3 cm2 patch). Therefore, the parasitic capacitances





(CPAR) of devices in a EH circuit, which are on the order of hundreds of pF, do not degrade energy extraction much. However, with 170µm thick FPEG, whose CP is only ~50 pF/cm2, (~500 pF for our sample), adding a few hundreds of pF CPAR can significantly degrade energy extraction since it significantly increases (several fold) the load capacitance seen by the FPEG. This trend is confirmed with the generated energy measurement results shown in Fig. 2, obtained for a single bending operation of the FPEG with varied CLoad.

For evaluating conventional cantilever-based EH systems, a shaker with varying frequency and acceleration is utilized to generate continuous/shock sinusoidal excitations. However, such a test setup is not suitable for evaluating an EH interface with FPEG since 1) it does not allow precise control of the amount of deformation (or displacement ∆d) and 2) it only allows continuous vibration. To properly evaluate an EH interface for FPEG with random excitation and controlled deformation, a test setup with a bending machine is utilized, as shown in Fig. 2(a), to mimic sporadic human motion with varying ∆d.

The measured values in Fig. 2(b) and (c) are obtained by directly connecting the load capacitance to the FPEG without an EH interface to compare the energy extraction of the PFEG with varying capacitance. The peak voltage and energy (bending) values are recorded at the end of the deformation. Similarly, the PEG is released to return back to its original position, which generates voltage with the opposite polarity. The releasing peak voltage and energy values are recorded at the end of the releasing operation. For these measurements, an explicit load capacitor (CLoad) was connected to the FPEG (making the total capacitance seen by PEG as C=CP+CLoad) as shown in the inset circuit diagram in Fig. 2(b), and the bending displacement was kept identical. As the bending force is applied to the FPEG, its output voltage increases to reach the peak voltage VPK. This peak voltage and generated energy values are plotted as functions of CLoad. Fig. 2(b) shows that the generated energy decreases as the explicit load capacitance is increased. This is because assuming a fixed Q with fixed Δd, the peak voltage generated by the PEG is also decreased with a larger CLoad as shown in Fig. 2(c). Therefore, for maximum

energy extraction with a given motion, explicit CLoad should be removed, and CPAR seen by the PEG should be minimized.

C. Conventional Harvesting Interface Designs

The EH scheme shown in Fig. 3(a) is a basic FBR-based harvesting scheme. In this scheme, an FBR is used to transfer energy from the PEG to a buffer capacitor (CBUF), which only conducts once VP exceeds VBUF. When continuous energy input is provided by the PEG, CBUF acts as a temporary charge storage and maintains VBUF at a certain level, and a harvesting circuit similar to a DC-DC converter can be used. However, limiting PEG voltage to a certain level decreases its electrical damping force [16], [28] and hence energy extraction. Moreover, for an FPEG, the large CBUF significantly degrades energy extraction (as explained earlier), and hence this structure cannot be used for EH with an FPEG. In addition, due to bias-flipping at every half-cycle of sinusoidal pulse, SSHI becomes unsuitable for irregular pulse/shock inputs, as demonstrated in [15].

SECE-based integrated EH interfaces, shown in Fig. 3(b), represent one of the most popular schemes for PEG EH [14], [15]. PEG voltage is increased to its peak before transferring energy to the inductor, which later drains this energy to storage. Although these IC-based interfaces aim to increase the PEG damping force, they only restrict the input voltage to




(buck-boost-like) SECE-based FPEG EH circuit. For maximum energy extraction, the buffer/load capacitance (such as CBUF in Fig. 3(c)) is removed, and the harvesting operation is conducted only with parasitic capacitances. An FBR is still required to rectify the PEG output voltage to VRECT, but to minimize the impact of the increased load capacitances, an FBR with the minimum possible parasitic capacitances (13 pF per diode) was chosen. The load-screening transistor S1 is introduced to enhance the energy extraction of the FPEG. [29] uses similar transistor for an EH circuit with 100 V due to load screening, whereas the battery voltage available for controlling switches (S1~S4) is in the 3-4 V range. In addition, PEG activity detection for waking up the peak-detecting circuit to activate the harvesting operation should be performed with regard to such high (>100 V) output voltage. In the following section, the implementation details for addressing these challenges are discussed in detail.

III. HARVESTING INTERFACE IMPLEMENTATION

Fig. 4 shows the block diagram of the implemented proposed FPEG EH interface and its conceptual operation waveforms. When the FPEG undergoes mechanical deformation, the proposed EH interface accumulates as much VP as possible, thanks to the load screening, and maximizes energy extraction. As VP increases, the always-on energy-aware wake-up controller (EA-WUC) monitors the level of rectified voltage, VRECT, and activates the rest of the harvester system when the minimum activation voltage is reached. Then the peak

detector (PD) is activated to detect the end of the bending operation by detecting the peak of VRECT (VPK). Once VRECT peaks, the pull-down driver (PDD) activates the level shifter (LS), which consists of two discrete resistors (R1, R2) and a pulldown NMOS (MN1). With a tunable pulse applied to the gate of MN1 (VLS), the voltage at the gate of MP1 (VG) is pulled down to turn on MP1, and energy is transferred to the inductor (L1) by turning on MN2 at the same time. As MP1 is turned on, the inductor voltage (VL1) increases instantly and then gradually decreases to zero as the inductor current (IL1) reaches its peak (IPK). The zero-crossing detector (ZCD) detects IPK and turns off MP1/MN2. Subsequently, MP2/MN3 are turned on, transferring energy to the battery. The reverse current detector (RCD) prevents the current from flowing back from the battery to the L1. To handle high VPK (>100 V) with standard voltage process, each block with a high voltage node is carefully designed to operate with discrete components.

Despite the fact that we utilized discrete power transistors, the CPARs of the discrete components are small enough. Since the PEG is self-loaded with ~500 pF CP, further reducing the CPAR (~100 pF) of the discrete components would not boost the energy extraction much. Moreover, power consumption could be minimized by 1) triggering EH operation based on motion events or 2) minimizing EH operation energy overhead by utilizing energy provided by the PEG for EA-WUC and other blocks. This allows efficient operation and EH even from very weak inputs. The implementation details of the sub-blocks are described in the following sub-sections.

A. Energy-Aware Wake-up Controller (EA-WUC)

A monitoring circuit is required to detect when the PEG is deformed and energy is available for harvesting. Therefore, an EA-WUC circuit was designed to assure that the EH interface is only activated when enough energy is available and stays in standby mode most of the time to minimize idle power consumption. Fig. 5(a) shows the circuit details of the EA-WUC. The supply generation block generates PEG-induced supply voltages (VSUP1, VSUP2) for other circuits by coupling VRECT through a high-voltage-rated discrete capacitor C3. VRECT and the EA-WUC voltages/signals are shown in Fig. 5(b). The voltage levels of VSUP1 and VSUP2 are regulated to ~2 V and ~1.5 V, respectively, with integrated diode stacks (D7~D10). When sufficient supply voltage is developed, the gate trigger signal VTRIG1 is pulled up by VRECT

Fig. 4. (a) Top level circuit diagram of proposed harvester. (b) Conceptual waveform.





through C1 only if VRECT is higher than 6 times the diode voltage (VD), and PEG-induced supply voltages VSUP1, VSUP2 are generated. Zoomed waveforms of Fig. 5(b) at the point where VTRIG1 triggers are shown in Fig. 5(c). VTRIG1 triggers the inverter chain that generates VTRIG2 at the voltage level of VSUP2, which then instantly pulls down VTRIG3 to ground through a level shifter in the trigger controller block, which is powered by the battery. The trigger controller initiates an evaluation trigger signal (Ø1).

However, if VRECT is not high enough due to weak motion, VSUP2 and hence VTRIG2 do not go high enough to instantly pull down VTRIG3. This can result in short circuit current on MX for a long duration. Therefore, VTRIG2 needs to be reset within a reasonable window of time. When VTRIG2 is triggered but not high enough to pull down VTRIG3, VDEL is triggered after a fixed inverter chain delay, which triggers ØRST1, resetting all internal nodes, including VTRIG2, for the next operation.

If Ø1 is triggered with high enough VRECT, the evaluation circuit compares the divided VRECT (VDIV) with an externally adjustable reference voltage (VREF1). The clocked comparator activates the harvesting phase (Ø2) only if VDIV>VREF1, preventing EH interface activation with weak energy input to save energy. If Ø2 is not triggered, TERM signal is asserted to terminate the evaluation phase and to activate ØRST2 to reset the EA-WUC. With this scheme, our simulation analysis shows that the EA-WUC consumes only ~1 nJ of energy from the PEG and a few pJ of energy from the battery since the battery-powered circuits (evaluation circuit and trigger controller in Fig. 5(a)) are triggered only for a very short duration.

Once Ø2 is activated (TERM not activated), the PD and other blocks are activated for EH operation. In this case, the EA-WUC needs to be de-activated to minimize power consumption until the end of the EH operation. Therefore, the internal circuits of the EA-WUC are kept reset (by Ø1 and Ø2) until the end of the EH operation. Ø1 and Ø2 are de-asserted at the end of each EH event to put the EA-WUC in standby mode

to detect the next motion. The trigger and reset operations of the EA-WUC internal signals are summarized in Fig. 5(d). The trigger condition (VRECT>6VD & VDIV> VREF1) was determined with simulations to ensure that EH is only activated when energy is greater than control loss.

All blocks in the EA-WUC except the trigger controller and evaluation circuits are powered by the PEG-induced supplies, VSUP1 and VSUP2, resulting in minimal power consumption from the battery. Thanks to the EA-WUC designed with I/O transistors, which also have high threshold voltage and low leakage, all other blocks, including the PD, PDD, ZCD, and RCD, are power-gated during standby, achieving 0.38 nA standby current. Process variation simulations were carried out to make sure that no node voltage within the integrated circuit exceeds 4 V as the VRECT exceeds >200 V. In addition, simulations were performed for different input pulse durations ranging from micro-seconds to hundreds of milli-seconds to model various input conditions the FPEG can experience. Even with long input pulses, the energy loss in the EA-WUC was kept on the order of pJ.

B. Peak Detector (PD)

To harvest the maximum energy, the EH operation should be activated when VP reaches its peak at the end of deformation. Therefore, a PD circuit is required to detect this moment. Due to the load screening, the VPK level can be as high as >100 V; detecting the peak with such high voltage is a non-trivial challenge. As the harvesting phase (Ø2) is activated by the EA-WUC, the PD circuit (Fig. 6(a)) is enabled. To deal with the high PEG output voltage , VRECT is coupled with high-voltage-rated discrete capacitor C1 [14], and only the slope of VRECT is monitored through IPD. When VRECT is increasing, positive IPD flows through N1, developing bias voltage VPDIV. On the other side, a small reference current IREF is generated with a slope tuning circuit, which flows through N2 and develops bias voltage VREF2. When VPDIV is lower than

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Fig. 5. Implementation details of energy-aware wake-up controller (EA-WUC) capable of monitoring high VRECT input (>100 V). (a) EA-WUC circuit.(b) Corresponding waveform. (c) Zoomed waveform at the point where EA-WUC detects PEG input. (d) Trigger and reset operations when VTRIG1 triggered





VREF2, this means that IPD < IREF, and this can be interpreted as the peak condition, and PDOUT is triggered as shown in Fig. 6(b). VBIAS and PBIAS1 are supplied through a tunable reference voltage generator [30], which is activated together with PD for minimized power consumption.

C. PEG-assisted Level Shifter (LS)

When the FPEG generates energy, the load screening transistor MP1 in Fig. 7(a) needs to be kept turned off to maximize energy extraction. Once VPK is detected, the EH operation should be initiated by turning on MP1/MN2. Due to high VP and hence VRECT, the gate node voltage of MP1, VG, needs to be driven as high as VRECT when turned off and pulled down properly to turn it on, which requires a complex driving scheme due to limited VBAT (up to 4 V). The VRECT-assisted LS in Fig. 7 was designed to address this challenge, utilizing high- voltage-rated discrete components (R1, R2, MN1). As the FPEG is deformed, VP (and VRECT) starts to increase. At this point, the control signal VLS is kept low so that VG can follow VRECT with charging current through R1. When VPK is detected, VLS is driven high to activate EH operation as shown in Fig. 7(b) (time t0). By turning on MN1, VBOT becomes ~0 V and current starts to flow through R2. As MN1 is turned on, VG is gradually pulled down due to the gate-source capacitance (CGS) of MP1. As large enough gate-source voltage (VGS) is developed to turn on MP1, drain current through MP1 rapidly increases and energizes L1. Since IL1 quickly becomes much larger than the current flowing through R2, VRECT drops at a faster rate compared to the rate VG was dropping. During this process, CGS of MP1 maintains the VGS difference (VGS=VRECT - VG) as shown in Fig. 7(b). As the VRECT drops, VG drops also since VRECT and VG are coupled with CGS. This means that R1, R2 do not function as a simple voltage divider. Therefore, VGS of MP1 is maintained large enough for continuous conduction until VRECT reaches 0 V, and the IPK is reached at time t1. To minimize the parasitic load seen by PEG and loss due to leakage, discrete MOSFETs (MP1, MN1) with low gate capacitance (102 pF, 45 pF) and low standby leakage current (100 nA @VDS=240 V) were chosen.

D. Zero Crossing Detector (ZCD)

As described earlier, VL1 needs to be monitored to determine when IL1 reaches its peak. A ZCD that can interface high VL1 voltage is designed as shown in Fig. 8 to monitor IL1 and open MN2 when the IL1 peak (IPK) is detected. Connecting the PEG to the inductor at its peak voltage results in a very high voltage at the node VL1. Therefore, the integrated transistors of ZCD cannot be connected directly, and hence VL1 is coupled to capacitively divided voltage VZC through C1, C2. The division ratio is 40:1, assuring the maximum voltage seen by the

integrated transistor is within the acceptable range. VZC is compared to 0 V with some tunability, which denotes the zero-crossing of VL1, indicating the IPK. This ZCD (derived from [31]) is faster than [14] where the compared voltages are fed to the source terminals of amplifying NMOS. Following the IPK detection, energy from the inductor is transferred to the battery by turning on MN3/MP2 (in Fig.4). RCD detects the end of energy transfer (IL=0 A) and activates a pulse for final reset. FRST (shown in Fig. 5(a)) is triggered, which resets all the active blocks and puts the EH interface into standby mode. As the ZCD and RCD are only turned on for a very short time (~10 µs), the energy consumed by these blocks is negligible.

IV. MEASUREMENT RESULTS

The prototype test chip of the proposed EH interface was fabricated in standard voltage 180nm process. A 3cm×3cm

FPEG sample with 170 μm thickness and 2 μm thick Pb(Zr0.52Ti0.48)O3 was used for the measurements; the fabrication details can be found in [28]. This FPEG has a current density of 0.167 μA/cm2. The internal parasitics of the FPEG were CP = ~500 pF and RP = ~6 GΩ. The test setup for the FPEG measurement is shown in Fig. 9(a). The FPEG was mounted on a custom-designed bending machine, mimicking an FPEG patch attached to clothing near a joint [10], as shown in Fig. 2(a). For quantitative analysis, the bending machine is precisely controlled to bend or release the FPEG from or back to its original position repeatedly. The FPEG sample is tested for horizontal bending displacement (Δd) of up to 2.5 mm. The FPEG is confirmed to be durable with such bending condition – no degradation was observed with fatigue test performed by bending it up to 12,000 cycles with bending radius of 2 cm [28]. Such bending radius corresponds to Δd of 2.726 mm and central deflection of 5.3 mm for the sample size of 3 cm × 3 cm used in our test. A LabVIEW interface was developed to control the test chip operation and acquire the measurement

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data from a Keysight B2912A source/measure unit for precise current and voltage measurement. A micrograph of the fabricated test chip is shown in Fig. 9(b). Although a large PCB with various debugging functionalities was designed for testing purposes (shown in Fig.9), for practical wearable applications, a compact system can be designed with approximate dimensions of 15mm×15mm with a 1.6 mm2 integrated circuit, 4 discrete switches, and one inductor.

Fig. 10(a) shows the operation of the proposed EH interface with input current of varying amplitudes and slopes, generated by bending the PEG. The waveform on the left shows that with a low energy input, harvesting is not activated. If the input energy is too low, which can be determined by monitoring the input voltage with the EA-WUC, evaluation trigger signal Ø1 is not activated so that the evaluation circuit in the EA-WUC is not activated (case ① in Fig. 10(a)). If the input is slightly higher, Ø1 can be triggered to activate the evaluation of VRECT. However, if VRECT is not high enough, Ø2 is not triggered so that the EH operation is not activated to prevent energy consumption (case ② in Fig. 10(a)). The measured waveform in Fig. 10(b) shows the harvesting operation when both Ø1 and Ø2 are triggered for sufficiently high input. In this case, as enough VRECT is accumulated, Ø2 is triggered, and VRECT reaches its peak at the end of the FPEG bending operation, where the EH operation is activated by the PD. The operation details at this moment are shown with the zoomed waveform in Fig. 10(c). The harvesting operation is activated by triggering VLS, which turns on MP1 to transfer energy from CP to the L1. As a result, VL1 is instantly driven high and then gradually becomes zero as the PEG is discharged. As VL1 reaches zero, the ZCD detects this point, and energy on the inductor is transferred to the battery by turning off MP1/MN2 and turning on MP2/MN3 (in Fig. 4), which is indicated by VEN driven low. As the battery is charged, VL2 becomes slightly higher than VBAT and remains higher until IL reaches zero. The RCD detects this moment and de-activates the harvesting operation and activates the standby state to wait for the next input.

In this experiment, the bending machine generates a pre-defined form of input pulses. However, in the case of real-life applications, FPEG-generated IP can be random. Hence, the PD will continuously monitor input and detect the peak when the IP approaches zero, where energy is instantly harvested using an inductive circuit, which only takes a few µs. This EH time is very short compared to real-life motion applied to a PEG, which would be on the order of milli-seconds. Therefore, any further PEG-generated input current (in either direction) after a single EH operation will also be dealt with as a separate pulse, and the circuit can expectedly handle that.

The proposed FPEG EH interface’s harvesting operation and its performance are evaluated under a variety of conditions. Firstly, to verify the impact of load capacitance on the PEG energy extraction, the VPK generated by the PEG with different loading conditions as functions of Δd are compared in Fig. 11(a). VPK,OC refers to the peak open-circuit voltage generated by the PEG when no load is attached, whereas VPK,IN refers to the VPK generated when the proposed EH circuit is connected (but not activated). Although the additional CPAR seen by the PEG is minimized by load screening, inevitable voltage drop is still observed as the additional capacitive load of the EH circuit

is seen by the PEG. Therefore, without the load screening scheme, the generated voltage, and hence the energy, would drop significantly further due to the much larger additional load, undermining its feasibility.

The amount of energy that the PEG can generate when there is no additional load attached (EPEG), the amount of energy actually generated when EH circuit is connected (EIN), amount of energy actually harvested with the proposed EH circuit (EHRV), and the amount of energy consumed by the proposed circuit for EH operation (ELOSS) are compared with the amount of energy that would have been harvested with a plain FBR (EFBR) in Fig. 11(b). EHRV can be calculated by measuring and integrating the current flowing into the output battery. Similarly, EFBR can be calculated by measuring and integrating the current flowing into the battery connected at the output of the FBR. ELOSS can be calculated by measuring and integrating the current consumed by the harvester IC during a single

(a)

(b)

Fig.9. (a) Test setup for FPEG harvester measurement. (b) Chip micrograph.

0 300 600 9000

30

3-10

-5

0

5

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15

Time (ms)

1

Fig. 10. Operation waveforms of the proposed harvester with random input pulses. (a) Simulated waveform is shown for long-term operation demonstration. (b) Measured waveform is shown for activated harvesting operation. (c) Measured waveform for energy transfer from FPEG to battery.





harvesting cycle. These energy values are measured for a range of Δd values and for two bending speeds (S), where S is defined as Δd/Δt, and Δt is the duration of the bending operation. To determine EPEG, a 1G Ω load resistor (RL) is connected, and the voltage/current across the RL is measured. A 1 GΩ load is chosen since 1) if RL is too large, a larger portion of EPEG would be consumed by the RP of PEG, which is hard to model precisely; and 2) if the RL is too small, a significant amount of charge would leak away during the bending operation, which would lower the VPK,OC and resulting EPEG. As Δd is increased from 0.75 mm to 2.5 mm, the generated and extracted energy are increased, as expected. Little difference between the measured energy values with S of 1.23 cm/s versus 1.76 cm/s is observed. EHRV is much higher than EFBR, which clearly shows the effectiveness of this load-screening approach. Fig. 11(c) shows how EHRV varies with S and Δd. During the bending operation, charges can leak away through the RP. Therefore, for slow S, more charges leak away since it takes longer to detect the peak, reducing harvestable energy.

Fig. 12(a) shows the maximum output energy improvement rate (MOEIR) for different bending and releasing speeds while keeping VDD (3.3 V) fixed. MOEIR shows how much improvement in energy extraction is achieved when comparing a harvesting circuit to a reference circuit for a given harvesting condition (e.g. bending speed/displacement, vibration frequency). An FBR is conventionally used as a benchmark comparison circuit by PEG EH interfaces [14]–[16], [20]. The MOEIR of the proposed harvesting interface can be calculated as

�� =�� − ��

�� (2)

As ∆d is increased, MOEIR increases for all the bending speeds by up to 496% (S=2.6 cm/s). On average, 268%, 383%, and 465% MOEIR is achieved for bending speeds of 1.23 cm/s, 1.76 cm/s, and 2.6 cm/s, respectively. Fig. 12(b) shows how the harvested energy varies with the battery voltage, i.e. energy storage voltage (VBAT=VDD), with a maximum S of 3.6 cm/s and Δd of 2.5mm. The proposed EH interface circuit was able to operate with a VDD range of 2-3.2 V. EHRV increases as battery voltage increases due to the smaller conduction loss associated with higher gate-source voltage at the power stage transistors. EFBR also increases with the increase in VDD since higher rectified voltage (VRECT=VDD in this case) allows for more energy harvested assuming that the amount of generated charge is proportional to Δd. ELOSS also increases with the higher VDD, but the increased amount is negligible compared to the increase in EHRV. Therefore, the overall improvement remains almost the

same. On average, the proposed EH interface has 514% (bending) and 519% (releasing) improvement compared to EFBR, and the maximum/minimum improvement was 562%/470%.

Table. I. summarizes the performance parameters of the proposed EH interface and compares them with the other state-of-the-art PEG EH interfaces. The proposed EH interface significantly enhanced energy extraction with its load-screening scheme. However, this scheme requires handling of very high voltage, as high as 140 V, unlike previously reported EH interfaces with low voltage inputs (200 V open-circuit input voltage, but the measurements could be performed only up to 102 V due to the bending machine and harvesting source (FPEG) limitations.

Most earlier PEG EH interfaces focused on improving energy extraction with periodic regular inputs [14]–[16], [20]. However, the proposed EH interface exhibited a large energy extraction improvement of 562% compared with an FBR, even with irregular pulse input. A few of the earlier works could handle ‘shock’ input [15], [20], but they still relied on resonance of the cantilever structure for EH operation, prohibiting their application to a single irregular pulse. Although [21] was designed for irregular pulse input from a PEG with 150 nF CP, its switched capacitor-based topology is an unviable solution for FPEG material since the large buffer capacitors (13.2 μF total) would be seen as load for the harvesting source, significantly degrading energy extraction with an FPEG source with 500 pF CP. In the proposed design, no explicit external load or buffer capacitor is utilized to

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EPEG (1.76 cm/s)

EIN (1.76 cm/s)

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ELOSS (1.76 cm/s)

EPEG (1.23 cm/s)

EIN (1.23 cm/s)

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EFBR (1.23 cm/s)

ELOSS (1.23 cm/s) 0.65 1.1 1.6 2.1 2.60.0

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d = 2.50 mm d = 2.25 mm d = 2.00 mm d = 1.75 mm

Fig. 11. (a) PEG-generated peak voltage when PEG output is open (VPK,OC) and harvester circuit is connected as load (VPK,IN) (but not activated). (b) EPEG, EIN, ELOSS, EFBR, EHRV for Δd variation. (c) Harvested energy for different bending speeds.

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Bending 2.60 cm/s Releasing 2.60 cm/s Bending 1.76 cm/s Releasing 1.76 cm/s Bending 1.23 cm/s Releasing 1.23 cm/s

Fig. 12. (a) Maximum output energy improvement (MOEIR) for different bending speeds. (b) Net harvested energy for range of supply voltages.





maximize output voltage and energy extraction. However, 9 discrete capacitors (on the order of 10 pF) were used for interfacing high VP with standard voltage IC. These capacitors do not need to be large, and the total capacitance seen by the PEG (during PEG deformation) is < 20 pF since many of them are stacked, having negligible effect on the energy extraction from the PEG.

Since the proposed EH interface is designed for sporadic energy input from human motion, minimizing the standby power between occasional EH operations is crucial. The EA-WUC allows power gating of all other circuits during standby, significantly lowering the quiescent (i.e. standby) current to 0.38 nA. By powering a large portion of the EA-WUC with power delivered from the PEG and activating EH operation for only a short duration (few μs), the minimum harvesting overhead is lowered to 13 nJ/pulse, which is significantly lower than that of prior art (12 μJ in [21]), potentially allowing EH from much weaker motions. The harvested energy can be stored in a battery or storage capacitor, depending on the applications. By utilizing a reasonably sized FPEG sample, the harvested energy should be sufficient to operate a low-power system, as shown in [21]. Based on the measurements, assuming a reasonably sized FPEG patch, the approximate maximum EHRV with elbow bending and knee bending would be ~8 μJ (10cm×6cm patch) and ~30 μJ (18cm×12cm patch), respectively.

V. CONCLUSION

A new energy harvesting interface circuit for a flexible thin film piezoelectric generator is proposed to enable energy harvesting from irregular human motion. Unlike the conventional kinetic energy harvesting interfaces, which focus on optimized harvesting operation from continuous sinusoidal inputs, the proposed harvesting interface adopts load screening

to maximize energy extraction from irregular pulse inputs. By minimizing the capacitive load seen by the PEG material during its mechanical deformation, the output voltage is increased up to 102 V, and the harvesting circuit is carefully designed to handle such high voltage. Energy extraction is enhanced up to 562% compared with FBR-based harvesting. By utilizing the EA-WUC to power gate most of the harvesting circuits during standby, the quiescent current could be kept as low as 0.38 nA, enabling efficient operation for human motions with long intervals.

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TABLE I. COMPARISON WITH PRIOR-ARTS

This Work [14] JSSC' 12 [15] ISSCC' 18 [16] JSSC' 14 [20] ISSCC' 16 [21] VLSI' 15

Process/ Control Voltage

0.18μm (Standard Voltage)

0.35μm (High Voltage)

40nm (High Voltage)


0.35μm (Standard Voltage)


Die Area (mm2) 0.29×0.65 1×1.25 1.1×0.5 1.8×1.3 1.1×1.5 2×1.2

Harvesting Approach

SECE with Load Screening

SECE SECE Energy

Investing SSHI

Series-Parallel SC

Piezoelectric Material

Flexible Thin-Film PEG (Pb(Zr0.52Ti0.48)O3)

MIDE V22B

MIDE PPA1011

MIDE V22B

MIDE V21B & V22B

PMN_PT on disc

PEG Internal Cap. 500pF 19.5nF 43nF 15nF 26nF, 20nF & 9nF 150nF

Buffer Capacitor -* - - - 200μF 2.2μF×6

Off-chip Inductor 220μH 2.2mH 2.2mH 330μH 3.3mH 470μH

Excitation Type Irregular Pulse Periodic Periodic & Shock Periodic & Aperiodic Periodic & Shock Irregular Pulse

Peak Input Voltage 102V 20V




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Muhammad Bilawal Khan received his B.S. degree in Electrical Engineering from National University of Computer and Emerging Sciences, Islamabad, Pakistan in 2014. He completed his M.S. leading to Ph.D. in Electronic and Electrical Engineering from Sungkyunkwan University, South Korea in 2020. His research interests include energy harvesting system design and low power circuit design.

Dong Hyun Kim received his B.S. degree in Materials Science and Engineering (MSE) from Sungkyunkwan University in 2015 and M.S. degree from KAIST in 2017. He is currently working toward his Ph.D. at KAIST under the supervision of Prof. Keon Jae Lee. His doctoral research interests include energy harvesting system, flexible blood pressure sensors, and biomedical engineering. Jae Hyun Han received his B.S. degree in Materials Science and Engineering (MSE) from Sungkyunkwan University in 2014 and Ph.D. degree from KAIST in 2020. Currently, he works as a staff engineer at Samsung electronics. His research interests include piezoelectric and triboelectric energy harvesting, flexible acoustic sensors, and laser-material interaction.

Hassan Saif received his B.S. degree in Electrical Engineering at University of Engineering and Technology, Lahore, Pakistan in 2012. He received his M.S. leading to Ph.D degree in Electronic and Electrial Engineering from Sungkyunkwan University, South Korea in 2020. He is currently Assistant Professor in the Department of Electrical Engineering at The National University of Computer and Emerging Sciences, FAST Islamabad. His research interests include low power electronics, power

management systems, switch capacitor DC-DC converters and energy harvesting system design.

Hyeonji Lee received her M.S. degree in Semiconductor Display Engineering and B.S. degree in Semiconductor Systems Engineering from Sungkyunkwan University, South Korea. She is currently an image sensor circuit designer in Samsung Electronics, South Korea. Her research interest includes ultra-low power energy harvesting system and CMOS image sensor design.





Minsun Kim received his B.S degree in information and communication engineering from the Hansung University, Seoul, South Korea in 2015. He received the MS degree in Electronic, Electrical and Computer engineering from Sungkyunkwan University, South Korea. He is currently with LG Electronics, South Korea. His research interests include low-power circuit design and security circuit design.

Yongmin Lee received the B.S degree in biomedical engineering from Konyang University, Daejeon, South Korea, in 2016, and his M.S degree in Electronic, Electrical and Computer Engineering from Sungkyunkwan University, Suwon, South Korea, in 2019. He is currently with Samsung Electronics, Suwon, South Korea. His research interests include low power circuit design and digital VLSI design.

Eunsang Jang received his B.S. degree in semiconductor systems engineering from Sungkyunkwan University, South Korea in 2016. He received his M.S. degree in electrical and computer engineering from Sungkyunkwan University, South Korea in 2018. He joined Samsung Electronics, Korea in 2019. His research interest includes low power integrated circuit and power management IC.

Daniel J. Joe is a senior research scientist in the Safety Measurement Institute at Korea Research Institute of Standards and Science (KRISS). Before joining KRISS, he was a postdoctoral research associate in the Department of Materials Science and Engineering (MSE) at KAIST and a staff engineer in the Mobile Communication Division at Samsung Electronics. He received his B.S. degree in electrical engineering at the University of Illinois at Urbana-Champaign (UIUC) in 2008 and his

Ph.D. degree in electrical and computer engineering at Cornell University in 2014. His research interests span sensors, MEMS, flexible electronics, wearable devices, and medical metrology.

Keon Jae Lee received his Ph.D. in Materials Science and Engineering (MSE) at University of Illinois, Urbana Champaign (UIUC). During his Ph.D. at UIUC, he involved in the first co-invention of “Flexible Single-crystalline Inorganic Electronics”, using top-down semiconductors and soft lithographic transfer. Since 2009, he has been a professor in MSE at KAIST. His current research topics are self-powered flexible electronic systems including energy harvesting/storage devices, IoT

sensor, LEDs, large scale integration (LSI), high density memory and laser material interaction for in-vivo biomedical and flexible application.

Yoonmyung Lee received the B.S. degree in electronic and electrical engineering from the Pohang University of Science and Technology, Pohang, South Korea, in 2004, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2008 and 2012, respectively. From 2012 to 2015, he was with the University of Michigan as a Research Faculty. In 2015, he joined Sungkyunkwan University, Suwon, South Korea,

as an Assistant Professor. His current research interests include energy-efficient integrated circuit design for low-power high-performance very large-scale integration systems and millimeter-scale wireless sensor systems.


a harvesting circuit for flexible thin film piezoelectric ...fand.kaist.ac.kr/attach/562.pdfflexible...

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