a highly integrated 65-nm soc process with enhanced … · 2014-12-18 · conclusions •dc...
TRANSCRIPT
A Highly Integrated 65-nm SoCProcess with Enhanced Power/Performance of
Digital and Analog Circuits
L. T. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Bolin g, M. Duane, K. Fujita*, P. Gregory, T. Hoffmann, M. Hori*, D. Kanai*, D. Kidd, S. Lee,
Y. Liu, J. Mitani*, J. Nagayama*, S. Pradhan, P. Ranade, R. Rogenmoser, L. Scudder, L. Shifren, Y. Torii*, M. Wojko, Y. Asada*, T.
Ema*, and S. Thompson
SuVolta, Inc.*Fujitsu Semiconductor Ltd
1
Presentation Outline
• Low-power SoC platform• Process and device results• Circuit results
– SRAM VDDmin reduction– Digital logic power reduction– Analog matching and performance
• Conclusions
2
Low-Power SoC Platform
• Significantly extends 65/55-nm node life with enhanced functionality
• Lower cost alternative to 40-nm migration
ARM M-0 200MHz @ 0.6V
- VDDmin ~400mV- Lower I SB
- 4X Rout- 2x better AVT
Transistor level benefits• Higher drive current• Tighter V T control • Seamless integration to baseline
Product level benefits• VDD reduction from 1.2V to 0.9V
– Nearly half power and matched delay
• Extended voltage range– Improved low voltage yield
3
Presentation Outline
• Low-power SoC platform• Process and device results• Circuit results
– SRAM VDDmin reduction– Digital logic power reduction– Analog matching and performance
• Conclusions
4
Deeply Depleted Channel (DDC)
• Seamless integration into baseline process• Legacy devices supported
– Legacy IP support possible
5
• 65-nm example transistor
DDC Matching Benefits• Improved transistor matching
– Un-doped channel• Better RDF
– Epitaxial channel formed after wells• No well proximity effects
– Excellent V T Control
– No halo implants• Further improves RDF• No halo proximity effects
• Epi layer thickness control– Wafer: 1σ = 0.25%– Overall 1 σ = 0.65%
26.9 27.3Thickness (nm)
6
DDC IEFF Increase
• Better SCE– Thinner t OX
– DIBL reduced ~50mV/V
– Higher low V DDmobility
• IEFF w/ same– LE
– IOFF
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0.6 0.7 0.8 0.9 1.0 1.1 1.20
10
20
30
40
50
60
DD
C I E
FF g
ain
(%)
VDD
(V)
Threshold Voltage Control• Enables better systematic corners
Logic Device SRAM
0.50
0.45
0.40
-0.50 -0.45 -0.40 -0.35
DDC
Control
3σ1σ 2σ
PMOS VT (V)
NM
OS
VT
(V)
0.3 0.7
0.70
0.4 0.5 0.6
0.65
0.60
0.55
0.50
0.45
PMOS VT (V)
NM
OS
VT
(V)
DDC
Control
8
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.60
10
20
30
40
50
σ∆σ∆ σ∆σ∆V
t/20.
5 (m
V)
VT(V)
SRAM Transistor Matching• Better SRAM matching: Lower SRAM V DDmin
• DDC σσσσ∆VT invariant across V T range
~60%
~40%
-0.55 -0.47 -0.39 0.36 0.40 0.440
10
20
30
40
50
σ∆σ∆ σ∆σ∆V
t/20.
5 (m
V)
VT (V)
9
Junction Leakage• Ijunction well controlled, consistent across
VT range
0.30 0.35 0.40 0.45 0.501
10
100
NM
OS
leak
age
(pA
/um
) (L
= 1
µµ µµm)
VT (V)
-0.2 -0.3 -0.4 -0.51
10
100
PM
OS
leak
age
(pA
/um
) (L
= 1
µµ µµm)
VT (V)
10
DDC Enhanced Body Effect
• Highly doped screen layer increases body coefficient by ~4x to ~7x
• Allows significant process corner pull-in
ION
I off
FF
SS
TT
0
50
100
150
200
250
300
PMOSNMOS
Logic
B
ody
fact
or (
mV
/V)
Control DDC
SRAMNMOS PMOS
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Corner Pull-in in Action
NMOS
PMOS
12
Presentation Outline
• Low-power SoC platform• Process and device results• Circuit results
– SRAM VDDmin reduction– Digital logic power reduction– Analog matching and performance
• Conclusions
13
SRAM VDDmin Improvement • No circuit changes from baseline—same masks
– 6-T 9.4Mb arrays– No redundancy
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0.2 0.4 0.6 0.8 1.0 1.2 1.40
102030405060708090
100
-40C RT 125C
% Y
ield
(9.
4 M
b)
VDD
(V)
Circuit Logic Corner Pull-in• Inverter ring oscillator measurements
• Baseline V DD = 1.2V• DDC VDD = 0.9V• SS frequency
400MHz to 150MHz by adjusting BB
• FF frequency 500MHz to 200MHz by adjusting BB
100 200 300 400 500 6000.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
Control DDC SS DDC TT DDC FF
Tot
al p
ower
(m
W)
Frequency (MHz)
SS@Vbb=0V
FF@Vbb=-0.8V
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No Body Effect Stack Penalty• Higher low V DS IEFF
counteracts body bias impact in stacks
• Ring oscillator– NAND (NMOS stack)
NOR (PMOS stack) gates are faster than baseline
• DDC VDD = 0.9V• Control V DD = 1.2V 2 3 4
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Rel
ativ
e R
O F
requ
ency
(nor
mal
ized
to in
vert
er)
Number of Inputs
NAND DDC NOR DDC NAND Control NOR Control
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0 200 400 6000.0
0.1
0.2
0.3
0.4
0.5
0.6
Tot
al p
ower
(m
W)
Frequency (MHz)
Logic Power Reduction with DDC• Inverter ring oscillator
• Sweep VDD and reverse body bias
• 38% greater performance at same total power
• 47% less power at same performance
38%
47%
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Logic Power Reduction with DDC• Large logic/SRAM embedded block
• 5.8M gates• 1.45Mb SRAM
• Same mask set
• 47% less power at same performance– Control V DD = 1.2V– DDC VDD = 0.9V
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0.0
0.2
0.4
0.6
0.8
1.0
DDC with Vbb V
DD = 0.9V
Nor
mal
ized
Pow
er d
issi
patio
n Dynamic Static
ControlV
DD = 1.2V
ARM M-0 Core Results• Preliminary results
– DDC implementation achieves 200 MHz @ V DD = 0.6V• Body bias selection not optimized
19
Presentation Outline
• Low-power SoC platform• Process and device results• Circuit results
– SRAM VDDmin reduction– Digital logic power reduction– Analog matching and performance
• Conclusions
20
DDC Analog Benefits
• Higher I EFF
• Reduced V Dsat
• Higher R DS
• Improved matching
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0.0 0.2 0.4 0.6 0.8 1.0 1.20.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0 DDC Control
NM
OS
I DS (
mA
)
VDS
(V)
DDC Analog Circuit Improvement• Matching improved by
– Local: 40% NMOS, 30% PMOS– Global: 40% NMOS, 30% PMOS
• Current mirrors – 16x current gain
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DDC Analog Circuit Improvement• Differential Amplifier
DC measurements
– DDC VDD = 1.2V and Control V DD = 0.9V
-20 -10 0 10 200.0
0.2
0.4
0.6
0.8
1.0
1.2
Out
put v
olta
ge (
V)
Input offset (mV)
Control DDC
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DDC Analog Circuit Improvement
• OTA DC measurements
• Gain improved 12dB
– More consistent gain– Same layout
• Better matchingallows smalleranalog circuits– Reduced loading– Better slew rate
24
Presentation Outline
• Low-power SoC platform• Process and device results• Circuit results
– SRAM VDDmin reduction– Digital logic power reduction– Analog matching and performance
• Conclusions
25
Conclusions• DDC 65/55-nm SOC process
– Nominal V DD scaled to 0.9V from 1.2V—up to 47% power savings– Proven on large logic/memory blocks– ARM M-0 core operates at 200 MHz at V DD = 0.6V
• 6-T SRAM VDDmin below 400mV demonstrated on 9.4Mb arrays– Un-doped channel mitigates RDF– No halo, well proximity effects
• Enhanced body effect– Allows effective logic corner pull-in with body biasing
• Improved analog circuit matching and gain• Processing compatible with multi-V T and legacy devices
– Straightforward support for existing IP
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Thank You for Your Attention• Questions?
27