a i ex presentation

7/23/2019 A i Ex Presentation

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AIE ProcessorConcept


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Sequential Processor Stages

Decode

FetchExecu

teMem WB


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Pipelining Processor Stages

Decode

FetchExecu

teMem

PipElin

e

WB

PipElin

e

P

ipElin

e

Pi

pEline


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Transaction Table

Five Stages Pipeline


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Pipelining Design

As Queue Problems:

High Circuit Compleit!

I" Queue is Full in a stage the previous musthalt until the queue release item# so there isno great bene$t%

Implementation Shi"t &egister Circuit ' &egisters ()aste

C!cles*

Counter ' &egisters (Save C!cles*


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Shi"t &egister Circuit ' &egisters


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Counter ' &egisters Pipeline


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Pipeline +ptimal Designs

S!nc Pipeline All Pipeline ,o-ules Attache- .ith Same

C!cle Controller

C!cle Time / ,a Stage Cloc0

ProblemsThere is )aste in Cloc0 but not to much

Ever! stage not a.are o" the status o"previous stage%


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A S!nc Pipeline Ever! Stage a.are o" the status o" the previous

stage using internal han-sha0ing signals &ea-! 1 Ac0no.le-ge Signals

A-vantagesThere is no cloc0 .aste than0s to han-sha0ing signals

There is no ,a C!cle Cloc0# ever! instruction ta0ethe cloc0s nee- to per"orm it2s operation%

Disa-vantages In Control 3nit !ou must speci"! ever! instruction

timing in ever! stage o" the pipeline- processor


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S!nc Pipeline ' A S!nc Pipeline


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S!nc Pipeline Implementation


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4e! Feature o" AIE Processor

567bit Pipeline- Processor

Processor Support 89 Instruction

Processor Inter"ace .ith Interleave-,emor!

Inter"ace .ith CD Terminal using

Instructions Processor have it2s Assembl!

Interpreter


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Instructions


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Ir register

I& &egister9 bit

I;ST&3CI+;S&+,

A--ress >>


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ROM CONTROLS

78c>66>>>=57&P;T reg76c>66>>>=87ST+)E a--ress#reg78c=>6>>>

=?7ST+)+ a--ress#reg78c=86>>>=@7ST+D) a--ress#reg78c5>6>>>=7+D)E reg#a--ress78c=B?>>>

=97+D)+ reg#a--ress78c=-?>>>=B7+DD) reg#a--ress78c5B?>>>=a7 a--ress79c8>>>>>

=b7E a--ress79c9>>>>>=c7 a--ress79cc>>>>>=-7C a--ress79->>>>>>

=e7; a--ress79c8>>9>>

7 #79c>>?>>>>67ADD -%reg#s=%reg#s6%reg76>>>>>>>57ADC -%reg#s=%reg#s6%reg766>>>>>

>87S3< -%reg#s=%reg#s6%reg768>>>>>>?7S3) -%reg#s=%reg#s6%reg76@>>>>>>@7,3 -%reg#s=%reg#s6%reg769>>>>>

>7DI -%reg#s=%reg#s6%reg76a>>>>>>97T&SA -%reg#s=%reg76c>>>>>>B7T&S< -%reg#s6%reg76e>>>>>>a7A;D -%reg#s=%reg#s6%reg75>>>>>>>b7+& -%reg#s=%reg#s6%reg756>>>>>>c7;A;D -%reg#s=%reg#s6%reg

758>>>>>>-7;+& -%reg#s=%reg#s6%reg


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Main Modes

I,,EDIATE ,+DE

&EISTE& # &EISTE& ,+DE

,E,+&G ,+DE


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I,,EDIATE ,+DE

&+,7 a--ress

9bit

&E7a--ress

? bit5bit

I,,EDIATE

=@ bit

IR Register :

Instructions :

,+ reg#imme-iate

79c>>?>>> a--ress79c8>>>>>E a--ress79c9>>>>> a--ress

79cc>>>>>C a--ress

;E a--ress

79c9>>9>>; a--ress79cc>>9>>;C a--ress79->>>9>>,P a--ress

79-8>>>>>


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&EISTE& &EISTE& ,+DE

IR Register :

&+,7 a--ress

9bit

Source&E6

? bit5bit

Source&E=

? bit5bit

Destination&

E

? bit5bit

Instructions :ADD -%reg#s=%reg#s6%reg

76>>>>>>ADC -%reg#s=%reg#s6%reg766>>>>>S3< -%reg#s=%reg#s6%reg768>>>>>S3) -%reg#s=%reg#s6%reg

76@>>>>>,3 -%reg#s=%reg#s6%reg

A;D -%reg#s=%reg#s6%reg

75>>>>>>+& -%reg#s=%reg#s6%reg756>>>>>;A;D -%reg#s=%reg#s6%reg758>>>>>;+& -%reg#s=%reg#s6%reg

75@>>>>>+& -%reg#s=%reg#s6%reg


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In-irect a--ressing ,+DE

IR Register :

9bit ? bit5bit? bit

Instructions :

IDST+)E a--ress 76c=>6>>>IDST+)+ a--ress 76c=86>>>IDST+D) a--ress 7

6c5>6>>>ID+D)E a--ress 7

&+,7 a--ress

9bit

Source&E6

? bit5bit

Source&E=

? bit5bit

Destination&E

? bit5bit


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,E,+&G ,+DE

IR Register :

&+,7 a--ress

9bit

I,,EDIATE

=@ bit

&E7a--ress

5bit ? bit

Instructions :

ST+)E a--ress#reg

78c=>6>>>ST+)+ a--ress#reg78c=86>>>ST+D) a--ress#reg78c5>6>>>+D)E reg#a--ress

78c=B?>>>+D)+ reg#a--ress

+DD) reg#a--ress78c5B?>>>

IP;T imme-iate78c>66>>>P3SH)E reg78c=>68>>P3SH)+ reg78c=868>>

P3SHD) reg78c5>68>>


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INSTR!TI"N set


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Tracing Some

Instructions


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,IPS Architecture base-


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For Eample

Eecuting These T.o InstructionSequentiall!

I=:&=/&6&5

I6:&8/&6 A;D &=


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I#: Fetching

I6: Still in ,emor!

l=


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I#: Decoding $ RegFetchR% R&

l6 l=


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I#: Execute 'R%( R&)

l6 l=


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I#: MEM*no "peration+ 'R%( R&)

l6l=


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I#: Write Bac, R#-'R%( R&)

Data Stored InR#

l6

l=


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Solution

I=:&=/&6&5

;+P

;+P ;+P

I6:&8/&6 A;D &=


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I#: Fetching

I6: Still in ,emor!

l=


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I#: Decoding $ RegFetch R%

R&

=;+P


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I#: Execute 'R%

( R&)

;+P

=

;+P


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I#: MEM*no "peration+ 'R%

( R&)

;+P =

;+P

;+P


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I#: Write Bac, R#-'R%

( R&)

Data Store- I

=

;+P

;+P

;+P

6


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I#: Terminated

I6: Deco-ing ' &egFetch &6

6

;+P

;+P

;+P


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I#: Terminated

I6:Eecute K&6

6

;+P

;+P


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I#: Terminated

I6:,E,(;o +peration* K&6 A;D

6

;+P


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I#: Terminated

I6: Terminate-


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Statistics ' Comparisons


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!isc .s Risc

!isc:

7&icher instruction set but ver! comple circuit%

7Instructions generall! ta0e more than = cloc0 to

eecute%

7Instructions o" a variable sie%

Risc:

7Instructions eecute in one cloc0 c!cle%

73ni"orme- length instructions an- $e- instruction

"ormat%

7Simple instructions an- circuit%


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Speed:

With Pipelining:

Each stage takes 4 clock cycles

5 stages IF,ID,EX,MEM,WB

If clock rate 5 MHz then tie for !erforing aninstr"ction !er !i!eline stage is #$% &sec$

Without Pipelining:

If clock rate 5 MHz then tie for !erforing an

instr"ction is 4 &sec$


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,+ r=#>?h,+ r6#>8hADD r5#r=#r6ST+D) r5#=658h

Pipelining

I"

ID

;+P ;+P

I"

I" ID

ID E ,E,

I" ID E ,E,

)

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