a low-impedance open-bitline array for multigigabit dram...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 4, APRIL 2002 487

A Low-Impedance Open-Bitline Array forMultigigabit DRAM

Tomonori Sekiguchi, Member, IEEE, Kiyoo Itoh, Fellow, IEEE, Tsugio Takahashi, Associate Member, IEEE,Masahiro Sugaya, Hiroki Fujisawa, Member, IEEE, Masayuki Nakamura, Member, IEEE, Kazuhiko Kajigaya, and

Katsutaka Kimura, Member, IEEE

Abstract—The noise-generating mechanisms inherent in theopen-bitline DRAM array using the 6 2 ( : feature size) memorycells and techniques for reducing the noise are described. Thesources of differential noise coupled to the paired bitlines laid outin two arrays are the p-well, cell plate, and the group of nonse-lected wordlines. It was found, by simulation and by experimentwith a 0.13- m 256-Mb test chip, that the level of noise is dramat-ically reduced by using a low-impedance array with careful layoutfeaturing low-resistivity materials, tight bridging between pairs ofadjacent arrays, and a small array, achieving a comparable levelof noise to that seen in the twisted and folded-bitline array. Onbasis of these results, it turns out that the open-bitline array has astrong chance of revival in the multigigabit generation, as long asthese noise reduction techniques are applied.

Index Terms—DRAM, memory cell layout, noise analysis, noisereduction, open-bitline array.

I. INTRODUCTION

I N THE development of the multigigabit DRAM [1], [2], re-ducing memory-cell size and thus chip size is a prime con-

cern in terms of cost effectiveness and compatibility of pack-aging with the chips of the previous generation. The folded-bit-line memory cell has been the sole type of cell for the last 20years because of its noise-canceling capability [3]. With the helpof a self-aligned contact process, this type of cell has reachedits minimum size of ( : feature size) [4]. The greater diffi-culty of device miniaturization and the increasing cost of fabri-cation in the 0.1-m era lead, however, to a requirement for newmemory cells which are smaller than . A trench-ca-pacitor folded-bitline cell has recently been proposed [5]. How-ever, it requires a vertical transistor along with an additionaltight-pitch layer for its vertically folded bitline arrangement.Another candidate is the open-bitline cell, because of its small( ) and simple structure. This will only be practical if its in-herently large levels of noise [3], [6] are reduced to an accept-able level. The resulting noise-reduction techniques would alsoprovide the key to making the cross-point cell of the future withits ideal size, since the open-bitline array will be an indis-pensable part of the architecture for such cells.

Manuscript received October 16, 2001; revised January 11, 2002.T. Sekiguchi, K. Itoh, and K. Kimura are with the Central Research Labora-

tory, Hitachi, Ltd., Tokyo 185-8601, Japan (e-mail: [email protected]).T. Takahashi, H. Fujisawa, M. Nakamura, and K. Kajigaya are with ELPIDA

Memory, Inc., Kanagawa 229-1197, Japan.M. Sugaya is with the Semiconductor and Integrated Circuits Division, Hi-

tachi, Ltd., Tokyo 185-8601, Japan.Publisher Item Identifier S 0018-9200(02)02566-0.

(a) (b)

Fig. 1. 6F open-BL memory cell. (a) Top view. (b) Cross-sectional view.

This paper begins with a description of how noise is gener-ated in the open-bitline array, using today’s scaled memory-cellstructure as our example. Then, noise-reduction techniques forthe open-bitline array are proposed and the effectiveness of thesetechniques is evaluated by simulation. These techniques includereducing the array impedance, bridging between two adjacent ar-rays, and reducing the array’s size. Next, noise simulation resultsare compared with experimental results for a 0.13-m 256-Mbtestchip[7], [8].Finally, thenoise intheopen-bitlinearray iscom-pared with that in the folded-bitline array.

II. GENERAL DESCRIPTION OFNOISE GENERATION AND

REDUCTION

A. Noise-Generating Mechanisms

Open-bitline cells with stacked capacitors are shown in Fig. 1.The cell size is at the wordline (WL) pitch of and the bit-line (BL)pitchof .Thecellplate (PL)on thestoragenode(SN)overlays the entire array, and the p-well (PW) and deep n-well(NW) on the p-substrate (SUB) are common to all memory cellsof the array. The tilted active area allows a wider transfer gateand smaller BL contacts (BCT). The storage capacitanceis25 fF. The capacitances related to the BL are the BL–WL capaci-tance , BL-storage node (SN) capacitance , BL–p-well(PW) capacitance , and BL–BL capacitance . Table Igives, forcomparison, thevaluesassimulatedbyusinga three-di-mensional (3-D) capacitance-extraction tool along with values

0018-9200/02$17.00 © 2002 IEEE

488 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 4, APRIL 2002

Fig. 2. Open-BL cell array with stacked-capacitor cell.

Fig. 3. Noise-generating mechanisms in an open-BL array.

TABLE IBITLINE RELATED CAPACITANCES OF THEOPEN BITLINE ARRAY IN

0.13-�m TECHNOLOGY

measured with the test chip that will be described later. In theopen-BL cell, a wider BL pitch and the shielding effect of denserstorage-node contacts (SCT) than in the folded-BL cell discussedin a later section lead to a reduced .

Fig. 2 shows an open-BL array where each pair of BLs isarranged in two adjacent arrays ( ) that are separatedby sense amplifiers (SA). Four kinds of conductors work asnoise sources in each array: the p-well, the plate, the group ofnonselected wordlines, and adjacent BLs. The above capacitorsthat are related to the conductors generate noise against thecell-signal voltage on the pair of BLs whenever the voltageson the conductors are changed. generates the well-knowninterbitline coupling noise [9]. The other capacitances generatenoise due to the differential voltage swing on each of the

pairs of BLs when the BL precharging scheme isapplied ( : the highest BL voltage from the on-chip voltagedownconverter). The generation of noise can be conceptuallyexplained by a simplified array (Fig. 3), in which two separatenoise sources ( ) represent p-wells, plates, and groupsof nonselected wordlines, is the resistance of each noisesource and is the connection resistance, represents

, and , and and are the capacitancesof the noise source and BL, respectively. The simultaneousdevelopment of a large voltage swingon the background BLscouples a voltage to the noise source . The magnitudeof depends on the data pattern of the cells along the selected

SEKIGUCHI et al.: LOW-IMPEDANCE OPEN-BITLINE ARRAY FOR MULTIGIGABIT DRAM 489

Fig. 4. Schematic view of precharge and sensing noise waveforms in anopen-BL array.

wordline. The value of is maximized when BLsin an array are driven with the same polarity. The maximumvoltage is then recoupled to the target BL in the samearray through . Since the two groups of BLs and

reference bitlines (BLBs) are differentially driven,the maximum differential voltage is generated across thetarget pair of BLs. The acts as differential-mode noisewhen its polarity is opposite to the cell-signal polarity on thetarget BL. We hereafter call this pattern the worst-case datapattern for noise. When both polarities are the same, it is addedto the signal.

This noise is generated after the precharging of BLs and whencell signals are sensed, causing precharge noise and sensingnoise, respectively.

1) Precharge (PC) Noise:This is the noise that remainswhen the cell signals are sensed, as a result of the incompletedecay of the noise generated by the BL precharging operationat the end of the previous cycle. WhenBLs are prechargedto at (i.e., at the end of the previous cycle) anaccumulated voltage is coupled to the noise sources ineach array (i.e., in array ) as shown inFig. 4. Although each pair of BLs is equalized to by theprecharge signal (PC in Fig. 5), is still decaying. After thePC is turned off at , it generates the following couplingvoltage on the floating BL :

(1)

Fig. 5. (a) Array-related circuits. (b) Worst-case data pattern and location forthe open-BL array. These are common to both the original and proposed arrays.

whereis the BL slope, and is the rise-and-fall time. Here,

is reduced by a smaller time constant for the conductorand by a longer precharge time . Usually, the p-well hasthe largest (as in Table II), and thus p-well noise is the majorconcern.

2) Sensing Noise:During the sensing operation, the pair oftarget BLs receive noise from PLs, nonselected WLs, and PWs.The maximum level of noise is given by

(2)

where is the BL slope, and is the rise-and-fall time in thesensing operation. Moreover, the maximum level of noisefrom the adjacent BLs is given by . The sensing noise isthe sum of the above two types of noise, and is thus increased byincreasing (i.e., shortening the sensing time) and decreasedby reducing .

B. Concepts for Noise Reduction

One guiding principle for reducing the level of noise is toreduce the impedance (Fig. 3). This enables suppressionof the noise peak and quicker recovery to the original voltagelevel because of the lower time constants of the conductors.Bridging of noise sources and with a low-impedance( ) conductor provides a further reduction in the voltagedifference, even though the respective voltages remain coupledto each noise source. The low-impedance array shown in Table IIwas thus proposed. Here, simple -supply and plate layoutsare acceptable in the original array used with the folded BL


TABLE IIPROPOSEDOPEN-BITLINE ARRAY AND THE ORIGINAL ARRAY

Fig. 6. Operating waveforms for an open-BL array (simulated).

becauseof its inherently low-noisefeatures.Arowof -supplycontacts is placed at one end of the p-well surrounded by theSA’s n-well and the deep n-well. Both plates are composed ofTiN, and they are only connected, with Al wiring, at the ends ofthe arrays. In the proposed array, however, a row of-supplycontacts is placed at each end of each p-well region with an areapenalty of only 0.6%. Moreover, the impurity concentration ofthe p-well is increased to reduce the p-well’s sheet resistancefrom 2 k to 500 . This increase is applied only to themiddle part of the p-well to avoid detrimental effects on thememory-cell MOSTs and to keep the p-well-to- deep-n-well

breakdown voltage constant. The plate layer itself provides thebridge over the SA region between the pair of adjacent plateswithout area penalty. The tungsten (W), which is used for BLs,is also utilized to reduce the sheet resistance from 20 to2 by placing it on the TiN. The WLs sheet resistance isreduced from 10 to 2 by using a W and poly-Sidual layer [10] instead of the WSi and poly-Si dual layer of theoriginal array. Circuit simulations are an indispensable way ofevaluating the usefulness of the proposed array, because thevarious noise components are mixed at the time of sensingand their effect is closely related to the waveforms on the BLs.


(a) (b)

Fig. 7. Conditions used in the noise simulation. (a) Precharge noise. (b) Sensing noise.V = 1:4 V, V = 0 V, V = 3:1 V, t = 10 ns (t is varied inFig. 12).

Fig. 8. (a) Voltage waveforms of PW after PC, and voltage waveforms of (b) WL, (c) PL, and (d) PW, after SA activation, for the original and proposed arrays.

III. SIMULATION OF AN OPEN-BITLINE ARRAY

IN TERMS OFNOISE

A. Simulation Conditions

Distributed overdriven sensing [7], [8] for low-voltage high-speed operation and alternate placement of SAs [11] are as-sumed, as is shown in Fig. 5. The word driver (WD) clamps each

nonselected WL to by keeping the main wordline (MWL)level or a decode signal (FXB) on the hierarchical wordlineat . The array’s size is fixed to 512 WLs1024 BLs andthe BL capacitance is 110 fF, including the SA’s capaci-tance. This BL length is the same as in the standard folded-BLarray of gigabit generation [12]. The case for varied array size isshown later (Fig. 12). The worst-case location of the target BL


Fig. 9. (a) Precharge noises versus PW sheet resistance, and sensing noises versus sheet resistance of (b) WL, (c) PL, and (d) PW for the original and proposedarrays.

for the worst-case data pattern is the center of the array wherethe greatest amount of noise is generated by the nonselectedWLs. This is because WLs are alternately clamped by WDs atthe edge of the array. The sensing time of a “0” signalon the background BLs that cause sensing noise was measuredfrom SA activation to 60% of (Fig. 6), and was thus fixed at3.3 ns. The case for varied is shown later [Fig. 11(a)]. Usu-ally, nMOST and pMOST of the SA are driven simultaneously.The case where they are driven with different timing is shownlater [Fig. 11(b)]. The level of precharge noise is calculated at20 ns after precharge (PC) with a precharge time of 10 ns.This is shown in Fig. 7(a). Sensing noise is calculated as the crit-ical “1” (high) signal necessary for successful sensing, when thesignal voltage is reduced by reducing the storage-nodevoltage of the selected cell. This is shown in Fig. 7(b).

B. Simulation Results

Fig. 8(a) shows the waveforms of the voltages at the centers ofthe p-wells in Fig. 5(b) after PC has been turnedon. In the proposed array, the voltage difference between theadjacent arrays has almost vanished after 10 ns (at 55 ns in thefigure) because of the smallof the p-well in (1), while the dif-ference is still large in the original array at the same time. Thus,

PC noise is reduced from 37 mV in the original array to1 mV in the proposed array, as is shown in Fig. 9(a). Fig. 8(b),(c), and (d) show the waveforms of the voltages at the centersof the nonselected WLs , the plates ,and the p-wells of Fig. 5(b) after the activation ofSAN and SAP1. The difference in voltage between paired adja-cent sources of noise are dramatically reduced in the proposedarray. Thus, the level of sensing noise is dramaticallyreduced from 72 mV in the original array to 21 mV in the pro-posed array, as is seen in Fig. 9(b).

The noise is the sum of the contributions of the nonselectedWLs, the plates, p-wells, and BLs. Each component is extractedby intentionally decreasing the corresponding resistance, as isshown in Fig. 9. The level of PC noise diminishes when

is reduced to 0 to exclude the PW component andleave the sum of the remaining components. This is 0 mV, asshown in Fig. 9(a), which is due to the much lowervaluesfor WL and PL. The estimated PW component for the originalarray is thus 37 mV, while it is only 1 mV for the proposed array.For sensing noise , each of the four components can be ex-tracted from (b) to (d) of Fig. 9, which shows the respective re-sistive components being varied. The levels of sensing noise are48 and 18 mV for the original and proposed array, respectively,


TABLE IIINOISE COMPONENTS(SIMULATED )

Fig. 10. Precharge noise versus precharge time (t ).

when both and WD-output resistance are 0 . Thisis shown in Fig. 9(b). These values are the sums of the otherthree components (i.e., the PL, PW, and BL components), aswas described above. The levels of sensing noise atare 37 and 19 mV for the original and proposed arrays, respec-tively [Fig. 9(c)]. These are the respective sums of the WL, PW,and BL components. The levels of sensing noise atare 32 and 12 mV for the original and proposed array, respec-tively [Fig. 9(d)]. These are the respective sums of the WL, PL,and BL components. Note that the BL component is calculatedby comparing the noise level for a “0” signal on adjacent BLswith that for a “1” signal, while keeping the same data patternon the background BLs. This component is generated when thesignal is generated, as well as at the time of sensing [9], and itsrespective values for the original and proposed arrays are 9 and7 mV. Thus, the respective estimated noise components for theoriginal and proposed array are 6 and 3 mV for the WL com-ponent, 17 and 2 mV for the PL component, and 22 and 9 mVfor the PW component, as shown in Table III. For the proposedarray, the total level of noise (i.e., 21 mV) is in good agreementwith the simple sum of the extracted components.

The 72-mV value for the original array, however, is markedlylarger than the simple sum (i.e., 54 mV). This is because thecomponents are large enough to enhance each other: A largercomponent worsens the still-small signal waveform on the target

Fig. 11. (a) Sensing noise versus sensing speed. (b) SA activation timing.

BL so that the start of amplification is delayed, allowing othercomponents to be more strongly coupled with the target BLduring the resulting longer period of sensing.

1) Design-Parameter Dependence:Design parameters alsoaffect the levels of noise. We use our proposed array to demon-strate this below. Fig. 10 shows PC noise versus the prechargetime . The level of noise increases rapidly as is shorted,as would be expected from (1). Fig. 11 shows sensing noiseversus sensing time for noise generated by background BLs withall “1” signals and all “0” signals. Both types of noise increasewith the speed of sensing because of the greater BL slopein(2). The difference between the magnitudes of the noise in thesetwo cases is because of the asymmetric amplification waveformson the background BLs driven by the nMOSTs and pMOSTs inthe SAs. SAN and SAP1 are the activation signals of the nMOSTand pMOST, respectively. When SAN leads SAP1 by a certaintime in Fig. 5(a), the amount of noise generated by BLswith “1” signals increases while the noise generated by BLs with“0” signals decreases, as is shown in Fig. 11(b). In this case,for a “1” signal is decreased because of the greater gate–sourcevoltage of the nMOST in the early stage of sensing. Thus, a


Fig. 12. Dependence of the noise level on array size.

target BL with a “0” signal receives more noise, while a BLwith a “1” signal receives less noise.

2) Array Size: The noise is also closely related to the phys-ical array size. This is because a larger array means an increasedimpedance for the conductors in the array. A smaller array canthus be considered as, in a sense, a reduced impedance array.The level of noise versus the numberof WLs that intersect aBL is summarized in Fig. 12. Here, all conditions, except thatof the BL’s length, are kept the same as in the basic proposedarray. The PL and PW components fall with, because a lower

means a shorter in (2). The BL–BL and WL componentsremain unchanged because of the BL and of the WL arenot changed.

IV. EXPERIMENTS ON ANOPEN-BITLINE ARRAY

A 0.13- m 256-Mb test chip (Fig. 13) was designed on thebasis of the results of simulation and fabricated [7], [8]. Thechip incorporates the proposed low-impedance array of Table IIexcept that k . Special care was taken in mea-suring the noise in this chip. The PC noise is derived bythe critical storage-node voltage for the successful sensing ofa “1” signal on the target BL, with a “0” signal voltage on allbackground BLs. This is shown in Fig. 14(a). Obviously, theabove critical voltage, (“1”), is proportional to the level ofnoise from the background BLs. Here, the storage-node voltageof the target cell is gradually decreased, solely by decreasingthe of the previous write cycle. Even so, noise from back-ground BLs on the read cycle remains because the storage-nodevoltages of all background cells are all fixed to in the writecycle. To estimate the level of PC noise at ns withthe sensing-noise component eliminated, the difference in(“1”) between ns and ns was measured. The levelof PC noise is diminished at ns, and the differenceis proportional to the PC noise. The difference was convertedto obtain the level of PC noise by using measured values ofand .

The sensing noise is estimated from the above valuesfor (“1”) and (“0”) at ns, where the PC noise

Fig. 13. Micrograph of the 256-Mb test chip. Memory cell size= 0:109�m

has been eliminated. Here, (“0”) is the critical storage-nodevoltage for a successful sensing of a “0” signal on the target BLwith a “1” signal voltage on all background BLs, as is shownin Fig. 14(b). In the write cycle, to preserve the “1” signal onbackground BLs despite the decreasing “0” signal on the targetBL, is written to the target cell and is writtento all background cells, while the plate voltage is reduced to

. Before the read cycle, however, both andare raised to the original levels at the read cycle, and

, respectively. Thus, the storage-node voltage of the targetcell is raised from a floating to , while the voltages ofthe background cells are raised from to . Thiscondition implies that it is possible to decrease the “0” signalon the target BL by increasing while preserving the noisefrom background BLs.

Measured critical values of (“1”) and (“0”) mayinclude offset voltages arising from the SA’s offset, BL’sprecharge level caused by capacitive coupling of the equalizerMOSTs just after precharging, and the WL–BL couplingvoltage when activating the WL. To compensate for suchoffsets, the difference between (“1”) and (“0”) ismeasured. This is proportional to the sum of the for thebackground BLs carrying “0” signals and the for thebackground BLs carrying “1” signals. The average level ofnoise can then be obtained by dividing this sum bytwo. The effect of the deviation of the and value is alsocompensated for by using the relationship between the numberof bit failures and the . In Fig. 15(a), the horizontal axesindicate and as calculated by measuring the average

and . Ideally, all bits fail when the signal level becomesequal to the noise level. In practice, however, the criticalhas some distribution that is due to fluctuations in theand

values. By examining the distribution of for manycells in the array, the levels of noise can be estimated from

by using the measured average of and values. Thedifference between the levels of noise at the center and edgesof the array is quite small, due to the alternate placement of

clamps in the word drivers. The difference between thedistributions of (“1”) and (“0”) was almost constantfor numbers of failed bits in the range from 0.1 to 10%, and thisdifference can be regarded as the sum of values describedabove.

Fig. 15(b) shows noise levels measured by means of the abovetesting methodology. It is obvious that a of 34 mV is ingood agreement with the simulated of 38 mV obtainedwith the fabricated device parameters. Thus, the utility of the


Fig. 14. Critical storage node voltagesV (“1”) and V (“0”) measured by varyingV andV with (a) all “0” values on the background BLs, and (b) all“1” values on the background BLs, respectively.

low-impedance open-BL array and of our simulation method-ology have been confirmed by the test chip.

V. DISCUSSION

Since the method of simulation has been verified as useful,we now compare, on the basis of simulation, noise levels inthe low-impedance open-BL array and the folded-BL array. Inan folded-BL cell with stacked capacitors (Fig. 16), thereis a large imbalance between the two s (i.e., and

) due to the side effects of the advanced process tech-nology: is only 4% of (Table IV), because theformer is from the thick (200-nm) interlayer dielectric and thelatter is from the thin (40-nm) WL side walls used in the self-aligning contact process around the oval-shaped BCT [12]. Inaddition, the lower BL pitch of and sparse storage-nodecontacts increase the value of . In the folded-BL array,noise from nonselected WLs caused by the imbalance ofand BL–BL noise due to are major noise components,

since the PL and PW noise components are negligible due tothe well-known cancellation effect. The former, however, is de-creased by the twisted BL that was originally introduced for theBL–BL noise reduction [13], as shown in Fig. 17. For example,the noise on a target BL pair in the nontwisted-BL array ishalved in the twisted array since the voltages on andare canceled out.

Noise in the folded-BL array was simulated by using theBL-related capacitances in Table IV and the device parametersfor the proposed array given in Table II, except forand s.The large of 28 fF is acceptable due to the larger cell size, and

s for the p-well and WL are 60 and 10 k , respectively,due to the larger array in the WL direction. is smaller (i.e.,85 fF) because the number of memory cells on a BL is halved(256 cells) due to the shared-SA capability. This is shown inFig. 18. Fig. 19(a) shows voltage waveforms on the nonselectedWLs after activation of the twisted-BL array’s SAs. The voltagedifference between and is decreased despite the largevoltage difference between and , as expected. As a


Fig. 15. (a) Method of noise measurement and (b) measured array noise in thetest chip.

(a) (b)

Fig. 16. 8F folded-BL memory cell. (a) Top view. (b) Cross-sectional view.

result, the twisted-BL array reduces the total sensing noise in-cluding the nonselected WL and BL–BL components, from 59to 23 mV. This is shown in Fig. 19(b). Hence, the nonselected

Fig. 17. Reduction of noise on nonselected wordlines by twised BL.

TABLE IVBITLINE RELATED CAPACITANCES OF THEFOLDED-BL ARRAY IN

0.13-�m TECHNOLOGY

Fig. 18. Worst-case location and worst-case data pattern for folded-BL array.Only nontwisted BLs are shown.

WL component is estimated to be 9 mV from the de-pendence, in the same manner as before. Intrabitline noise re-mains as high as 14 mV. This is derived from the noise level at

, and is due to the larger value.Fig. 20 gives comparative figures for the total noise level

as simulated for the open-BL array and folded-BL array. The


Fig. 19. (a) Nonselected WL voltage waveforms, and (b) sensing noise versusWL sheet resistance.R of nonselected WD is intentionally set to0 at�(WL) = 0 for analysis of the noise component from nonselected WLs.

Fig. 20. Total array noise (simulated).

low-impedance open-BL array reduces the noise level fromthe 109 mV of the original array to 22 mV. The twisted andfolded-BL array reduces the noise level from the 59 mV of thenontwisted BL to 23 mV. Consequently, the noise level of theopen-BL array is comparable to that of the folded-BL array.

VI. CONCLUSION

The noise-generating mechanisms that are inherent in theopen-BL DRAM array using memory cells and noisereduction techniques have been described. The sources ofthe differential noise that is coupled to the paired BLs laidout in two arrays are the p-well, cell plate, and the group ofnonselected wordlines. A low-impedance open-BL array hasthus been proposed. Its features are low-resistivity materials,tight bridging between the two adjacent arrays, and smallarrays. Although these techniques increase process costs dueto adding new materials, the increase will become small whenprocess technology has matured. Simulation demonstratedthat the proposed array structure was capable of dramaticallylowering the level of noise for a 0.13-m 512-kb subarray,from the 109 mV for the conventional array structure to 22 mV.This is comparable with the 23-mV noise level for the twistedand folded-BL array. The results of simulation were verified byexperiments with a 0.13-m 256-Mb test chip with cells.These noise reduction techniques for the open-BL cell arraywill be important in realizing cost-effective chip sizes for themultigigabit generation, and will be indispensable in achievingthe ideal cross-point memory cell of the future.

ACKNOWLEDGMENT

The authors thank S. Shimizu, K. Miyazawa, Y. Kinoshita,and M. Mishima for their encouragement of this work, R. Hori,Y. Tadaki, T. Sakata, and R. Takemura for discussions on noiseanalysis, S. Kimura, T. Sekiguchi, H. Matsuoka, Y. Nakamura,S. Yamada, and H. Asakura for memory-cell process integra-tion, and S. Miyatake, M. Morino, K. Arai, H. Otori, S. Narui,H. Kawamura, and M. Ebihara for test-chip design and evalua-tion.

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Tomonori Sekiguchi(M’93) was born in Kanagawa,Japan, on October 9, 1968. He received the B.S. de-gree in physical electronics and the M.S. degree inelectrical and electronic engineering, both from theTokyo Institute of Technology, Tokyo, Japan, in 1991and 1993, respectively.

He joined the Central Research Laboratory,Hitachi Ltd., Tokyo, in 1993. Since then, he has beenengaged in the research of DRAMs.

Mr. Sekiguchi is a member of the Institute of Elec-tronics, Information and Communication Engineers

of Japan.

Kiyoo Itoh (SM’89–F’96) received the B.S. andPh.D. Degrees in electrical engineering from TohokuUniversity, Sendai, Japan, in 1963 and 1976.

Since 1972, he has led memory (especiallyDRAM) technology at Hitachi Ltd. He was the leaddesigner of the first prototype for eight generationsof Hitachi DRAMs ranging from 4 kb to 64 Mb. Hehas also developed low-power/low-voltage CMOScircuits focusing on subthreshold current reductionsince 1988. He is currently one of two Fellowswith Hitachi Ltd., Tokyo, Japan. He was a Visiting

MacKay Lecturer at the University of California, Berkeley, in 1994, and aVisiting Professor at the University of Waterloo, Waterloo, Canada, in 1995,and is currently a Consulting Professor at Stanford University, Stanford, CA.He holds over 140 patents, including the folded bitline, in both Japan and theU.S. He has authored or co-authored three books (Memory Chip Design, LowPower Design Methodology, and VLSI Memory Chip Design) and over 110papers in IEEE journals and conference proceedings.

Dr. Itoh won the IEEE Paul Rappaport Award in 1984, the Best Paper Awardof the IEEE ESSCIRC’90, and the 1993 IEEE Solid-State Circuits Award. Hehas won many awards in Japan, including the Commendation by the Ministerof State for Science and Technology (Person of Scientific and TechnologicalMerits) in 1997, and a National Medal of Honor with Purple Ribbon in 2000.

Tsugio Takahashi (M’00–A’01) was born inMiyazaki, Japan, on April 13, 1964. He received theB.S. degree in electronic engineering from ShizuokaUniversity, Shizuoka, Japan, in 1989.

He joined the Device Development Center, HitachiLtd., Tokyo, Japan, in 1989, where he has been en-gaged in the design of MOS DRAMs. In 2000, hewas temporarily transferred to Elpida Memory, Inc.,Kanagawa, Japan.

Masahiro Sugayawas born in Tokyo, Japan, on De-cember 3, 1958. He received the B.S. and M.S. de-gree in mechanical engineering from the Universityof Electro-Communications, Tokyo, Japan, in 1982and 1984, respectively.

He joined the Central Research Laboratory,Hitachi Ltd., Tokyo, Japan, in 1984. He wastransferred to the Semiconductor and IntegratedCircuit Division, Hitachi Ltd., Tokyo, in 1995. Hehas been engaged in the research of process anddevice simulation on silicon devices.

Hiroki Fujisawa (M’00) was born in Saitama, Japan,on December 14, 1969. He received the B.S. degreein electrical and electronic engineering and the M.S.degree in information and processing from the TokyoInstitute of Technology, Tokyo, Japan, in 1992 and1994, respectively.

In 1994, he joined the Device DevelopmentCenter, Hitachi Ltd., Tokyo. From 1994 to 1999,he worked on developing MOS memories. In 2000,he was transferred to Elpida Memory, Inc., theNEC–Hitachi DRAM manufacturing joint venture.

Since then, he has worked on developing DRAMs.

Masayuki Nakamura (M’94) was born in Aichi,Japan, on June 28, 1961. He received the B.S.and M.S. degrees in electrical engineering fromNagoya University, Aichi, Japan, in 1985 and 1987,respectively.

In 1987, he joined the Device Development Center,Hitachi Ltd., Tokyo, Japan, where he has been en-gaged in the design of dynamic RAMs. In 2000, hewas temporarily transferred to Elpida Memory, Inc.,Kanagawa, Japan.

Kazuhiko Kajigaya was born in Tokyo, Japan, onSeptember 29, 1956. He received the B.S. degreefrom Waseda University, Tokyo, Japan, in 1979.

In 1979, he joined the Device DevelopmentCenter, Hitachi Ltd., Tokyo. From 1979 to 1999, hewas engaged in the development of MOS memories.In 2000, he was transferred to Elpida Memory,Inc., the NEC–Hitachi DRAM manufacturing jointventure. Since then, he has been engaged in thedevelopment of DRAMs.

Katsutaka Kimura (M’90) was born in Osaka,Japan, on January 26, 1956. He received the B.S.and M.S. degrees in electronic engineering fromKyoto University, Kyoto, Japan, in 1978 and 1980,respectively.

He joined the Central Research Laboratory,Hitachi, Ltd., Tokyo, Japan, in 1980, where he hasbeen engaged in the research and development ofMOS memories, such as DRAMs, BORAMs, andflash memories, as well as solid-state image sensors.

Mr. Kimura is a member of the Japan Society ofApplied Physics and the Institute of Electronics, Information and Communica-tion Engineers of Japan.

a low-impedance open-bitline array for multigigabit dram...

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