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Ind. Co., Ltd. for their continuous encouragement and providing theexperimental devices used in this paper.REFERENCES

[ I ] C. F. Hawkins, I. M. Soden, E. 1. Cole, Jr., and E. S. Snyder, Theuse of light emission in failure analysis of CMOS ICs, Int. Symp. f o rTrsting and Failure Analysis. pp. 5 5 4 6 , 1990.[2] N. Tsutsu, Y.Uraoka, T. Morii, and K. Tsuji, Life time evaluation ofMOSFET in ULSIs using photon emission method, Proc. IEEE Int.Conf. on Microelectronic Test Structures, pp. 94-99, Mar. 1992.

131 T. Ohzone and H. Iwata, Photoemission characteristics of reverse-breakdown ii+-diodes with LOCOS- and trench-isolation, Proc. IEEEI n t . Conf. on Microelectronic Test Structures, pp. 177-182, Mar. 1993.[4 ] G. Fuse, H. Ogawa, K. Tateiwa, 1. Nakao, S . Odanaka, M. Fukumoto, H.

the parameters may be difficult because it involves the nonlinearoptimization and the minima of the objective functions may not belocated within reasonable number of iterations. On the other hand, theBSIM [6], [7] used a lot of redundant parameters and some of theseparameters even have no any physical justification and u nfortunatelylarge errors were still found (71. The latest version of B S I M ha s morestronger physical basis and has several improvements [8]. However,the physical functional forms are still very complicated. In this work,we aim at the development of a simple short-channel model thatis suitable for device analysis and circuit simulation. The model isdeveloped by incorpo ration of some secondary effects into Pao-Sahsequation. It is a new attempt although similar treatment may befound in characterizing other parameters. A completely new form

, LConf. on Microelectronic Test Structures, pp. 34-38, Mar. 1992. computation efficiency.161 T. Ohzone and H. Iwata, Channel-width measurements of LOCOS- andtrench-isolated n-MOSFETs by photoemission, Proc. IEEE Int. Con5

on Microelectronic Test Structures, pp. 269-274, Mar. 1993. 11. DEVICEQUATIONORMULATIONAccording to Pao and Sah [I],he current-voltage ( I - V ) character-istics for long-channel MOS transistor can be modeled by

A New Approach to Current-Voltage Ch aracteristicsFormation for Short-Channel MOSFETs where C,,,, S i n , T i ) , and 12; are the oxide capacitance per unit area,threshold voltage, drain-to-source voltage and gate-to-source voltage,H. Wong

Abstract-A new ap proach to the current-voltage (I-V) characteristicsformulation for short-channel MOSFETs by in corpor ating the channellength m odulation, mobility degradation, drain induced harrier lowering,and threshold voltage variation into Pao4ahs equation is presented.Results show that the calculated I-V characteristics agree well with theexperimental ones for devices with effective channel length in the rangeof 0.44 N 20 irm. Compared with the existing models, the model has theadvantages of less number of model parameters and simpler form of thecurrent-voltage relationship.

respectively. T I 7 and L are the effective channel width and channellength, respectively. The channel mobility p in (1) can be modelledby the empirical equation given below [9],

where 110 is the bulk mobility of substrate, E,,,, is the saturationelectric field, and 0 is an empirical parameter.At saturation region, the I-V characteristics of MOSFET is given

by(3 )

I. INTRODUCTIONAs the classical device equation based on the gradual channelapproximation [1]-[2] s no longer suitable for submicron MOS-FETs, several complicated yet more precise models by consideringthe charge sharing effects in the two dimensional structure [3]

Supposing that the saturated I-V characteristics for the short-channelMO S transistors (IDS)o not divert greatly from Pao-Sahs equation,IDS an be approximated by

I D S= I D S O 6 L .-I u soL +sr;.- I ID SO d I D S 0+ 611 .-p . (4)or based on solving the two-dimensional Poissons equation [4],were developed. However, the complicated equation forms prohibitthemselves be used for device evaluation and circuit simulationpurposes, not only due to the computational overhead but also becauseof the difficulties in determining the model parameters with theautomatic parameter extraction facilities. Then semi-empirical modelswere developed [SI-[7]. The accuracy of these models was improvedby adding a n umber of empirical parameters in addition to thephysical ones. However, these models are in term of som e nonlinearfunctions and involve sophisticated measurements for extracting themodel parameters [SI. Determination of the values for some ofManuscript received M ay 7, 1994; revised July 20, 1994. The review ofTh e author is with the Department of Electronic Engineering, City Poly-IEEE Log Number 9405946.

this brief was arranged by Associate Editor K. Tada.technic of Hong Kong, Kowloon, Hong Kong.

The change of effective channel length, a i , due to drain bias canbe approximated by [ I O ] ,6L = - - 7 ( J 0 D + rb - h,*t -6) 5 )

where N B , E . ; , , eo an d y are the substrate doping concentration,dielectric constant of silicon, permittivity in vacuum, and electroncharge, respectively. O D is an empirical parameter [lo]. n~ is thefree charge density in the depletion region. The minus sign in ( 5 )represents the reduction of channel length. By equating the driftcurrent in the depletion region to 1 ~ 5 0 ,I D can be approximated by

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where TGT = Vi: - Tko, and T~ is the junction depth of drainjunction. Here we have assumed that the channel thickness is muchsmaller than the junction depth and averaged cross-section area forthe current flow will be Tt7xJ/2 .The saturation drain voltage in (5) is given by [111,

On the other hand, the threshold voltage is also sensitive to thedrain bias. Considering the effect of drain induced barrier lowering[12], we have

where O B is the surface-inversion potential of silicon. Further con-sidering the channel length modulation effect, we get,

And the change of mobility is(9)

Substituting (9 , 9) and (10) into (4), we have the final expressionfo r IDS ,

x [ ?+ L ( & D + L b - L T D d - &)I (11)2fS10(208+ Lb) . 2 + (0 + 2/EsatL)lcT

(1+ % l k T ) ( I+ 2 l? ,T /&atL)F = C,,LT~;T1+ 1+ LD/&LIt is noted that only two additional parameters, 2 and 00, reintroduced into the equation for saturation current that is given in

( 1 1). Other parameters are already appeared in the ohm ic region I-Vcharacteristics. In addition, it can be readily shown that IDSn (1 1)will reduce to IDSOor long-channel devices and the saturation draincurrent, IDS,s equal to the linear region drain current at T b = 1Dsat.Furthermore, the drain conductance in the transition between thelinear and saturation regions is continuous by considering the biasdependence of the free charge density in the depletion region.111. RESULTS ND DISCUSSION

In order to verify the validity of the new analytical model, thecalculated device characteristics are compared with the experimentaldata. Fig. 1 plots the experimental (continuous lines) and calculated(open circles) I-V characteristics for n-channel MO S transistors witheffective channel lengths of 0.44 and 1.04 pm which were fabricatedusing the standard polysilicon gate technology. For theoretical charac-teristics, equation (1) was used for ohmic region and (11) was usedfor saturation region plots. The parameters used in the theoreticalplots, except for -, which depends on the channel length, substratedoping, and junction depth, are extracted from the I-V curves in theohmic region of the device with effective channel length of 1.04 pm .The values for the parameters 0 , f .at , o , ar e 0 .1 5 V - I , 1 . 0 5 ~ 1 0 ~V/cm, and 513 cm 2/V s, respectively. C,, and L Y ~re 0.1 pF/cm2and 2 x l O I 5 cm P3 , respectively, which agree well with the resultsfrom CI measurement. For the sake of sim plicity, OD is assumed tobe zero in the curve fittings. This treatment only introduces a small

8 17-

6 -

z5 -1 4 -s 3 -

2 -

1

0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5DRAIN VOLTAGE (V)(a)

Fig. 1. Comparison between experimental and calculated current-voltagecharacteristics for n-channel MOSFET with effective channel length of (a)0.44 pm and (b) 1.04 pm. The bottom curve in each plot corresponds tot, = 1 V and step for I& is 1 V. Same set of model parameters whichwere obtained from parameter extraction was used in the theoretical plots forthe devices.error in the transition region of the drain current although large errormay be found in drain conductance in this region [lo]. As shown inFig. 1, the calculated results agree well with the experimental datain the whole range of T i : and bias for the transistors. Neitherdiscontinuity nor excess error are found at the transition betweentriode and the pentode regions. The maximum error between theexperimental and theoretical results is about 5% for 0.44 pm longdevice and less than 3% for devices with channel length in the rangeof 1 - 0 pm. Hence, this model is valid for devices with channellength down to 0.44 pm . How ever, further experimental validation isneeded for the applicability of this model to shorter devices. Othereffects, e.g., punchthrough, and subthreshold conduction, and velocityovershoot [13], should also be considered in deep submicron devices.

IV . CONCLUSIONA simple short-channel MOSFET model has been developed by

incorporating the secondary effects into Pao-Sah equation. The

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model shows good agreement with the experimental data. Most ofthe phenomena observed in short-channel devices, including finiteconductance at saturation or channel length modulation effect, draininduced threshold shift, mobility saturation, were considered. Theadvantage of the newly developed model is its applicability to shortchannel devices without using sophisticated mathematical treatmentand complicated function or a large number of empirical parameters.This model can be used for both device evaluation and circuitsimulation.

ACKNOWLEDGMENTThe devices used in this work were fabricated in the Microelec-tronic Institute of Tsinghua University, China.

REFERENCESH. C. Pa0 and C. T. Sah, Effects of diffusion current on character-istics of metal-oxide (insulator)-semiconductor transistors, Solid-stateElectron., vol. 9, pp. 927-937, 1966.L. D. Yau, A simple theory to predict the threshold voltage of short-channel IGFETs, Solid-Slate Electron., vol. 17, pp. 1059-1063, 1974.L. A. Akers and J. J. Sanchez, Threshold voltage models of short,narrow and small geometry MOSFETs: A review, Solid-Srate Electron.,vol. 25, p. 621, 1982.P. S. Lin and C. Y. Wu, A new approach to analytically solving thetwo-dimensional Poissons equation and its application in short channelMOSFET modeling, IEEE Trans. Electron Devic es, vol. ED-34, pp.1947-1956, 1987.C. K. Park. C. Y. Lee, K. Lee, B . J. Moon, Y. . Byun and M. Shur,A unified current-voltage model for long-channel nMOSF ETs, IEEETrans. Electron Device s, Vol. ED-38, pp. 399406, 1991.B. J. Sheu, D. L. Scharfetter, P. K. KO, and M. Jeng, BSIM: Berkeleyshort-channel IGFET model for MOS transistors, IEEE J. Solid-StareCircuits, vol. SC-22, pp. 558-566, 1987.M. C. Jeng, P. M. Lee, M. M. Kuo , P. K. KO , and C. Hu , Theory,algorithms, and users guide for BSIM and SCALP , Univ. C alifomia,Berkeley, memo UCB/ERL M87/35, 1987.J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. KO, and C. Hu, Robustphysical and predictive model for deep-submicrometer MOS circuitsimulation, Proc. IEEE 1993 Custom Integrated Circuits Con&, SanDiego, 1993, p. 14.2.1.H . Q. Su, C. C . Wei, and T. P. Ma, Mobility degradation in verythin oxide p-channel MOSFETs, lEEE Trans. Electron Device s, vol.ED-32, p. 559, 1985.Y. P. Tsividis, Operation and Modeling of rhe MOS Transistor. NewYork: McGraw-H ill, 1987, p. 172.C. G. Sodini, P. K. KO , and J. L. Moll, The effect of high fields onMO S device and circuit performance, IEEE Trans. Electron Devices,vol. ED-31, pp. 1386-1393, 1984.T. Skotnichi and W. Marciniak, A new approach to threshold voltagemodeling of MOSFETs, Solid-state Electron., vol. 29, pp. 1115-1 128,1986.K . Sonoda, K . Taniguchi, and C. Hamaguchi, Analytical device modelfo r submicrometer MOSFETs. IEEE Trans. Electron Devic es, vol. 38,pp. 2662-2668, 1991.

An Orthogonal-Transfer CCD ImagerB. E. Burke, R. K. Reich, E. D. Savoye, and J. L. Tonry

Abstract-We describe a new two-dimens ional CCD imager structurecapable of transfe rring charge packets in all four d irections, as well asexperimental results on a 64 x 64-pixel prototype device. Applicationsinclude astronomical imaging where the charge shifting can be madeto track the tip-tilt correction for atmospheric turbulence and therebyimprove image resolution.

Conventional CCD imagers, though two-dimensional (2D) in struc-ture, are capable of transferring a charge-packet array along a singledimension at most. A CCD which can transfer charge in all fourdirections could find use in imaging applications where the chargewould be shifted to track a moving image and thereby eliminate blur.SCquin proposed a structure capable of true 2D transfer which hadfive clock phases and could be realized with five conductor levels, aswell as an alternative version which used only three conductor levels[I]. From a fabrication point of view the former has the virtue ofbeing immun e to intralevel gate-gate shorts, but has the drawb ack ofrequiring more conductor levels. The latter version, on the other hand,requires gates for separate clock phases to be fabricated on the sameconductor level (therefore leaving it vulnerable to intralevel shorts),and in addition requires these gates to be closely abutted. For goodcharge transfer the gap between these gates must be less than 1 / tm,and this exacerbates the susceptibility of this structure to intralevelshorts. The only 2D-transfer CCD demonstrated thus far has beena 32 x 32 device by Kansy that was developed as a reformattinganalog memory for 2D Fourier transforms, but his structure allowedonly unidirectional transfer in each of two orthogonal directionsP I .We describe here a new 2D CCD structure, which we term anorthogonal-transfer CCD (OTCCD), that is capable of transferringcharge in all four directions. In contrast to SCquins proposed struc-ture, this device is implemented as a four-phase device in fourconductor levels. It thus features immunity to intralevel shorts withone less level and can therefore be applied to large-area devices withthe prospect of high yields. We also describe some initial results on a64 x 64pixel prototype frame-transfer imager in which the OTCCDstructure is used in the imaging pixels.Fig. 1 illustrates the basic features of the CCD cell, with the fourgate levels, or phases, labeled G1-G4. With G1 biased low to act asa channel stop, gates (32434 can be clocked in a con ventional three-phase manner to transfer charge vertically. Likewise, the gates G2 canbe biased low and gates G 1, G 3 , and G4 can be clocked to transfercharge horizontally. Conventional channel stops (such as LOCOS ) arerequired under the intersection of the GI and G2 gates and are shownas shaded areas. Fig. 2 shows a portion of an OTCCD pixel arrayfrom the imaging section of a 64 x 64-pixel frame-transfer imager.

Manuscript received March 1, 1994; revised July 27, 1994. The review ofthis paper was arranged by Associate Editor W . F. Kosonocky. This work wassupported by the Department of the Air Force and by the National ScienceFoundation under Contract Number AST 89-58065.B. E. Burke, R. K. Reich, and E. D. Savoye are with the Lincoln Laboratory,Massachusetts Institute of Technology, Lexington, MA 02173-9 108 U S A .J. I To ny is with the Department of Physics, Massachusetts Institute ofTechnology, Cambridge, MA 0 2139-4307 U S A .IEE:E L og Num ber 9406195 .

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