a new chipset for qemu - intel's q3515 jason baron irq routing i440fx/piix4 vs. q35 q35 pirq...
TRANSCRIPT
![Page 1: A New Chipset For Qemu - Intel's Q3515 Jason Baron IRQ Routing I440FX/PIIX4 Vs. Q35 Q35 PIRQ has 8 pins - PIRQA-H Q35 has two modes – legacy PIC vs I/O APIC Q35 runs in I/O APIC](https://reader030.vdocument.in/reader030/viewer/2022040603/5e9b500b7a87cf1879142fcb/html5/thumbnails/1.jpg)
Jason Baron1
A New Chipset For Qemu - Intel's Q35
Jason [email protected] 7th, 2012http://people.redhat.com/~jbaron/q35/
KVM Forum 2012
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Jason Baron2
Agenda
● Introduction to Q35
● PCIe
● Differences between I440FX/PIIX4 and Q35
● Current status
● How to try this at home
● Todo
● Discussion
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Jason Baron3
Why do we need a new chipset?
● We want PCIe, PCIe, PCIe...● Currently we use I440FX/PIIX4 (sort of)● 'sort of' goes a long way...10+ years● So we don't get backed into a corner● Better experience● Easier to add chipsets in the future● I440FX/PIIX4 has been hardened for quite
some time
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Jason Baron4
Why Q35?
● Isaku Yamahata said 'I have a real machine'
● Lots of devices already – USB, sound, bridges, AHCI
● Lots of docs (Trust me)
● Has PCIe
● Emulation can be hard – lots of work already on it (Isaku Yamaha, Jan Kiszka)
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Jason Baron5
What is Q35?
● Intel chipset released September 2007
● North Bridge: MCH
● South Bridge: ICH9
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Jason Baron6
What isn't Q35?
● Isn't the latest Intel chipset (Yes, I know)
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Jason Baron7
What is PCIe?
● Introduced by Intel/Dell/HP/IBM 2004 designed to replace PCI, PCI-X, and AGP
● Point-to-point topology
● PCIe AER
● PCIe Hotplug
● Backwards compatible with PCI
● Some drivers are PCIe specific
● Extended configuration space
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Jason Baron8
PCI Configuration Space Access
0x0000
0xFFFF
0x0CFC
0x0CF8
23 16 15 11 10 8 7 0
bus dev fn offset
data
0x00
0xFF
Port I/O
PCI Configuration Space
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Jason Baron9
PCIe Configuration Space
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Jason Baron10
PCIe MMCONFIG
256 buses * 32 devices * 8 functions * 4096 registers = 256MB required
Let's access: Bus 5, Device 0, Function 3, Register offset 85
5 * 0x100000 + 0 * 0x8000 + 3 * 0x1000 + 0x85 = 5003085
0x0000
0xFFFF
0x0000 0000
0xFFFF FFFF
0xC500 3085
0xD000 0000 256MB MMCFG Area
0xC000 0000
0x0085
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Jason Baron11
PCIe AER
Interrupt
PCIeDevice
RootPort
Error!
RootPort
PPB
PPB PPB PPB
switch
Bus 2Bus 2
Physical Host Bus
Virtual Host Bus
Device Assignment
Host OS
Insert Error
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Jason Baron12
Topology of I440FX/PIIX4 Vs. Q35
● Q35 has IOMMU
● Q35 has PCIe
● Q35 has Super I/O chip with LPC interconnect
● Q35 has 12 USB ports
● Q35 SATA vs. PATA
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Jason Baron13
I440FX/PIIX4
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Jason Baron14
Q35 Topology
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Jason Baron15
IRQ Routing I440FX/PIIX4 Vs. Q35
● Q35 PIRQ has 8 pins - PIRQA-H
● Q35 has two modes – legacy PIC vs I/O APIC
● Q35 runs in I/O APIC mode
● Slots 0-24 are mapped to PIRQE-H round robin
● PCIe Bus to PIRQ mappings can be programmed● Slots 25-31
● Q35 has 8 PCI IRQ vectors available, I440FX/PIIX4 only 2
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Jason Baron16
I440FX/PIIX4 INTx routingSlot #
PCI BusIRQ0
IRQ10
IRQ11
Programmable InterruptRouter (PIRQ)
I/O APIC
0
1
0
1
2
3
4
5
4
6
To CPU
PIRQ APIRQ BPIRQ CPIRQ D
6
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Jason Baron17
Q35 INTx routingSlot #
PCIe BusIRQ 0
IRQ 10
IRQ 11
Programmable InterruptRouter (PIRQ)
I/O APIC
0
1
0
1
2
3
4
5
4
6
To CPU
PIRQ APIRQ BPIRQ CPIRQ DPIRQ EPIRQ FPIRQ GPIRQ H
IRQ 21
IRQ 23
IRQ 22
IRQ 18
IRQ 16
IRQ 18IRQ 19
IRQ 17
IRQ 20
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Jason Baron18
Physical Memory Layout
● MMConfig window
● 32-bit pci space now fixed doesn't float down
● MMConfig window a problem for a 32-bit OS
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Jason Baron19
Physical Memory Layout
Dos Compatibility Memory 1MB
0xb0000000
Low RAM
MMconfig0xc0000000
4GB
PCI Config Space
PCI Config Space
High RAM.
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Jason Baron20
Physical Memory Layout – '(qemu) info mtree'
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Jason Baron21
I440FX/PIIX4 vs. Q35 devices
● AHCI vs. Legacy IDE
● PCI addresses
● Populate slots using flags
● Default slots
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Jason Baron22
Q35 Vs. I440FX/PIIX4 – 'lspci'
Q35:
I440FX/PIIX4:
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Jason Baron23
PCI Bridges (I440FX/PIIX4) Vs. PCIe Switches (Q35)
● PCI Bridge
● Root, upstream, downstream ports
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Jason Baron24
PCI Topology
vga e1000PPBvirtioscsi PPB
Bus 1
Bus 0
Bus 2
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Jason Baron25
PCIe Topology
e1000 virtioscsi
PCIeToPCI
Bridge
Bus 0
Bus 9
vga
Bus 1
PPB
PPB PPB PPB
switch
Bus 2Bus 2
Bus 3Bus 4 Bus 5
Bus 6 Bus 7 Bus 8
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Jason Baron26
Current Status
● Merge Plans
● What I can do on Q35 that I can't on I440FX/PIIX4, right now?
● OS support – Fedora 16, 17, Windows XP, 7, 8, BSD, OSX (Gabriel Somlo)
● Passthrough/VFIO
● Migration testing
● Hotplug
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Jason Baron27
Don't Try This At Home
● git clone git://github.com/jibaron/q35-qemu.git
● git clone git://github.com/jibaron/q35-seabios.git
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Jason Baron28
Todo - AHCI
● Cleanups
● Migration
● Optimizations
● Testing! Testing! Testing!
● Command line interface● hda-hdd continues to create IDE disks● if=ide continues to create IDE disks● AHCI drives specified using if=none and -device (see
previous slide for details)
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Jason Baron29
Todo - Hotplug
● Multiple levels of PCI hotplug. Scale?
● Hotplug PCIe switches?
● Goal: no advance setup
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Jason Baron30
Todo
● PCIe passthrough, VFIO
● Add AER capture and pass to guest – topologies could differ
● Windows 8 boots every other time :)
● Add OSX support
● Fill-out options -usb, etc.
● Libvirt changes?
● Create smarter INTx allocations?
● Performance testing – AHCI, INTx devices
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Jason Baron31
Questions?
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Jason Baron32
Thanks!