a new hetero-material stepped gate (hsg) soi ldmos for rf power amplifier applications

8/14/2019 A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications

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Fig. 1. Cross sectional view of (a) conventionalLDMOS (b) HSG LDMOS.

Table.1. Device parameters used insimulation .

Gate length,

(LG1, L G2 and L G3)0.3 m, 0.7 m and 0.4m

Gate oxide thickness,

(tox1 , tox2 and t ox3)25 nm, 50 nm and 150nm

Channel length, L 0.5 m

Buried oxide thickness 400 nm

Silicon thickness 1 m

Drift region length 2.3 m

Source/Drain doping 110 cm -

Drift region doping 210 cm -

Channel doping 110 cm -

Threshold voltage 1.85 V

Fig. 2. Process steps to fabricate HSG LDMOS.

Fig. 2 shows the proposed fabrication procedure of HSG gate LDMOS. This process is similar to themethod proposed by Xing et al [7]. The fabrication

process begins with an SOI wafer with an n-siliconlayer with a doping of 210 16 cm -3. The first 0.3 mlong p + poly gate is formed on a 25 nm thermallygrown gate oxide using standard photolithography asshown in Fig. 2 (a). Subsequently, a 50 nm lowtemperature oxide (LTO) and over that n + poly isdeposited. Using blanket reactive ion etching (RIE),the polysilicon layer is etched leaving a sidewall

polysilicon layer as shown in Fig. 2(b) which will nowact as the second gate of 0.7 m length. Now, we

deposit 100 nm LTO and over that p+

poly is depositedand etched back to form 0.4 m long third gate asshown in Fig. 2 (c). A chemical-mechanical polishing(CMP) process will planarize the gate as shown in Fig.2(d). Once the gate is defined, rest of the fabrication

process is similar to the conventional LDMOSfabrication. After metallization process, source, drainand gate contacts are formed and all the three gatesshorted resulting in the final HSG LDMOS structureshown in Fig. 1(b).

3. Simulation results and discussion

We have created the conventional and proposeddevice structure in ATLAS, a two dimensional devicesimulator. The design of the LDMOS is doneaccording to RESURF principle [8]. The effect of hetero-material stepped gate on breakdown voltage,DC characteristics, gate charge transients andswitching characteristics are discussed below.


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Fig. 3. Breakdown voltage of conventional and

HSG LDMOS.

Fig. 4. Electric field distribution along the

surface of conventional and HSG LDMOS at adrain voltage of 40 V.

3.1. Breakdown Voltage

Breakdown voltage of LDMOS is the drain voltage atwhich the off state current rises abruptly with theincrease in drain voltage (we have taken this draincurrent as 1 pA/m). The breakdown voltagecharacteristics of the HSG LDMOS and theconventional device are shown in Fig. 3. It can be seenthat the proposed device exhibits an enhanced

breakdown voltage by about 29% compared to the

conventional LDMOS.The stepped gate in the drift region enhances RESURFand introduces additional electric field peaks as shownin Fig. 4. These additional peaks reduce the mainelectric field peak from 7.1 10 5 V/cm to 4 10 5 V/cmand also smear the electric field uniformly resulting inimproved breakdown voltage.

Fig. 5. Output characteristics of conventionaland HSG LDMOS.

Fig. 6. On-resistance of conventional and HSG

LDMOS.

3.2. DC Characteristics

The output characteristics of the HSG LDMOS and theconventional LDMOS are shown in Fig. 5, it can beobserved that the proposed device has higher draincurrent than the conventional device. The reduced gateoxide at the source end improves the channel chargedensity thereby increasing the drain current. Theimprovement in drain current is approximately 60% atVGS = 4 V and V DS = 20 V. Due to the improved draincurrent, specific on-resistance also decreases as shown

in Fig. 6. The improvement in on-resistance is 32% atVGS = 6 V. Here, the specific on-resistance iscalculated as the ratio of drain current by drain voltage

per unit area at the gate potential of 6 V. Furthermore,the HSG LDMOS shows 13% enhancement in peak transconductance than the conventional device asshown in Fig. 7. This improvement is again due to theimproved channel charge density.


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Fig. 7. Transconductance of conventional and

HSG LDMOS.

Fig. 8. Gate charging transient curves forconventional and HSG LDMOS for 10 A gate

charging current.

3.3. Gate-Charging Transient

Gate charging transient analysis is important inunderstanding the switching speed of LDMOS as itreveals the behavior of input capacitance C iss (parallelcombination of C GS and C GD) [3]. It is desired to havehigh C GS for higher gate control and lower C GD for higher switching speed. Both of these requirements areexpected to be met in the HSG LDMOS since the

proposed device has thin gate oxide at the source endand thicker gate oxide at the drift region. Therefore,

gate charging experiment is conducted through mixedmode simulations in ATLAS device simulator. Thecircuit configuration used in the simulation is shown inthe inlet of Fig. 8, which has a constant current sourcecharging the gate. The width of the device is chosen to

be 10,000 m.

Fig. 9. Switching characteristics ofconventional and HSG LDMOS in an inverter

configuration.

Fig. 8 shows the gate charge analysis, the initial part of

the curve till the slope changes determines the C GS, andthe next part of the curve with lesser slope determinesCGD (miller capacitance). The charging time multiplied

by the constant current gives the charge per unit area. Itcan be seen from Fig. 8, that the gate charge (Q GS) of the HSG LDMOS and the conventional LDMOS are283 pC/mm 2 and 204 pC/mm

2 respectively. This isapproximately 39% improvement in the gate charge of the HSG LDMOS compared to the conventionaldevice. Similarly, the gate to drain charge (Q GD) of the

proposed device is 158 pC/mm 2 and for theconventional device, it is 172 pC/mm 2. This is a 9%reduction in the gate to drain charge.

3.4. Switching Delay

Switching speed of the LDMOS is calculated by theinverter configuration shown in the Fig. 9. The circuitis implemented using ATLAS mixed mode simulator.The device width is chosen to be 10 m. The delay iscalculated as the difference between input and output

pulse at 2.5 V (which is 0.5V DD). From Fig. 9, it can be seen that the switching delay of the HSG LDMOS isreduced by 38% compared to the conventional device.

4. Conclusion

In this paper, we have proposed a new LDMOSwith hetero-material stepped gate (HSG) for improved

performance. Using two dimensional numericalsimulations, the proposed device is demonstrated toexhibit improved breakdown voltage, drive current,transconductance, on-resistance, gate charge andswitching speed compared to the conventional device.These improvements have been realized without


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unduly increasing the fabrication complexity. The proposed device can be advantageously deployed for RF power applications.

5. References

[1] M. M. De Souza, G.Cao, E. M. S. Narayanan, F.Youming, S. K. Manhas, J. Luo and N. Moguilnaia,"Progress in Silicon RF Power MOS Technologies-Current and Future Trends.(Invited)," in Fourth IEEE

International Caracas Conference on Devices,Circuitsand Systems , Aruba, 2002, pp. D047-1-D047-7.

[2] J. G. Fiorenza and J. A del Alamo, "ExperimentalComparison of RF Power LDMOSFETs on Thin FilmSOI and Bulk Silicon," IEEE Transactions on Electrondevices , vol. 49, no. 4, pp. 687-692, Apr. 2002.

[3] T. Khan, V. Khemka, and R. Zhu, "IncrementalFRESURF LDMOSFET structure for enhanced voltage

blocking capability on 0.13um, SOI based technology,"in 20th International Symposium on Power Semiconductor Devices and IC's , Oralando, 2008, pp.

279-182[4] S. Linder, Power Semiconductors , 1st ed. Lausanne,Switzerland: EPFL Press, 2006

[5] M. M. De Souza, "Design for Reliability: The RF Power LDMOSFET," IEEE Transactions on Device and Material Reliability , vol. 7, no. 1, pp. 162-174, Mar.2007.

[6] ATLAS user's manual : Device simulation software . SantaClara, CA: Silvaco International, 2007.

[7] H. Xing, Y. Dora, A. Chini, S. Heikman, S. Keller and U.K. Mishra, "High Breakdown Voltage AlGaN-GaNHEMTs Achieved by Multiple Field Plates," IEEE

Electron Device Letters , vol. 25, no. 4, pp. 161-163, Apr.2004.

[8] J. A. Appeles and H. M. J. Vaes, "High Voltage ThinLayer Devices (RESURF Devices)," in IEDM Tech

Digest , 1979, pp. 238-241.

a new hetero-material stepped gate (hsg) soi ldmos for rf power amplifier applications

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