A New Low Power Flash ADC A New Low Power Flash ADC UsingUsing

Multiple-Selection MethodMultiple-Selection Method

Adviser: Dr.Hsun-hsiang Chen Presenter: Chieh-En Lo

ReferenceReference

Wen-Ta Lee; Po-Hsiang Huang; Yi-Zhen Liao; Yuh-Shyan Hwang;Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

20-22 Dec. 2007 Page(s):341 - 344 Digital Object Identifier 10.1109/EDSSC.2007.4450132

OutlineOutline

IntroductionModified flash adc architectureProposed multiple-selection for flash adcSimulation and experimental results

introductionintroductionTo reduce the power consumption for flash adc,

we propose a multiple-selection design method to reduce the number of comparators

Compared with the traditional 6-bit flash adc uses 63 comparators, our new proposed 6-bit modified flash adc architecture only uses 27 comparators therefore has smaller size and lower power consumption.

Modified flash adc Modified flash adc architecturearchitectureA. Comparator

Vin>Vref, Vout 1 Vout! 0

Vin<Vref, Vout 0 Vout! 1

Modified flash adc Modified flash adc architecturearchitectureB. 4-bit modified flash adc

Proposed multiple-selection for Proposed multiple-selection for flash adcflash adc

Simulation and experimental Simulation and experimental resultsresults