a novel low cost implementation of democratic sharing of paralleled converter modules

8/6/2019 A Novel Low Cost Implementation of Democratic Sharing of Paralleled Converter Modules

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A NOVEL, LOW-COST IMPLEMENTATION OF DEMOCRATICLOAD-CURRENT SHARING OF PARALLELED CONVERTER MODULESMilan M. JovanoviC and David E. Crow

DELTA Power Electronics Lab. , Inc.1872 Pra tt DriveBlacksburg, VA 24060

Abstract - A simple, low-cost, and robustdemocratic (autonomous) current-sharingcircuit is proposed and analyzed. The cir-cuit maintains good current sharing among themodules by properly adjusting the voltage ref-erences of the modules based on the differ-ences between the average current of the paral-leled modules and the currents of the individ-ual modules. Design guidelines for achieving adesired current-sharing performance are givenand verified on a number of dc/dc modules op-erating in parallel.

1 IntroductionGenerally, the paralleling of lower-power convertermodules offers a number of advantages over a single,high-power, centralized power supply. Performance-wise, the advantages include higher efficiency, betterdynamic response due to a higher frequency of opera-tion, and be tter load regulation. System-wise, paral-leling allows for redundancy implementation, expand-ability of ou tput power, and ease of maintenance. Infact, paralleling of standardized converter modules isthe approach that is widely used in distributed powersystems for both front-end and load converters.When operating converter modules in parallel, themajor concern is load-current sharing among the par-alleled modules. A variety of approaches, with dif-ferent complexity and current-sharing performance,were proposed, developed, and analyzed in the past[l] [8]. Among these approaches, the most attractiveare those which provide the desired current sharingwithout implementing a master/slave configuration orrequiring a separate current-share controller. Thesedemocratic (also referred to as autonomous [2] orindependent [SI) current-sharing approaches, whichallow each module to operate either as a stand-aloneunit or as a parallel module, make possible the imple-mentation of true N+ 1 redundant systems.

Generally, democratic current sharing can be im-plemented using two approaches. The first approach,known as th e droop approach [6, 71, relies on the in-ternal (output) and/or externally added resistance ofthe paralleled modules to maintain a relatively equalcurrent distribution among the modules. The droop

Lieu Fang-YiDELTA Electronics, Inc.3 Tung Yuan b a dTaoyuan, Taiwan, R.O.C.

method can be implemented in a variety of schemesas described in [7]. It is simple to implement, andit does not require any communication (control-wireconnection) between the paralleled modules. How-ever, the major deficiency of the droop method is apoor load regulation. As a result, the droop method isnot suitable for applications where a tight regulationis required.

The other method ensures the desired current shar-ing by adjusting the reference voltages of the voltage-feedback error amplifiers of the indiv idual modules sotha t t he deviations of the modules currents from theaverage current are eliminated [l ] [SI. This current-sharing technique requires a single-wire communica-tion (current-share bus) between the modules in or-der to provide the average current information to thecurrent-share circuits of each module. An implemen-tation of this current-share technique is described indetail in [5]. A modified circuit, which is used to im-plement an IC controller with current sharing functionis presented in [6].

Generally, the current-share-bus technique em-ploys an operational amplifier (current-error ampli-fier) in the low-bandwidth, current-share loop to gen-erate a current-error signal which is used to adjustthe reference voltage [2] - [6]. In add ition, it requiressensing of the load currents (or currents proportionalto the load currents) of the individua l paralleled mod-ules. To ensure the stability of the paralleled-modulesystem, the current-share loop gain has to be properlytailored [2], [3]. Otherwise, the system may exhibit in-stabilities, especially during load transients [8]. How-ever, even for a stable system, the operation of thistype of current-sharing circuit may not be satisfac-tory due to its high sensitivity to the noise. In fact,the implementation of the circuit requires very carefullayout and grounding considerations [SI.

In this paper, a novel implementation of thecurrent-share-bus technique is described. The mainfeature of the proposed implementation is tha t it doesnot employ the operational amplifier to generate thecurrent-error signal. As a result, th e circuit is inher-ently stable, robust, and cheaper to implement.

The paper also presents a detailed analysis of op-eration and design guidelines for achieving a desiredcurrent sharing. Finally, the proposed technique isverified on a number of experimental dc/dc modules

0-7 @B2 WW9 4/ 4.00 1994 IEEE 420


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YN

................ ....,

POWER STAGE

' -I POWER STAGEL

VOl1

I.S.BUS

Fig. 1: Parallel connection of two dc/dc modules which employ proposed current-sharing circuits. R!,, andR;, represent interconnect (cable) resistance between outputs of modules and load. If not stated otherwise, it-is assumed that RL =e R,,,.operating in parallel.

2 Implementation and Analy-sisThe parallel connection of two dc/dc modules whichemploy the proposed current-sharing (CS) circuit isshown in Fig. 1 . Instead of using an operational am-plifier to process the current-error signal [2] - [6], theproposed circuit employs a comparator followed by alow-pass filter (passive integrator) consisting of Rz,R3, nd C. Current source I s represents the sensedcurrent which needs to be proportional to the outputcurrent I o , i.e., I S = K s I o , where K s is the currentsensing gain. If sensing resistor Rs is much smallerthan R1 (Rs


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Fig. 2: Current-sharing circuits of two parallel mod-ules shown in Fig. 1. If not stated otherwise, it isassumed that C1 C2= C and V i = V i = VR.

the modules is achieved by comparing voltages acrossthe sensing resistors V i and V i in the CS circuitsof the individual modules with CS-bus voltage VCS,and by appropriately adjusting the output voltages ofthe modules so that the differences between voltagesV i and V j , and the CS-bus voltage are decreased tothe desired levels. The output voltages are adjustedby voltages across capacitors C and C2,which effec-tively change reference voltages V i and V i accordingto the duty cycle of the comparator-output voltages

Voltages V and V i are proportional to the cor-responding load currents, while the CS-bus voltage,according to Fig. 2 , is

VEom and VZom.

i.e., it is proportional to the average of the outputcurrents of the individual modules. Therefore, thecurrent-sharing circuit tries to maintain the outputcurrents of individual modules equal to the average ofthese currents. This conclusion can be generalized forany number of modules in parallel.

Figure 3 shows the key steady-state waveforms ofthe CS circuit of two identical modules. Since themodules are identical, they are expected t o share theload current perfectly. As can be seen from Fig. 3, themodules carry equal average output currents. How-ever, their instantaneous output currents are differ-ent ; i.e., the output-current waveforms contain 180out-of-phase ac components. These ac current com-ponents are induced by the CS loop due to the in-evitable ripple of the capacitor voltages v h and vNamely, when the comparator outputs in the CS cir-cuits are high, capacitors C and C2 are chargedthrough R3 with time constant T&ar = CR3. Sim-ilarly, when the comparators outputs are low, thecapacitors discharge through R2 with time constantTdisehar = C(R211R3).The changes in capacitor volt-

Fig. 3: Key waveforms of two identical (V i = V i =VR )parallel modules shown in Fig. 1 with relativelysmall capacitors C and C2 (C = C2= C).ages v i and v g induce changes in the output voltagesof the modules, v h and U;, which cause changes inoutput currents ib and ib.For the twemodule parallel connection, compara-tor outputs must be in the opposite states (i.e., if v~,,is high, vZom must be low, and vice versa) because forone comparator the voltage across the sensing resistor(output current) must be higher than the CS-bus volt-age, whereas for the other this voltage must be lowerthan the CS-bus voltage. The comparators changestates when the instantaneous currents of the indi-vidual modules become equal to the average currentof the modules. If the modules are identical, the dutycycles of comparator output voltages viom and v&,,are 50%. Generally, for any number of modules inparallel, at any given time, at least one of the com-parators must be in the opposite state than t he others.= Vc as afunction of the duty cycle of the comparator out-put can be calculated from the equivalent charg-ingldischarging circuit shown in Fig. 4 as

The average capacitor voltage

where DCS is the duty cycle of the comparator out-put voltage and VF s the forward voltage drop of the

Fig. 4: Equivalent chargingldischarging circuit.

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1vc [V

0

" 0 0.2 0.4 0.6 0.8 1Dc sFig. 5: Plot of Vc as function of D .

diode.Figure 5 shows the plot of VCas a function of DCS.As can be seen, for small duty-cycle changes aroundDcs = 0.5, the Vc dependence on DCS is virtuallylinear for all R3/R2 ratios. For duty cycles higher

than 0.7 and R3/R2 2 5, Vc increases rapidly towardthe reference voltage (VR= 2.5 V ). Finally, i t shouldbe noted that ratio R3/R2 has no effect on Vpaz=VR that occurs for Dcs = 1, but only on V?'" thatoccurs at Dcs=O. A smaller R3/R2 ratio increasesthe V p n alue, and therefore decreases the Vc range.Furthermore, from Fig. 2, it can be derived thatthe output voltage of the module is dependent on theaverage capacitor voltage as

As can be seen from Eq. ( 3) , voltage Vc effectivelychanges the reference voltage of the voltage-feedbackerror amplifier. From Eqs. (2 ) and (3) , the adjust-ment range AVO of Vo, assuming that R3 >> R2,is

AVO = ,Fa,- G in= VO(@V,"'") - Vo(@Vcmaz)

(4)Switching frequency fcs of the comparators in theCS circuits, and therefore, also the ac component fre-quency in the output voltage and current waveforms,

is determined by the frequency of the closed-loop com-plex poles of the output filter of the power stage. Tofacilitate the explanation of this claim, Fig. 6 showsthe small-signal, block diagram of a module with theCS circuit.In the circuit in Fig. 6 , th e CS circuit is modeled bya voltage source th at represents the voltage waveformof the capacitor in the CS circuit. The ac componentof this voltage source serves as the excitation signal tothe close-loop circuit consisting of the error amplifier

POWER STAGE .

Fig. 6: Small-signal blockcurrent-share circuit.

&---diagram of module with

(E/A), PWM modulator, power stage, and voltagedivider (R 5 and R4 ) , which represents the output-voltage feedback loop. It should be noted that, gen-erally, the PWM modulator can be of a current-modetype.According to Fig. 6 , a change in v c (due to un-avoidable charging or discharging of C) will producea response in outpu t VOa t the frequency of the closed-loop complex poles of the power stage. As a result,the comparator in the CS circuit will switch at thesame frequency. Generally, this frequency depends onthe open-loop frequency of the complex poles of thepower stage and the amount of feedback (E/A gain)and can be determined from the root locus plot of thevoltage feedback loop.

Finally, Fig. 7 shows the key waveforms of the par-allel connection of the two modules with the mis-matched reference voltages (i.e., V i > V i ) .As can beseen, the frequency of the ac current and voltage com-ponents is the same as for the case of equal references(Fig. 3). However, the duty cycles of the comparatorsare not equal. As a result, the average voltages of C'and C2 are different, i.e., V i > Vz .2.2 Accuracy of current sharingAs illustrated in Fig. 3, the current sharing of twoidentical modules is, as expected, perfect. However,the modules which are not identical exhibit a current-sharing error, as can be seen in Fig. 7 for moduleswith slightly mismatched reference voltages. Namely,the difference in the reference voltages (or, generally,any other source of mismatching) calls for differentaverage voltages of capacitors C' and C2 to correctthe mismatching. To obtain the required average ca-pacitor voltages v&~, , ) and v& ~ , , ) , the duty cycle ofcomparator voltage vEom must be different than thatof &,,, . Since the comparators compare the instanta-neous load currents of the individual modules with theaverage current of the modules, the only way to gen-erate different duty cycles is to have the current wave-forms shifted in the opposite directions with respect

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Fig. 7: Key waveforms of two parallel modules withmismatched references ( V i> V i ) nd relatively smallcapacitors C' and C2 C'= C2 C).

to th e average current of the modules. If V1> V i , hehas to move up for the same distance with respectto the average current level of ICS = ( I A+ I6)/2 ascan be seen from Figs. 3 and 7. Since the ac com-ponents of the o utpu t voltages are vA = Rhi& andv g = Riig , where Rh = R% = R, are the resis-tances of the cables connecting the individual outpu tswith the load as shown in Fig. 1 , the output voltagesalso shift with respect to each other, as can be seenfrom Fig. 7. The shifting of the waveforms not onlyintroduces a difference in the duty cycles of the com-parators, bu t also introduces a difference between thedc components of individual ou tput currents, i.e., cre-ates a current-sharing error. This error is smaller ifthe ac components of the individual output currentsare smaller. Since, according to Fig. 6, the magnitudeof the ac output-current component is proportionalto the magnitude of the ac component of capacitorvoltages U& and v: , the current-sharing error can becontrolled by proper selection of the capacitor values.Generally, larger values of C' and C2 re required forhigher accuracy.

Figure 8 shows the waveforms of the same two mod-ules as in Fig. 7, but with larger capacitors C' =C2 C. s can be seen, the ac components of capac-itor voltages U& and v: are very much reduced. Asa result, the ac components of the output currents,and consequently, the current-sharing error are alsoreduced compared t o Fig. 7.

I; waveform has t o move up, and the I s waveform

2.3 StabilityDue to th e presence of th e comparator in the CS loop,the CS loop is inherently sta ble if the voltage-feedbackloop is stable within the range of the effective voltage

Fig. 8: Key waveforms of two parallel modules withsame mismatched references (V i > V i )as in Fig. 7and five times larger capacitors C' and C2 C' =C2 C) compared to those in Fig. 7.

reference change. Namely, according to Fig. 6 , themagnitude of the ac component of the output cur-rent (voltage) is dependent on the gain of the voltage-feedback loop and the magnitude of the ac componentof capacitor voltage vc . Since the magnitude of theac component of vc is bounded and independent ofthe CS loop gain, it follows that the magnitude of theac component of the output current is proportionalto the magnitude of the ac component of v c , if thevoltage-feedback loop is stable . As pointed out ear-lier, the magnitude of the output current ac compenent can be controlled by properly selecting chargingTchor and Tdisch time constants.

2.4 Effect on output voltageAs shown in Fig. 3, when two identical modules areconnected in parallel, their effective reference volt-ages will change for the same amount because theCS-loop comparators will switch with 50% duty cy-cle. Therefore, the output voltages of the modulesafter paralleling will stay equal but will assume dif-ferent values than before paralleling. As a result, theload voltage will also change due to the paralleling.Whether the output voltages after paralleling will behigher or lower than before paralleling depends on theoutput-voltage adjustment procedure before parallel-ing. If the out put voltages are adjusted while the CSbus is held low, the output voltages will increase af-ter the paralleling. If the CS bus is held high duringthe output-voltage adjustment , the output voltageswill decrease after the paralleling. To help explainthis claim, Fig. 9 shows the load regulation curvesof two identical modules for the above-mentioned ad-justments of the out put voltage. The separation of

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aftervb +7aralleling

Fig. 9: Load regulation lines for two identical mod-ules before and after paralleling. For clarity, lines areshown slightly apart, although for identical modulesthey actually coincide.

the curves before paralleling AVO for the adjustmentswith low and high VCS can be calculated from Eq.(4). Since the modules are identical, the correspond-ing curves for both modules coincide with each other.When the modules are connected in parallel, capaci-tor voltages V i and V i change for the same amountdue to 50% duty cycle operation, causing the outpu tvoltages to shift equally from their values before par-alleling, as shown in Fig. 9.

As can be seen from Fig. 5 , Vc at Dcs=O.5 is onlyslightly different than Vc at Dcs=O if R3/R2 >> 1,i.e., when VCS is held high. However, VC at Dcs=O.5is much lower than Vc at Dcs=l , i.e., when VCS isheld low. As a result, the shift of the output voltagesafter paralleling is smaller if the adjustment is donewhen the CS bus is held high and the ratio R3/Rzis selected to be high (2 0) . This is seen clearly inFig. 9, where the load regulation lines of the modulesafter paralleling are closer to the regulation lines tha tcorrespond to the adjustment with the CS bus heldhigh.

This conclusion can be generalized for any numberof modules in parallel. Of course, the voltage shift de-pends on the number of modules, adjustment proce-dure, and the output-voltage adjustment range givenby Eq. (4). Generally, the voltage shift decreases asthe number of modules increases.

3 Design GuidelinesThe design of the CS circuit requires a proper selec-tion of resistors Rs ,RI ,R2, and R3 and of capacitorC.The value of Rs is determined by the choice of thesensing network and its gain. While the resistive sens-ing is a viable approach to sensing low currents, thetransformer sensing is a more practical approach to

sensing larger currents. In fact, for modules that em-ploy a current-mode control, the existing current sens-ing device can be also used for the CS loop sensing.To avoid the dependence of the sensed voltage V . onthe value of RI ,RI should be selected much largerthan Rs. A good choice is to select RI ten t o twentytimes larger tha n Rs. Finally, it should be noted th atRs and RI need to be high-precision (small tolerance)resistors since the differences in their values affect theaccuracy of current sharing.

Resistors Rz and R3, for given voltage divider re-sistors & and Rs , set the range of the output volt-age. This range must be within the specified regula-tion range, V" - V z a s of the modules. Assumingthat R3 >> R2 and tha t the adjustment range of theoutput voltage is equal to the regulation range, i.e.,AVO = VZaZ-V g i n ,R3 can be calculated by solvingEq. (3 ) as

To satisfy R3 >> R2, R2 should be selected at least10 times smaller than R3.With the above calculated values for resistors R2and R3, the CS circuit can maintain the desired cur-rent sharing for mismatched modules whose outputvoltages before paralleling are within the specified reg-ulation range when their CS-bus lines are held low, aslong as the cable resistances tha t connect the outp utsof individual modules to th e load (R, n Fig. 1 ) arethe same. Otherwise, this range can be smaller orlarger, depending on the cable resistance differences

As described in Sec. 2.2 , the value of capacitor Cdetermines the accuracy of the current sharing. Gen-erally, higher values of C result in better current shar-ing. However, the trans ient response of the CS loopbecomes slower as the value of C is increased. As aresult, the dynamic current-sharing performance maydegrade for excessively large values of C. Therefore,the minimum value of C which meets the desired ac-curacy spec should be taken. To determine this valueanalytically, it is necessary to know the closed-loopgain of the voltage-feedback oop at the current-shareloop frequency. Without resorting to the computa-tion of this gain, a good rule-of-thumb value for thecapacitor selection is tha t t he capacitor voltage peak-to-peak ripple should be kept below 1%of the dc levelto achieve current-sharing accuracies of around 1%.

Finally, the selection of the comparator in the CScircuit does not require any special considerations.Since the CS loop is a slow loop, the compara tor speedis not criti cal, and therefore, a cheap, all purpose com-parator can be used. In fact, to further reduce thecomponent count, an open-collector comparator with-out a pull-up resistor can be used. The operation ofthe CS circuit is identical with that with the compara-tor with a pull-up resistor, except that the comparatoroutput voltage vcom in the high stat e follows the ca-

PI.

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1vmvcom2

1

2' 0

' 0

Fig. 10 : Oscillograms of key waveforms of two exper-imental modules connected in parallel with identicalreferences Vi = Vi = 2.5 V and C' = C2= C = 330nF at vin = 48 V and I L = 10 A . Scales: v,,,,, - 1V/div; vc 50 mV/div; Io - 0.1 A/div.

pacitor voltage instead of being pulled up all the wayto the rail voltage. Lastly, since the comparator doesnot have any hysteresis, it requires a filter at the in-put terminals to eliminate false triggering due to thenoise.

4 Experimental EvaluationTo evaluate the performance of the proposed CS cir-cuit, three identical experimental 5V/15A1 dc/dc for-ward converters operating at 300 kHz were built forthe input voltage range from 40 V to 60 V. The follow-ing components for the CS and the voltage-feedbackcontrol circuits, according to labeling in Fig. 1, wereused: Rs = 0.1 K , R1= 1 K , R 2 = 4 .3 K , R3 = 100K , C=220 nF , & = Rs = 10 K , Z I = RI = 1 K ,and Z F B = CFB= 22 nF. The values of the majorcomponents of the power stage are: turns ratio of thetransformer N=2.5, filter inductor L F = 15 pH, andCF = 4700 pF. The control was implemented usingthe current-mode controller UC3825. The informa-tion about the o utput current was obtained indirectlyby measuring the primary current. The sensing wasdone by using the same current transformer which wasused to implement the current-mode control.

Figure 10 shows the oscillograms of the key wave-forms of two experimental modules connected in par-allel. As can be seen, the frequency of the current-share loop is around 500 Hz, which represents thefrequency of the closed-loop complex poles of thepower stage (note that natural undamped frequencyof open-loop complex poles of the power stage isfo = l / d m = 600 Hz. The waveforms in Fig. 10are in good agreement with those in Fig. 3 except thatin th e oscillogram, the crossovers of the load-current

waveforms occur before the moments the comparatorschange states. This is caused by the delay introducedby an RC noise-filtering network at the input of thecomparators. With reference to Fig. 2, thi s filter con-sists of resistor R, = 10 K , connected in series withthe positive input of the comparator and capacitorC n = 10 nF, connected right across the comparatorinput terminals.Table 1 summarizes the current-sharing measure-ments for two paralleled modules with mismatchedreferences ( V i = 2 .5 VI Vi = 2.45 V) without andwith the current-sharing circuits connected. As can beseen, the CS circuit dramatically improves the load-current distribution among the modules. T he relativecurrent-sharing error , lI&dc) - :(dc) l / ( I ~ / 2 ) , whenthe CS buses are not connected is in the 20% to 135%range, depending on the load current. With t he CS -busses connected, the current-sharing error decreasessignificantly. For C1= C2 = 330 nF, the current-sharing error reduces to 7.2% at light load ( I L=5 A)and to 0.8% at full load ( I L =30 A) . As explainedearlier, larger values of C1 C2 decrease the ac com-ponents of the output currents (I&(ac), and,consequently, give bet ter current-sharing accuracies.For C' = C2= 1. 5 pF , the current-sharing accuracyis better than 1% in the entire load range. At the sametime, the measurements of the dynamic current shar-ing during large load transients (from 10% to 100%)showed no noticeable increase in the current-sharingerror.

Finally, Table 2 summarizes the experimental re-sults for a parallel connection of three experimen-tal modules with the mismatched reference voltages(Vi - 2.5 V, Vi = 2.475 VI and Vi = 2.45 V).As in the case of two paralleled modules, the CS cir-cuit dramatically decreases the current-sharing error.Without the CS buses connected, the current-sharingerror is in the 26% to 176% range. However, whenthe CS busses are connected, the current sharing er-ror reduces to 10.4% at light load ( I L =7.5 A ) andto 2.2% at full load ( I t =45 A). It should be notedthat in the entire load range, the maximum absolutecurrent-sharing error maxlI;(,,) - &(,c) is less than330 mA.

The larger relative current-sharing errors in thethree-module parallel connection compared to thosein the two-module connection are caused by small dif-ferences in the power stage paramete rs of Module #3compared to th e other modules. Namely, as pointedout earlier, in the experimental converters, the mea-surements of the output currents were done indirectlyby sensing the primary currents. As a result, anymismatching of the power stage parameters such as,for example, transformer magnetizing inductance andturns ratio and/or efficiency, introduces errors in theoutpu t currents of the modules. If the output currentsare directly measured, the differences in the powerstage parameters do not affect the accuracy of thecurrent sharing.

R. -

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Table 1: Measured current-sharing performance of two paralleled experimental modules with mismatched refer-ences ( V i =2.5 V , V i =2.45 V). Relative current-sharing error in % is defined as [ l I & d c l - I & d c ) l / ( I ~ / 2 ) ] 1 0 0 % .

Table 2: Measured current-sharing performance of three paralleled experimental modules with mismatchedreferences (V i =2.5 V , V i =2.475 V, V i =2.45 V). Relative current-sharing error in % is defined as [maxII&) - &) I/(IL/3)1100%.

5 SummaryA simple, low-cost, and robust democratic current-sharing circuit is proposed and analyzed. Detailedexplanations of operation, current-sharing accuracy,current-sharing loop stability, and the effect on theoutput voltage of the proposed circuit are presented.The current-sharing performance of the proposedscheme is evaluated experimentally on the parallelconnection of two and three, 5V/15A, forward con-verter modules.

AcknowledgementThe authors wish to thank Mr. Andrk S. Kislovski ofAscom Hasler L td., Berne, Switzerland, for providingcopies of references [2] and [3].

ReferencesPI M. Grossoni, F . Molinari, Some special devicesused in the new type of power plants for the

Italian telecommunication systems, IEEE In ter-national Telecommunication Energy Conf. Proc. ,pp. 401-404, 1979.

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A S . Kislovski, About uninterruptible dc powersupplies, HASLER Kurzbenchte , pp. 63-70,1981.AS . Kislovski, On uninterruptible dc powersupply systems, Third IFAC Symposium onControl in Power Electronics and ElectricalDrives Proc . , pp. 691-696, 1983.M. Grossoni, G. Cimador, A selective supervi-sion device for paralleling operating ac/dc anddc/dc converters, IEEE International Telecom-munication Energy Conf Proc. , pp. 587-593,1983.K.T. Small, Single wire current share parallelingof power supplies, U.S. P a te n t 4,717,833, 1988.M. Jordan, Load share IC simplifies power sup-ply design, High-Frequency Power ConversionConf. Proc . , pp. 65 76 , 1991.C. Jamerson , C . Mullett, Paralleling suppliesvia various droop methods, High-FrequencyPower Conversion Conf Proc . , pp. 68-76, 1994.I. Baterseh, K. Siri, J. Banda, An alter-native approach for improving current-sharingin parallel-connected dc-dc converter systems,High-Frequency Power Conversion Conf. Proc. ,pp. 102-119, 1994.

a novel low cost implementation of democratic sharing of paralleled converter modules

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