a novel progressive trigger method of di/dt control for mosfet

A novel progressive triggermethod of di/dt control forMOSFET

Jiangping Hea), Bo Zhang, Gao Pan, and Qing HuaState Key Laboratory of Electronic Thin Films and Integrated Devices,

University of Electronic Science and Technology of China, Chengdu 610054, China

a) [email protected]

Abstract: A novel progressive trigger (PT) method of di/dt control for

MOSFET is presented in this paper. The principle of the proposed method

is based on the progressive trigger current during ON and OFF states by

variable channel width for MOSFET. The experimental results show that

the di/dt reduces from 105mA/nS to 57mA/nS for OFF state, and from

110mA/nS to 86.7mA/nS for ON state with RON = 0.5Ω and Vgg = 3V.

The flexibility of the method is easy to implement in integrated circuits.

Keywords: progressive Trigger, di/dt control, gate driver

Classification: Integrated circuits

References

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© IEICE 2016DOI: 10.1587/elex.12.20151006Received November 26, 2015Accepted December 7, 2015Publicized December 18, 2015Copyedited January 25, 2016

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LETTER IEICE Electronics Express, Vol.13, No.2, 1–9

http://dx.doi.org/10.1109/63.285504

http://dx.doi.org/10.1109/63.285504

http://dx.doi.org/10.1109/63.285504

http://dx.doi.org/10.1109/63.285504

http://dx.doi.org/10.1109/15.544311

http://dx.doi.org/10.1109/15.544311

http://dx.doi.org/10.1109/15.544311

http://dx.doi.org/10.1109/TPEL.2010.2047734




http://dx.doi.org/10.1109/PESC.1998.703241





http://dx.doi.org/10.1109/63.388004

http://dx.doi.org/10.1109/63.388004

http://dx.doi.org/10.1109/63.388004





http://dx.doi.org/10.1109/TIA.2003.810654









http://dx.doi.org/10.1109/ECCE.2010.5617892














http://dx.doi.org/10.1587/elex.12.20150189




[14] W. Zhiqiang, S. Xiaojie, L. M. Tolbert and B. J. Blalock: IEEE APEC 21(2013) 1266. DOI:10.1109/APEC.2013.6520462

[15] J. E. Makaran: IEEE Trans. Power Electron. 25 (2010) 1339. DOI:10.1109/TPEL.2009.2037905

[16] T. Shimizu and K. Wada: IEEE ICPE’07 (2007) 857. DOI:10.1109/ICPE.2007.4692507

[17] H. Riazmontazer and S. K. Mazumder: IEEE Trans. Power Electron. 30 (2015)2338. DOI:10.1109/TPEL.2014.2327014

[18] Z. Ivanovic, B. Blanusa and M. Knezic: ICAT’11 XXIII Int. Symp. (2011) 6.DOI:10.1109/ICAT.2011.6102129

[19] W. Eberle: Ph.D thesis Queen’s University Kingston, Ontario, Canada (2008).

1 Introduction

Since MOSFETs can switch at a high frequency with very low conduction

resistance, it has been one of the best choices for the power transistors in most

portable applications. However, since MOSFETs usually induce high di/dt and

dv/dt during the switching commutation transient, the systems may suffer from

electromagnetic interference (EMI) issues [1, 2]. Therefore, it is critical to control

the di/dt and dv/dt of the MOSFET.

The traditional methods of di/dt control for MOSFETs mostly focus on the

adjustment of the Vgs slope during the MOSFET switching transient [3]. The

product of gate resistor (Rg) and the parasitic capacitor of gate-drain (CGD), gate-

source (CGS) (RgðCGD þ CGSÞ) is used to control the Vgs increasing or decreasing

speed [4]. An adjustable gate resistor (Rg) or the gate capacitor [5, 6, 7, 8] is

provided to control the Vgs slope during MOSFET switching transition. The rising

and falling speed of Vgs can be controlled by setting the maximum gate-driven

voltage to different values during the device’s switching transition [9, 10]. A close

loop gate driven method is applied for power MOSFET to increase or decrease the

speed of Vgs [11, 12, 13, 14, 15, 16, 17], in which a feedback circuit is used to sense

the device voltage or current slopes for the gate-driven circuit.

A novel progressive trigger (PT) di/dt control method is presented in this paper,

which is based on the variable channel width to handle the di/dt of MOSFETs

ON/OFF behaviors. The theory, operation, and circuits of the proposed methods

will be discussed in the following.

2 The proposed progressive trigger method

Based on the MOSFET operation investigation, the proposed PT di/dt control

method is based on the drain-source current Ids(t) expression shown as:

IdsðtÞ ¼ K½VgsðtÞ � Vth�2 �WðtÞ ð1Þwhere Ids(t) is the MOSFET drain-source current, K ¼ �nCOX =L, �n is the N-

MOSFET carrier mobility, COX is the gate capacitance per area, L is the device

channel length, Vth is the MOSFET threshold voltage, Vgs(t) is MOSFET gate-

source voltage, and W(t) is a new variable, which indicates the variable channel

width of the MOSFET.


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IEICE Electronics Express, Vol.13, No.2, 1–9

http://dx.doi.org/10.1109/APEC.2013.6520462









http://dx.doi.org/10.1109/ICPE.2007.4692507








http://dx.doi.org/10.1109/ICAT.2011.6102129




To simplify the proposed PT method implementation in integrated circuit, the

continuous time variable W(t) is discretized as Wm. The proposed PT method is

illustrated in Fig. 1, where the main power MOSFET is divided as M1�Mn sub-

MOSFET, the width of the whole power MOSFET equals the sum of W1�Wn.

When the power MOSFET turn-on signal is valid, the M1�Mn would be turned on

sequentially with a proper time sequence. Fig. 2 shows the power sub-MOSFET

M1�Mn turn on/off timing chart, the turn on/off delay time is TD between the

adjacent devices, and the total channel width of the MOSFETs is increasing or

decreasing linearly with time.

Fig. 1. The discretized PT method diagram. (A) The whole equivalentcircuit of PT method with Wtotal ¼ W1 þ . . . þWn. (B)Equivalent circuit for each sub-MOSFET.

Fig. 2. The timing chart of the discretized proposed PT method. Thereis a delay time TD between the adjacent sub-MOSFET duringON/OFF.


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The proposed PT di/dt control method operation is shown as Fig. 3, in this

graph, the operating procedure of the sub-MOSFET M1�Mn is described. The idsZoom In graph is shown in Fig. 4 for the PT method during the MOSFET ON/OFF

state. Take M1 as an example (Characterized with blue line in Fig. 3/4), the

detailed behaviors of proposed method during on/off transient is analyzed in the

following.

During the device turn-on event, the first MOSFET M1 gate-source voltage

(Vgs1) is charged by Vgg through Rg1, the drain-to-source current (Ids1) keeps the

leakage current until the gate voltage Vgs1 is higher than the threshold (Vgs1 > Vth),

then the ids1(t) can be expressed as equation (2) with Vgs1 rising slowly because of

the gate charge current through Rg1 while M1 drain-source voltage (VDSM1) keeps

constant. As time increases, Vgs1 rises further, and other MOSFET start to conduct,

the total current of Ids1�n ≧ IDSMAX1 (MOSFET ON state Maximum current). The

VDSM1 then begins to decrease while Vgs1 keeps constant (due to the miller effect of

drain-gate capacitor of M1) until VDSM1 reaches the minimum value, which is

determined by the product of the power MOSFET conduction resistance RDSON1�nand the IDSMAX1. Then M1 operates in deep linear region with fully ON state.

During turn-off event, the last device that turns off is M1. At first (T5�T6), the Rg1

discharges Vgs1 to the logic low while the device drain to source current keeps

constant. In this interval, only the RDSON1 of this device is increasing over time until

the Ids total (total current) = IDSMAX2. Then the Vgs1 of M1 keeps constant with the

VDS rising quickly approximate to VO (Output voltage). In the third turn-off stage,

the Vgs1 shows a continuously decrease by the Rg1 discharge current to logic low

level with Ids1 falling behavior. Within the last turn-off stage, the Vgs1 is less than

Vth, and all the MOSFETs conduct only leakage current.

Fig. 3. The PT method switching behavior. Where T1 to T4 is ON state,T1 to T2 is turn-on interval, T2 to T3 is miller region; T3 to T4 isfully on region. And T5 to T8 is OFF state, the sub-interval isinversely to ON state.


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After the delay time TD, the second MOSFET M2 works with a similar

operating behavior to M1, the difference is only a delay time TD between each

other. All the others MOSFETs operate in a similar mode. Equations (2) and (3)

provides the expression of power MOSFET Mm drain-source current (idsm(t)) and

gate-source voltage (Vgsm(t)).

idsmðtÞ ¼ 0 VgsmðtÞ < Vth; 1 � m � n

idsmðtÞ ¼ K½VgsmðtÞ � Vth�2 �Wm VgsmðtÞ � Vth; 1 � m � n

ids totalðtÞ ¼XNm¼1

idsmðtÞ N ¼ mint

TD

� �; n

� �

8>>>>><>>>>>:

ð2Þ

where, ids total(t) is the total drain-source current of MOSFETs M1 to Mn, Wm is the

m MOSFET’s channel width.

VgsmðtÞ ¼ 0 t � ðm � 1Þ � TD; 1 � m � n

VgsmðtÞ ¼ Vggf1 � e�½t�ðm�1Þ�TD�=Rgm�ðCGDmþCGSmÞg t > ðm � 1Þ � TD; 1 � m � n

�

ð3Þwhere, Rgm is the m device gate resistor, CGDm, CGSm are the m device gate-drain,

gate-source parasitic capacitor separately, Vgg is gate driver logic high voltage, TD

is the delay time between adjacent MOSFETs.

Therefore, based on (2) and (3), the di/dt of the power MOSFET can be

expressed by

didsmðtÞdt

¼ 0 t � ðm � 1Þ � TD; 1 � m � n

didsmðtÞdt

¼ ½VgsmðtÞ � Vth� 2KVgg

RgmðCGD þ CGSÞe�½t�ðm�1Þ�TD�=RgmðCGDmþCGSmÞ �Wm

t > ðm � 1Þ � TD; 1 � m � n

dids totalðtÞdt

¼XNm¼1

didsmðtÞdt

N ¼ mint

TD

� �; n

� �

8>>>>>>>>>><>>>>>>>>>>:

ð4Þ

Compared with the conventional RC gate-driven di/dt control method, two

additional control parameters, Wm and TD, appear in the proposed PT di/dt control

techniques shown in (4). If setting n � TD equals to the power MOSFET on/off

time of the traditional RC gate-driven control method, the di/dt of the proposed PT

method is reduced to 1/n of the conventional one at the Vgs1 ≧ Vth. The reason is

that only M1 provides conduction current for the power MOSFETs. As the other

sub-MOSFETs turned on and the di/dt is added to the previous value with the turn-

on time increasing, the di/dt of the whole power MOSFET is rising quickly. After

Fig. 4. The ids Zoom In behavior for the PT method during ON/OFFstate.


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all the n sub-MOSFETs is turned on, the di/dt reaches the maximum, which is

approximate to one of the traditional RC gate-driven method. Therefore, the di/dt

of proposed PT method is reduced significantly, especially during first interval of

the MOSFET turn-on transition.

Similar to the turn on procedure, the di/dt for the power MOSFET turn off

transition will get manifest improvement by appropriate selection of the parameters

TD and n. The switching behavior is inversely to the turn-on transition shown

as Fig. 3.

From Fig. 3/4, it can be seen that, compared with the traditional RC gate-

driven method, the proposed PT method will increase the power MOSFET switch

transition time. This method will affect the conduction loss of the power MOSFET

at the instant it is turned on/off. According to reference [18], the formula for power

increment is the following:

�Pswitching ¼ k � ð�TON � IDSMAX1 þ �TOFF � IDSMAX2Þ � VO � fSW ð5Þwhere �TON and �TOFF are the switch time increment during the MOSFET turn-

on/off event, respectively, IDSMAX1 and IDSMAX2 are the MOSFET maximum

current during turn-on/off event, VO is the output voltage, fSW is the MOSFET

switching frequency. Constant k is in the range between 1/6 and 1/2 [19].

From formula (5), the power increment is proportional to the increment of turn-

off and turn-on time. This has little effect on the overall efficiency due to the fact

that the time increment in this proposed method is minor (which is in the nano-

second level). This can be confirmed in the following test results.

3 Experimental results and discussion

In order to make a fair comparison on the power MOSFET di/dt performance

during switching transient, both the proposed PT control method and the conven-

tional RC gate-driven circuit have been applied to design an asynchronous boost

converter. The only difference of these two boost converters is that the power

MOSFET is divided by n ¼ 1=3 with the proposed PT di/dt control method, while

the others remain almost the same. When n ¼ 1, the proposed PT method shows the

same control structure as the conventional RC gate-driven method. The measure-

ment is setting up as Fig. 5, in this circuitry, MN is the power MOSFET with 0.5Ω

on resistance, SW is the drain node of this device. Fig. 6 shows the chip micro-

graph of the boost converter with n ¼ 3 of the proposed PT di/dt control method.

Fig. 5. Measurement setup of the designed boost converter.


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The power MOSFET dynamic characteristics test has been carried out to

evaluate the di/dt performance of the proposed PT control method. During the

OFF state, the drain-source voltage (VSW) and the drain-source current (IMN) are

shown in Fig. 7, it is clearly noticeable that di/dt of the power MOSFET is reduced

from 105mA/nS (Fig. 7B) to 57mA/nS (Fig. 7A) by the proposed PT technique.

During the ON state, the VSW and IMN are shown in Fig. 8, the di/dt

decreases from 110mA/nS (Fig. 8B) to 86.7mA/nS (Fig. 8A) by the proposed

PT control method.

Fig. 6. Micrograph of the designed boost converter.

(A) MOSFET OFF state di/dt with n=3 (B) MOSFET OFF state di/dt with n=1

Fig. 7. MOSFET OFF state di/dt with the Proposed PT method atVgg ¼ 3V. When n ¼ 1, which indicates the conventional RCgate-driven results; when n ¼ 3 is the proposed PT methoddi/dt test results.

(A) MOSFET ON state di/dt with n=3 (B) MOSFET ON state di/dt with n=1

Fig. 8. MOSFET ON state di/dt with the Proposed PT method atVgg ¼ 3V. When n ¼ 1, which indicates the conventional RCgate-driven results; when n ¼ 3 is the proposed PT methoddi/dt test results.


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From the test waveform in Fig. 7/8, it can be seen that, compared to traditional

RC gate-driven circuit, the proposed PT method increases the power MOSFET

turn-off time from 22 nS to 26 nS and the turn-on time from 10 to 12 nS. Mean-

while, since the switching loss accounts only a small part in the total power loss,

so the proposed method effect to the overall efficiency is nearly zero. Compared to

the traditional RC circuit, the efficiency of the proposed PT method decreases from

85.6% to 85.2% under the same testing conditions as in Fig. 7/8. The 0.4%

efficiency difference has little or no effect in practical application.

At different Vgg voltages, the di/dt characteristics of the proposed PT method

and that of the conventional RC gate-driven approach are also compared. Fig. 9 and

Fig. 10 illustrate a comparison of the OFF/ON state di/dt with Vgg at 3V, 3.6V,

and 5V.

Fig. 9 and Fig. 10 shows that the PT di/dt control method always keeps the

di/dt less than that of the conventional RC gate-driven approach, whether it is

during MOSFET OFF or ON state. Otherwise, when the Vgg increases, the di/dt

performance improvement by the PT control method is getting weak because of the

growing influence caused by MOSFET Vgs.

Fig. 9. di/dt VS Vgg during OFF state.

Fig. 10. di/dt VS Vgg during ON state.


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4 Conclusion

This paper presents a novel progressive trigger method of di/dt control to reduce

the MOSFET drain-to-source current slope during switch transition. The approach

is implemented by dividing the whole power MOSFET into n aliquot, which is

triggered successively with TD delay time. The performance is verified by an

integrated boost converter chip fabricated with 0.5-µm CDMOS process. And the

measurement results show that the MOSFET’s di/dt decreases from 105mA/nS to

57mA/nS for OFF state, and from 110mA/nS to 86.7mA/nS for ON state. This

shows that the proposed approach can obviously improve the di/dt performance of

the power MOSFET.


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a novel progressive trigger method of di/dt control for mosfet

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