A Pipelined SAR ADC Reusing the Comparator asResidue Amplifier

Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon and Nan SunDepartment of Electrical and Computer Engineering

University of Texas at Austin, Austin, TX 78712, USAEmail: mfgandara@utexas.edu, nansun@mail.utexas.edu

Abstract—This paper presents a 12-bit two-stage SAR-basedpipelined ADC that reuses the comparator from the first-stageSAR to perform residue amplification. This enables residue am-plification without increasing the hardware complexity comparedto a traditional SAR. The proposed amplifier utilizes positivefeedback to achieve a large gain at high speed, which can bedifficult to achieve with other dynamic amplifier topologies. Sincethe comparator is reused for amplification, no additional offsetcalibration is required to limit the input swing of the amplifier.By utilizing a high resolution in the first stage, the amplifierdoes not require any nonlinearity calibration. All componentsin the ADC consume only dynamic power and the architectureuses only scaling-friendly components. The ADC is fabricated in130-nm CMOS and achieves 63.2 dB SNDR and 75.4 dB SFDRwhile consuming 0.28 mW at a sampling rate of 10 MS/s. Themeasured analog power of the prototype is only 11% of thetotal power which highlights the power efficiency of the proposedresidue amplifier. To the authors’ knowledge, this work achievesthe highest interstage gain of any reported dynamic amplifier.

Index Terms—pipelined ADC, SAR, dynamic amplifier

I. INTRODUCTION

Successive approximation register (SAR) analog-to-digitalconverters (ADCs) are very popular for medium resolution(8-10 bits) applications because of their mostly digital archi-tecture and high power efficiency. For higher resolution athigh speeds, pipelining becomes an attractive option to limitthe capacitive digital-to-analog converter (CDAC) size andreduce the number of serial conversions per conversion cycle.The main drawback to this approach is the requirement ofresidue amplification between each stage. Traditional closed-loop residue amplifiers require large open-loop gains whichare difficult to achieve in advanced processes. Moreover,these amplifiers consume static power, which limits the powerefficiency when compared to a standard single-stage SARarchitecture.

Many recent works have proposed alternatives to traditionalclosed-loop residue amplifiers. One option is to performopen-loop residue amplification, which greatly reduces therequired amplifier gain at the cost of increased non-linearity.This approach can require complex digital calibration [1] orlinearization techniques [2] and still consumes static power.Other recent works have proposed using dynamic amplifiers,or integrators, for residue amplification [3]–[6]. Integrator-based amplifiers are attractive because they achieve high powerefficiency for a given input-referred noise. One drawback ofintegrator-based amplifiers is that the maximum achievable

gain is limited by transistor gm/ID and the voltage supply.Recent works have attempted to overcome this issue [4], [5],but the gain is either still limited [5], or additional gain requiresincreased timing complexity [4]. Another challenging issue formost residue amplifier architectures is the mismatch betweencomparator and amplifier offsets. Offset mismatch both in-creases the amplifier’s input swing, increasing non-linearity,and can cause overranging in later stage ADCs. These effectsare especially harmful in dynamic-amplifier based pipelinedSAR ADCs because 1) the linearity of dynamic amplifiers isgenerally much more sensitive to input swing than closed-loop amplifiers and 2) the first-stage resolution is generallyhigh in order to maintain the SAR’s power efficiency andlimit the amplifier input swing, thus reducing the LSB sizeand the effectiveness of gain redundancy. In general, eitherlarge devices or offset calibration techniques must be used inorder to meet the offset matching requirements.

In this paper, we propose a novel pipelined SAR archi-tecture, shown in Fig. 1. It addresses the aforementioneddrawbacks of other dynamic amplifiers without adding anyhardware complexity to the traditional SAR architecture byreusing the first-stage comparator, a strongARM latch, asa residue amplifier. This architecture maintains the noisefiltering of an integrator as in [5], while adding a high-speed positive feedback gain phase. The achievable maximumgain is only limited by the ratio of supply voltage to inputswing and the required second-stage linearity. The gain controlonly requires a simple tunable delay line. Since the amplifierand comparator are the same block, no calibration for offsetmismatch needs to be done to limit input swing or preventoverranging. By properly partitioning the pipeline stages, thefirst-stage residue can be kept small enough that the amplifierdoes not require any non-linearity calibration.

This paper is organized as follows. Sec. II discusses the op-eration of the proposed residue amplifier. Sec. III describes theproposed pipelined SAR ADC. Sec. IV shows the measuredresults.

II. STRONGARM LATCH AMPLIFIER OPERATION

The schematic of the proposed residue amplifier is shownin Fig. 2. The latch is very similar to that in [7], with anadded current bias to improve the common-mode rejection ofthe amplifier. When the clka signal is low, the second stageSAR capacitance is disconnected from the amplifier and the

978-1-5090-5191-5/17/$31.00@2017 IEEE

64C 32C 8C 8C C

−

+

−

64C 32C 8C 8C C

16C 8C 2C 2C C

16C 8C 2C 2C C

−

+

Vinp

Vrefn

Vrefp

Vrefp

Vrefn

Vinn

Vrefn2

Vrefp2

Vrefp2

Vrefn2

Vcm

Vcm

Clock

Generationamp

7-bit First Stage 6-bit Second Stage

DAC

Logic

clkaclk

Vresp

Vop

Von

Voc,p

Voc,n

DAC

Logic

clk2

+

clks

Vresn

clk

clka

clk2

clks

amp

Fig. 1. Proposed pipeline ADC architecture and timing diagram.

amplifier behaves as a normal comparator. When clka is high,the amplifier transfers the residue to the second stage SARwith a gain that is proportional to the time clka is kept high,τamp. The proposed amplifier operates in two gain phases,integration and regeneration. During the integration phase, thedifferential current through M1 and M2 is initially integratedon the capacitance at nodes Vxp/Vxn, Cx. Once the Vx nodevoltages decrease enough to turn on transistors M3/4, thedifferential current is then integrated onto the output load, theparallel combination of the second-stage DAC capacitance,Cs2, and the comparator parasitic capacitance, Co, until thevoltage at nodes Vop/Von drops below the threshold voltageof PMOS transistors M5/6, at which point the regenerationphase begins. At the end of this phase, the integration gainGint will be [8]

Gint ≈(gmID

)1,2

{VT5,6 +

CXCs2 + Co

(VT5,6 + VT3,4)

}(1)

M1 M2

M12

M13Vbias

M3 M4

M5 M6

M7 M8

M9 M10

Vdd

clk

clk clkclka

Cs2

clka

Cs2

Vresp

Vresn

Vop

Voc,n Voc,p

Von

clkclk

CoCo

Cx Cx

Vxp Vxn

Fig. 2. Proposed amplifier schematic.

2 4 6 8 10 12 14

Time (ns)

20

40

60

80

100

120

Gai

n (

V/V

) Integration Regen

τamp 7.2 ns

Integration and

regeneration

Integration only

Fig. 3. Simulated amplifier gain (with extrapolated integration curve)

Once the amplifier is in the regeneration phase, it acts as apositive feedback latch until clka is deasserted. At the end ofthe regeneration phase, the total amplifier gain, G is

G ≈ Gint · eTregen/τ (2)

where Tregen is the total regeneration time and τ is theregeneration time constant, given by

τ ≈ Cs2 + Cogm5,6

(3)

Fig. 3 shows the amplifier gain as a function of time. Duringthe integration phase, the gain grows linearly and in the regen-eration phase the gain grows exponentially. An extrapolatedversion of the integration gain is shown as well to highlightthe speed advantage of the positive feedback stage. For a gainof 32, adding positive feedback to the amplifier increases thespeed by more than two times.

One key advantage of this amplifier topology is that its op-eration can easily be tuned for noise and speed requirements.In the integration phase, input-referred noise is inverselyproportional to integration time, which is controlled by thebias current and load capacitance [5]. In the regenerationphase, input-referred noise is inversely proportional to loadcapacitance. Additionally, the noise from the regenerationstage is attenuated by the gain from the integration stage. Theinput-referred noise plot of Fig. 4 shows that noise decreases

1 2 3 4 5 6 7

Time (ns)

0

50

100

150

200In

pu

t-re

ferr

edn

ois

e (µ

Vrm

s)

Integration Regeneration

Fig. 4. Simulated amplifier input-referred noise

during the integration phase and levels off once regenerationbegins. For low speed and low noise designs, the integrationtime can be maximized by reducing the bias current. Forhigh-speed designs with less stringent noise requirements, thebias current can be increased to minimize integration time.Whenever possible, the load capacitance should be minimizedso that the regeneration phase can be as fast as possiblewhile still meeting noise requirements. For a given integrationtime, the input pair’s gm/ID should be large so that thenoise contribution from the regeneration phase is minimized.The upper limit on gm/ID is the required linearity of theamplifier, since the integration gain becomes more non-linearwith increasing gm/ID. By carefully controlling bias currentand load capacitance, this topology can be used across a widerange of noise and speed requirements.

Sharing the amplifier and comparator has many benefits.First, no additional amplifier hardware is needed to enableresidue amplification, reducing the system hardware complex-ity. Second, no calibration for offset mismatch needs to bedone and the comparator input pair can be sized only to meetnoise requirements without regard for offset. With standardresidue amplifiers, a mismatch between the amplifier andcomparator offsets will cause an increase in the input swingseen by the amplifier. This increased output swing is especiallyharmful for dynamic open-loop amplifiers, where non-linearityis usually very sensitive to input swing. In the proposed ampli-fier topology, the offset seen during comparator operation andamplifier operation are the same, so even a very large offsetwill have no effect on the ADC functionality. To illustrate thispoint, Figure 5 shows the offset in comparator and amplifiermode from a 10000 run Monte Carlo simulation, showingthat the offsets in both modes are almost perfectly correlated.Finally, since the amplifier sees the much larger second-stageDAC capacitance in amplification phase, the noise and speedcan be optimized separately for comparator and amplifieroperating modes by changing the ratio of comparator parasiticcapacitance to second-stage DAC capacitance. Table I showsa comparison of important performance parameters for theproposed amplifier when it is in comparator and amplifieroperation. When in comparator mode, the noise is only re-quired to match the first-stage resolution, so the comparatorcan work in a high speed, high noise mode. Once the secondstage DAC capacitance is connected, the amplifier works in alower speed, lower noise mode. Additionally, Table I shows

-40 -20 0 20 40

Comparator Offset (mV)

-40

-20

0

20

40

Am

pli

fier

Off

set

(mV

)

r = 0.9998

Fig. 5. Amplifier offset vs. comparator offset and correlation coefficient fora 10000 point Monte Carlo simulation

TABLE IPERFORMANCE COMPARISON BETWEEN COMPARATOR AND AMPLIFIER

OPERATING MODES.

Comparator Amplifiermode mode

Input-Referred Noise (µVrms) 344 101Integration Time (ns) 0.98 5.2

Regeneration Time Constant (ns) 0.19 1.8Offset (mVrms) 10.67 10.71

Energy per Operation (fJ) 86 148

that from an energy perspective, the amplifier operation isapproximately equivalent to firing the comparator an extratwo times, highlighting the power efficiency of the proposedamplification method. Sharing the amplifier and comparatorreduces hardware complexity, eliminates offset calibration, andstill enables separate optimization between comparator andamplifier operating modes.

III. PIPELINE ADC ARCHITECTURE

The proposed amplifier from Section II was integrated intothe 12-bit, 10 MS/s two-stage SAR-based pipelined ADCshown in Fig. 1. The first-stage resolution of 7 bits waschosen to reduce the amplifier input swing and eliminate theneed for gain non-linearity calibration. Both SAR sub-ADCsuse the bidirectional single-sided switching technique from[9] in order to minimize reference energy and reduce therequired DAC capacitance. Redundant capacitors are addedto overcome the common-mode voltage shifts that occurwhile using the bidirectional switching scheme. The redundantcapacitors ensure the critical conversion cycle will happenafter the common-mode voltage shifts become small. By doingthis, the offset matching between the comparator operation andamplifier operation is maintained. A voltage-controlled delayline (VCDL) is used to control the amplification time and itsdelay is tuned to a gain of 32.

IV. MEASUREMENT RESULTS

The ADC described in Section III was fabricated in 130nm CMOS technology. Fig. 6 shows the die photo andlayout of the chip. Capacitor mismatch was calibrated in theforeground with a single input. For this proof of concept,the VCDL delay was calibrated to achieve the desired gain

in the foreground with a single input, but this work couldeasily be extended to place the delay-line in an interstagegain background calibration loop to ensure robustness againstprocess, voltage, and temperature (PVT) variation. Fig. 7shows the measured output spectrum with a Nyquist input.The measured SNDR and SFDR at Nyquist was 63.2 dBand 75.4 dB, respectively, leading to a 10.2-bit ENOB. Thetotal measured power was 280 µW, of which 83% was digitalpower. Table II shows the power breakdown between digital,analog, and reference power. Fig. 8 shows the SNDR/SFDRacross input frequency and input amplitude. The dynamicrange of the ADC was measured to be 63.9 dB. These numberstranslate to a Schreier FoM of 166.4 dB. As this work is mainlya proof of concept, much optimization is possible to furtherimprove the performance. Additionally, this architecture usesonly scaling-friendly components and consumes only dynamicpower. Fabricating this design in a more advanced process than130 nm would provide significant performance benefits. TableIII shows that this prototype achieves the largest interstagegain among other state of the art dynamic amplifier works.

(a)

STG1

DAC

STG1

LOGIC

AMPSTG2

DAC

STG2

LOGIC

CLK

GEN

(b)

Fig. 6. ADC (a) die photo and (b) layout.

0 1 2 3 4 5

Frequency (MHz)

-100

-50

0

Spec

trum

(dB

FS

)

23

fin = 4.8 MHz

SNDR = 63.2dB

SFDR = 75.4dB

Fig. 7. Measured ADC output spectra with 32768 points.

TABLE IIPOWER BREAKDOWN

Supply Power (µW ) Percentage of totalDigital

(Clock generation/distribution, 233 83SAR logic)

Analog (Comparators) 30 11Reference 16.5 6

0 2 4

Input frequency (MHz)(a)

60

65

70

75

80

85

90

SN

DR

/SF

DR

(dB

)

SNDR

SFDR

-60 -40 -20 0

Input amplitude (dBFS)(b)

-20

0

20

40

60

80

SN

DR

/SF

DR

(dB

)

DR = 63.9 dB

SNDR

SFDR

Fig. 8. Measured SNDR and SFDR vs. (a) input frequency and (b) inputamplitude.

TABLE IIIPERFORMANCE COMPARISON

[5] [3] [10] [6] This workProcess (nm) 28 40 65 90 130Architecture Pipe SAR Pipe SAR Pipe SAR Pipeline Pipe SARRes. Amp Dynamic Dynamic Static Dynamic Dynamic

Architecture open-loopInterstage Gain 16 4 16 3 32

Supply Voltage (V) 1.0/1.8 1.1 1.0/1.2 0.5/0.55 1.2Sampling Rate (MS/s) 80 250 160 160 10

SNDR (Nyq) (dB) 66 56 66.2 38 63.2ENOB (bit) 10.7 9.0 10.7 6.0 10.2Power (mW) 1.5 1.7 11.1 2.43 0.28

HF Walden FoM (fJ/step) 11.5 13.2 41.6 234.0 23.7HF Schreier FoM (dB) 170.3 164.7 164.8 143.2 166.4

REFERENCES

[1] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC usingopen-loop residue amplification,” IEEE JSSC, vol. 38, no. 12, pp. 2040–2050, Dec 2003.

[2] L. Yu, M. Miyahara, and A. Matsuzawa, “A 9-bit 1.8-GS/s pipelinedADC using linearized open-loop amplifiers,” in 2015 IEEE A-SSCC,Nov 2015, pp. 1–4.

[3] B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s2x interleaved fully dynamic pipelined SAR ADC in 40nm digitalCMOS,” in 2012 IEEE ISSCC, Feb 2012, pp. 466–468.

[4] B. Malki et al., “A complementary dynamic residue amplifier for a 67dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC,” in 2014 IEEEESSCIRC, Sept 2014, pp. 215–218.

[5] F. van der Goes et al., “11.4 a 1.5mW 68dB SNDR 80MS/s 2 ×interleaved SAR-assisted pipelined ADC in 28nm CMOS,” in 2014 IEEEISSCC, Feb 2014, pp. 200–201.

[6] J. Lin, D. Paik, S. Lee, M. Miyahara, and A. Matsuzawa, “A 0.55 v7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers,”in Proceedings of the IEEE 2013 CICC, Sept 2013, pp. 1–4.

[7] Y.-T. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D converter,”IEEE JSSC, vol. 35, no. 3, pp. 308–317, March 2000.

[8] L. Chen, A. Sanyal, J. Ma, X. Tang, and N. Sun, “Comparator common-mode variation effects analysis and its application in sar adcs,” in 2016IEEE ISCAS, May 2016, pp. 2014–2017.

[9] L. Chen, A. Sanyal, J. Ma, and N. Sun, “A 24-µW 11-bit 1-MS/s SARADC with a bidirectional single-side switching technique,” in 2014 IEEEESSCIRC, Sept 2014, pp. 219–222.

[10] V. Tripathi and B. Murmann, “A 160 ms/s, 11.1 mw, single-channelpipelined sar adc with 68.3 db sndr,” in Proceedings of the IEEE 2014CICC, Sept 2014, pp. 1–4.