A Semi-Canonical Form

for Sequential Circuits

Alan Mishchenko Niklas Een Robert Brayton

UC Berkeley

Michael Case Pankaj Chauhan Nikhil Sharma Calypto Design Systems

MOTIVATION Logic circuits often contain duplicate sub-

circuits expressed in terms of different primary inputs

This leads to redundant workSynthesis tools repeatedly analyze the same

sub-circuitsVerification tools repeatedly solve the same

instances2

MOTIVATIONKey idea: identify duplicate sub-circuitsIdeal solution: exact graph isomorphism

May be expensive and hard to implement

Our solution is heuristicFind a semi-canonical circuit structureComputation is similar to simulationEfficient and straight-forward to implement

Uses only structural informationNo need for signal names and user hints

3

EXAMPLE

Fanout count {b}, {m} are unique Complemented outputs {c} is unique Fanin level {F}, {G} are unique

F

a

G

b c d

n m Level 2

Level 1

Level 0

4

Consider unique attributes of each node

EXAMPLENodes that cannot be uniquely

identified belong to the same equivalence class

The above circuit has two equivalence classes of primary outputs: {F, F’}, {G, G’}

F

a

G

b c d

n m Level 2

Level 1

Level 0

5

G’ F’

AIG In this work, sequential circuits are

represented as And-Inverter Graphs (AIGs) AIG is a Boolean network whose logic

nodes are two-input AND-nodes and invertersInverters are represented as complemented

attributes AIG is a uniform and low-memory data-

structureIt allows for an efficient implementation of a

variety of algorithms working on sequential circuits

ALGORITHM OVERVIEW Structural signature of a node is an integer

number computed for the node using its location in the circuit Initially, signatures of all nodes are set to 0 Circuit is repeatedly traversed and signatures are updated Goal: assign unique signatures for as many nodes as

possible

Motivation for computing unique signatures If a node has a unique signature, it has been uniquely

identified using its position in the circuit structure A one-to-one mapping between the nodes of two circuits

can be found using unique signatures of their nodes If such mapping exists, the circuits are structurally

isomorphic 7

ALGORITHM OVERVIEW Signature propagation is similar to circuit

simulation During circuit simulation, values of the nodes are

computed in a direct topological order During signature propagation, signatures of the nodes

are computed in a direct (or reverse) topological order

Edge value reflects the structure around an edge Depends on the position (logic level) of the driving

node Depends on whether the edge is complemented or not

Each time a node is traversed, edge values of its fanins (or fanouts) are added to the signature of the node

8

ALGORITHM OVERVIEW

9

4

1 3

5 6

8

7

2

F

a

G

b c d

n m Level 2

Level 1

Level 0

0

0

0

0

0 0 0

0

12 12 12 12

15 1

9

71

42

ALGORITHM OVERVIEWWhen nodes cannot be uniquely identified

using their structural signatures, tie breaking is used

Choose the equiv class with the largest level Assign unique signatures to the class nodes Propagate signatures to other nodes until convergence If some equiv classes are left, repeat

10

F G

H

EQ3

EQ2

EQ1a

EQ1b EQ1a EQ1b EQ1a

EQ0

71

421

515

IMPLEMENTATION Computation of unique signatures is implementation in

ABC The unique signatures (which are integer numbers) are

used to put nodes of a circuit in a semi-canonical order When nodes are written into a file in this order, the

resulting file is a semi-canonical form of the circuit If files for two circuits are identical, the circuits are

isomorphic

Application 1: ABC command “write_aiger –u” Writes the netlist in a semi-canonical form

Application 2: ABC command “&iso” Discards isomorphic POs

11

IMPLEMENTATION Application 1: ABC command “write_aiger –

u” Writes the netlist in semi-canonical form Useful for quickly comparing AIGER netlists

12

Netlist N1 write_aiger -u

N1.aig

Netlist N2 write_aiger -u

N2.aig

diff

IMPLEMENTATION Application 2: ABC command “&iso”

Derive a semi-canonical form for each PO Discard POs that have duplicate semi-canonical

forms i.e. “drop isomorphic proof obligations”

13

F

a

G

b c d

n m Level 2

Level 1

Level 0

G’ F’

a' b’ c’ d’

Counterexamples/invariants on F/G can be re-mapped to F’/G’

EXPERIMENTAL RESULTS

Test Case

FFs ANDs POs

POsafter iso

iso time (sec

)

POs after synt

h.

 

POs after iso

 

iso tim

e(sec)

SDCU 2442 14418 834 727 3.2 361 353 .09TPC_P 1619 1270 948 795 16.00 394 393 .28TCP_O 3838 36890 598 553 4.78 545 541 .55PC_T 2565 20101 274 258 .55 129 129 .01SDXIA 7822 78858 600 490 32.04 245 245 .63

DU 10864 84397 946 518198.1

4 458432 .80

Initial AIG Statistics

Use industrial verification benchmarks Remove isomorphic POs Apply synthesis, remove proved

POs Remove isomorphic POs (again)

14

CONCLUSION Previous work focused on

computing functional symmetries and automorphismssimplifying reachability and SAT using symmetries

To our knowledge, this is the first work on computing a structural semi-canonical form for sequential circuits

Allows for caching intermediate circuits in EDA tools

Future work may include: Speeding up propagation of node signaturesGeneralizing the algorithm to work for logic networks

other than the traditional sequential AIGs15

THANK YOUPublic implementation is available

in ABC https://bitbucket.org/alanmi/abc