a soft-switched high frequency link single-stage three ... · three-phase inverter for grid...

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2889795, IEEETransactions on Power Electronics

A Soft-switched High Frequency link Single-StageThree-Phase Inverter for Grid Integration of Utility

Scale RenewablesAnirban Pal,Student Member, IEEE,Kaushik Basu,Senior Member, IEEE

AbstractA novel single-stage high frequency link three-phase(3�) inverter along with a modulation strategy is presented in thispaper. The topology is targeted for grid integration of utility scalerenewable and alternative energy sources like solar, fuel cell andwind, where the power �ow is unidirectional (from DC to AC).The primary side converter has3� voltage source inverter (VSI)structure along with an additional half-bridge leg. Sinusoidalpulse width modulation is implemented in the primary sideconverter. The three legs of the primary side VSI are zero voltageswitched (ZVS) for most part of the line cycle. The additionalhalf bridge leg is zero voltage switched (ZVS) over the completeline cycle. The active switches in secondary side converter are linefrequency switched and thus results in negligible switching loss.The converter switching process is described in detail to showthe soft-switching of the primary side converter using the devicecapacitances and leakage inductances of the high frequencytransformers. The high frequency transformer galvanic isolationresults in high power density. A 4 kW laboratory scale hardwareprototype is built and tested with the proposed modulationstrategy. The experimental results are presented to verify theconverter operation.

Index TermsSingle-stage, high frequency link, DC-AC con-verter, pulse-width modulation, zero-voltage-switching, line fre-quency unfolding.

I. I NTRODUCTION

W ITH the depletion of fossil fuel reserve and the presentglobal warming scenario, power utilities all over theworld are focusing on renewable and alternative energy sourcebased power generation. In 2016 globally, total installed re-newable power capacity is 921 GW out of which 303 GW issolar capacity and wind power is 487 GW [1]. Commerciallyavailable power electronic converters to integrate utility scale(few hundreds of kW to few MW) renewable energy systemsto AC transmission grid (Fig. 1a and Fig. 1b) use a three-phase (3�) voltage source inverter (VSI) in case of PV [2],[3] or back to back connected3� VSIs in case of wind [4],[5]. The VSI output is connected to the LVAC (440-480V)grid through line �lters and a3� line frequency transformer

Manuscript received June 5, 2018; revised August 20, 2018; revised October15, 2018; revised November 23, 2018; accepted December 17, 2018. Thiswork was supported by the Central Power research Institute (CPRI), Ministryof Power, Government of India under the project titled Power conversion,control, and protection technologies for microgrid. This work was alsosupported by Department of Science and Technology, Government of Indiaunder the project titled Development of an advanced System-On-Chip (SoC)based embedded controller for power electronic converters. (Correspondingauthor : Anirban Pal).The authors are with the Department of Electrical Engineering, IndianInstitute of Science, Bangalore 560012, India. (e-mail: [email protected];[email protected]).

(LFT). Beside the voltage matching the LFT ensures safety byproviding galvanic isolation [6], avoiding DC current injectioninto the grid [7] and also helps to reduce leakage current toconform with the PV system standards such as VDE 0126-1-1[8]. The LFTs are heavy, bulky and expensive.

High frequency link (HFL) based isolated converter topolo-gies as an alternative solution to LFT based state of the artconverters have been studied extensively in recent years. Thehigh frequency transformer (HFT) based solution comes withsome attractive features like high power density, small andcompact footprint, low system cost. Most popular HFL basedsolutions are the two-stage HFL DC-AC converter topologies[9][13]. In these topologies, an isolated DC-DC stage isconnected to a VSI through a DC bus capacitor (Fig. 1c).The intermediate DC bus is voltage stiff. The VSI is highfrequency hard-switched and the DC electrolytic capacitorhas long term reliability issue [14]. The VSI can be soft-switched by employing additional switches and resonatinginductors and capacitors in the DC link. The resonant DClink concept is �rst introduced in [15] where a LC network isused to produce oscillatory DC link voltage and the inverter isswitched when the DC link voltage becomes zero. The inverterswitches suffer from high voltage stress (2-3 times input DCvoltage) and discrete pulse modulation (sigma-delta) strategyproduces signi�cant undesirable sub-harmonics at the output,[15], [16]. In quasi-resonant DC link inverter (QRDCLI), theresonating circuit comes in operation only during the switchingtransitions of the inverter to make the link voltage zero.The �rst QRDCLI topology was proposed in [17], where theresonating circuit has four active switches. Subsequent works[18][22], tried to address the problem of high voltage andcurrent stress experienced by the additional switches in theresonant cell and to reduce the number of the active devices.[19], [20], [23] reduced the frequency of the operations of theresonant cell, by reducing the number of switching transitionsthrough modi�cation of the PWM strategies of the inverter.This approach usually results in low quality output voltagewaveform when compared with standard conventional spacevector PWM. In general, the QRDCLI uses at least one activeswitch in series with the DC voltage source to disconnectthe supply during resonant operation. The RMS and peakcurrent rating of this switch is signi�cantly high comparedto the inverter switches. Though soft-switched, this switchcontributes signi�cantly to the conduction loss. This restrictsthe use of QRDCLI in high power application. Additionally,control complexity and high current stress of resonant circuit



are two major limitations of QRDCLI.In literature single-stage recti�er type HFL DC-AC con-

verters (RHFL) are widely discussed where inter-stage DCcapacitor is removed (Fig. 1d) and the DC bus is pulsating[24][27].

(a) (b)

(c)

(d)

Fig. 1. State of the art grid integration of (a) PV system and (b) wind energy.(c) Multi-stage HFL DC-AC topology, (d) Single-stage RHFL topology

In applications like grid integration of PV, fuel cell andPMSG based wind generation, the power �ow is unidirec-tional (from source to grid) [28]. Several unidirectional RHFLtopologies have been proposed in literature [14], [29][32].In these topologies, uncontrolled diodes are used in the highfrequency recti�er (HFR in Fig. 1d). In [14], [29][31] hybridmodulation (HM) strategy is used which results in highfrequency switching of the AC side converter (ASC) over onlyone third of the line cycle, results in signi�cant reductionof switching loss in ASC. In [32], the ASC is completelyline frequency switched. The DSC with six half-bridge legsare soft-switched only for some part of the line cycle. Theconverter supports only UPF operation.

In this paper a novel topology is proposed where the DSChas a 3� VSI structure connected to the DC sourceVdc alongwith one additional half bridge leg as shown in Fig. 2a. TheHFR has three diode bridges and the ASC has three half-bridge legs. The proposed topology with suggested modulationscheme has following features.

� Sinusoidal PWM is implemented in DC side converter.� The modulation strategy results in high quality output

waveform along with active power transfer at UPF.� The DSC legS1 � S2 is zero voltage switched (ZVS) over

a complete line cycle where as other three legs are zerovoltage (ZVS) switched for most part of a line cycle.

� The ASC half-bridge legs are line frequency switchedresulting in negligible switching losses.

� The high frequency galvanic isolation provides a compacthigh power density converter solution.

A part of this work was presented in [33].The paper is organised as follows. Section II describes the

modulation strategy of the converter. In section III, the con-verter switching process is described in detail. Experimentalresults are presented in section IV to validate the theoretical

analysis. The converter power loss and ef�ciency are presentedin section V.

II. C IRCUIT CONFIGURATION AND MODULATIONTECHNIQUE

The proposed topology is shown in Fig. 2a. The primaryside of the converter has a two level three-phase (3�) voltagesource inverter (VSI) structure connected to the DC sourceVdcalong with one additional half-bridge leg (S1 � S2). For eachphase, a three winding high frequency transformer (HFT) withturns ratio (n: 1 : 1) is employed. The primary windings ofthe 3� HFTs are star connected and the neutral point (N ) isconnected to the pole of legS1 � S2. In each phase, the staringend of one secondary winding is connected to the �nishing endof the other identical secondary winding. All these points areconnected to form a common point (nt ). In the secondary side,each phase of the converter has a diode bridge along with ahalf-bridge leg. The converter is connected to a balanced3�voltage source (va0n g , vb0n g , vc0n g ) with angular frequency

! o =2�T0

and peakVgpk through �lter inductors (Lf ). All theactive switches can be realized with IGBT or MOSFET with abody diode. In the following discussion, IGBTs are consideredfor implementation. The directions of the currents shown inFig. 2a are considered to be positive in rest of the paper.

To generate balanced adjustable magnitude3� AC fromthe input DC, the modulation signals (m�r j ) are given in (1).Where,m is the modulation index and is a positive fraction.j 2 f a; b; cgandM a = 0, M b = +1 andM c = �1.

m�r j = m��sin

�! ot + M j

2�3

� �� (1)

Due to presence of diode bridge, the instantaneous power�ow is unidirectional (from DC to AC). The carrier frequencyaverage of the synthesized pole voltages (vjn t ) should bein phase with the fundamental component of line currents(i a;b;c ) (Fig. 2a). So, the reference signals (m�r j ) are in phasewith fundamental component of the line currents,i j . Themodulation is implemented in the primary-side converter.The eight switches in the DC side converter are modulatedfollowing the principle of phase-shifted full-bridge (PSFB)DC-DC converter. A high frequency square wave signalFwith time period Ts and duty ratio 0.5 is considered, Fig.2b. Ts is also the period of the HFT �ux balance cycle. Aunipolar saw-tooth carrier with unity peak and period ofTs2 isconsidered and is aligned withF . Each half-bridge leg in theprimary is complementary switched with 50% duty ratio.F isused as the gating pulse (GS1 ) of S1. The gating pulses (GSX 1 )of the top switches of each VSI leg,SX 1 (X 2 f A; B; C g)are time shifted with respect toS1. For example,GSA1 is

time delayed bym�r a Ts

2with respect toGS1 or F , Fig. 2b.

So, a sine pulse width modulated (PWM) quasi square wavewith levels �V dc and zero and periodTs is applied acrossthe transformer primary (vAN in Fig. 2b). The high frequencyquasi-square wave is recti�ed by the secondary diode bridgesD j 1�4 . Wheni j > 0, Qj 1 is turned ON and the high frequencyrecti�cation happens with the top diodesD j 1, D j 3. Qj 2, D j 2;4



(a)

(b) (c)

Fig. 2. (a) Proposed 3�HFL DC-AC converter. Modulation strategy of the converter shown- (b) over a switching cycle, (c) over a line cycle.

take part in conduction wheni j < 0. So, Qj 1 and Qj 2 are

switched at line frequency�

1T0

�in complementary fashion,

Fig.2c. This results in generation of unipolar sine PWM pole

voltagesvjn t with voltage levels0 and��

Vdcn

�with respect

to nt (seevan t in Fig. 2c). The average3� pole voltages withrespect to HFT secondary neutralnt are given in (2).

vjn t =mVdc

nsin

�! ot + M j

2�3

�(2)

For a desired average pole voltage peak,Vpk , the modulation

index m =�

nVpkVdc

�. As the AC ports are connected to a

balanced3� system with �oating neutral (ng), the averagepole voltagesvjn t are equal to output voltagesvjn g .

III. C ONVERTERSWITCHING PROCESSIn this section, the circuit operation of the converter is

discussed in detail over one switching cycle (Ts). The pre-sented analysis shows that the half-bridge legS1 � S2 iscompletely soft-switched and each of the legs of the VSI,SX 1 � SX 2 (X 2 f A; B; C g), are soft-switched for most partof the line cycle with the help of device parasitic capacitances(Cs) and transformer leakage and additional series inductance(L lk ). The secondary side active switch pairsQj 1 � Qj 2 areline frequency switched incurring negligible switching loss.For ease of analysis, slowly varying line currentsi a;b;c areconsidered as constant current sources with magnitudeI a;b;c

over a switching cycleTs. The switching process of theconverter is described wheni a = I a and i b = I b but i c = �I cand I c > I a > I b. In other regions similar switching processwill be followed. Switching waveforms overTs are shown inFig. 3. The circuit dynamics in one half of the switching cycle(Ts) is divided into ten modes (1-10), other half evolves in anidentical fashion.

A. Mode 1 (t0 < t < t 1)In this mode in the primary side converter,S1 andSX 2 (X 2

fA; B; C g) are conducting (Fig. 4). The equivalent circuit isshown in Fig. 5a. Negative voltage�V dc is applied acrossHFT primary terminalsAN , BN andCN . The HFT primarycurrents,i pj = �

I jn

where (j 2 f a; b; cg) as shown in Fig. 3.The voltage polarity and direction of currents indicate activepower �ow from DC to AC side in all three phases (all threephases are in active state). In secondaryDa3 ; Qa1 ; Db3; Qb1andD c2; Qc2 are conducting.

B. Mode 2 (t1 < t < t 2)At t1, SB 2 is turned OFF (Fig. 6). Active to zero state

transition of phaseb starts att1. Due to device capacitance(Cs), the voltage acrossSB 2 can not rise immediately. Voltagestarts rising after channel current falls below zero resultingzero voltage turn OFF (ZVS) ofSB 2. b phase primary current� I bn starts charging the capacitance acrossSB 2 and discharg-ing the capacitance acrossSB 1. Equivalent circuit in this mode



Fig. 3. Switching waveforms overTs

Fig. 4. Simpli�ed circuit diagram inMode 1(t0 < t < t 1 in Fig. 3)

(a) (b)

Fig. 5. (a) Equivalent circuit diagram inMode 1, (b) Equivalent circuitdiagram inMode 2.


is shown in Fig. 5b. From the equivalent circuit it can be shownthat the voltages acrossSB 1, vSB 1 falls as per (3).

vSB 1 (t) = Vdc �I b

2nCs(t � t1) (3)

Phasea andc remain in active state during this duration.

C. Mode 3 (t2 < t < t 3)

At t2, the capacitor acrossSB 1 is completely discharged.The anti-parallel diode ofSB 1 starts conducting (Fig. 7). Aftert2, SB 2 blocksVdc . The durationtazb = ( t2 � t1) is given in(4).


tazb =2nCsVdc

I b(4)

The primary ofb phase HFT is shorted throughS1 and anti-parallel diode ofSB 1. To achieve ZVS transition,SB 1 is turnedON in this mode (dead time betweenSB 2 and SB 1 must begreater thantazb ). Equivalent circuit in this mode is shownin Fig. 8a. Phaseb is in zero state i.e no active power istransferred from DC to AC side in phaseb.

D. Mode 4-6

Similar active to zero state transitions occur in phasea inMode 4 (t3 < t < t 4) with ZVS turn OFF ofSA2 and in phasec in Mode 6 (t5 < t < t 6) with ZVS turn OFF ofSC 2. InMode 5 (t4 < t < t 5), phasea, b are in zero states and phasec is in active state.SA1 is turned ON to ensure ZVS when itsanti-parallel diode is conducting.



(a) (b)

Fig. 8. (a) Equivalent circuit diagram inMode 3, (b) Equivalent circuitdiagram inMode 7.

Fig. 9. Simpli�ed circuit diagram inMode 7 (t6 < t < t 7 in Fig. 3)

E. Mode 7 (t6 < t < t 7)In this mode, all three phases are in zero state. HFT primary

terminalsAN , BN and CN are shorted throughS1 and theanti-parallel diodes ofSX 1 (Fig. 9). ZVS turn ON ofSC 1 isachieved in this interval. No active power is transferred fromDC to AC side. Equivalent circuit is shown in Fig. 8b.

F. Mode 8 (t7 < t < t 8)


(a) (b)

Fig. 11. (a) Equivalent circuit diagram inMode 8, (b) Equivalent circuitdiagram inSub-mode 1of Mode 9

At t7, S1 is turned OFF. Due to device capacitanceCs,voltage acrossS1, vS1 can not rise immediately, resulting in

ZVS turn OFF ofS1. The neutral currenti N starts chargingthe capacitor (Cs) acrossS1 and discharging the capacitoracrossS2 (Fig. 10). Equivalent circuit in this mode is shown inFig. 11a. A positive voltage appears across the HFT primaries(AN; BN andCN ). Secondary diodesDa1 , Db1 andD c4 areforward biased and start conducting. This results in shortingof HFT secondary windings (Fig. 11a) and the primary circuitdynamics become independent of secondary line currents. Inprimary, the voltage polarity is against the direction of currentsthroughL lk resulting in reduction of magnitudes of primarycurrents (ipa ; i pb and i pc). Circuit equations are given in (5).

i N = i pa + i pb + i pcVdc = vS1 + vS2

i N (t) = Cs�

dvS1dt

�dvS2dt

�

dipadt

=dipbdt

=dipcdt

= �vS1L lk

(5)

WherevS1 andvS2 are the voltages acrossS1 andS2. Solving(5) following expressions of voltage and currents are obtained.

i N (t) = i N (t 7) cos! r (t � t7)

i pj (t) = i pj (t 7) �i N (t 7)

3(1 � cos! r (t � t7))

vS1 (t) =! r L lk i N (t 7)

3sin ! r (t � t7)

(6)

Where j 2 fa; b; cg and ! r =r

32L lk Cs

. At t8, vS1 reachesVdc and vS2 = 0. The anti-parallel diode ofS2 is forwardbiased and starts conducting. The duration ofMode 8,tza1 =(t 8 � t7) is expressed as

tza1 =1

! rsin�1

�3Vdc

! r L lk i N (t 7)

�(7)

For the capacitor acrossS2 to be completely dischargedfollowing condition must be satis�ed

! r L lk i N (t 7) � 3Vdc (8)

Else the circuit will enter into resonant oscillation mode withangular frequency! r and will remain in this mode till thegating pulse ofS2 is being applied.

G. Mode 9 (t8 < t < t 9)

From (6),ji pj (t 7) � i pj (t 8)j have same values forj = a; b; c.So, ji pc(t 8)j > ji pa (t 8)j > ji pb(t 8)j as I c > I a > I b. In thismode, the primary currentsi pj change the direction linearly

and wheneveri pj reachI jn

the circuit dynamics of the cor-responding phase is complete. Based on the magnitude att8,�rst b phase primary current reaches

I bn

and thena and thenc

phase primary currents reachI an

andI cn

respectively (see Fig.12). Mode 9 is divided into three sub-modes. As the primaryside3� VSI switchesSA1 ;B 1;C 1 are already ON (ZVS) beforeentering into this mode, in the sub-modes initially the anti-parallel diodes and then active switches (SA1 ;B 1;C 1) take partin conduction based on the direction ofi pj .



Fig. 12. Enlarged current wave forms inMode 9

Fig. 13. Simpli�ed circuit diagram inSub-mode 1(t8 < t < t 81 in Fig. 12)

1) Sub-mode 1 (t8 < t < t 81 ): Simpli�ed circuit in thissub-mode is shown in Fig. 13 and the equivalent circuit isshown in Fig. 11b. As the voltage polarity applied across theHFT primaries is against the direction of currents throughL lk ,primary currents andi N fall linearly as in (9).

i N (t) = i N (t 8) �3VdcL lk

(t � t8)

i pj (t) = i pj (t 8) �VdcL lk

(t � t8)(9)

In secondary, line currents are transferred linearly fromDa3 ,Db3 and D c2 to Da1 , Db1 and D c4 respectively. In Fig. 12,currents throughDa1 andDa3 are shown. In this intervali pbchanges its direction.

2) Sub-mode 2 (t81 < t < t 82 ): At t81 , i pb reaches the

active state valueI bn

. In secondary,I b is completely trans-ferred fromDb3 to Db1 and Db3 is reverse biased (Fig. 15).

(a) (b)

Fig. 14. (a) Equivalent circuit diagram inSub-mode 2of Mode 9, (b)Equivalent circuit diagram inSub-mode 3of Mode 9

Equivalent circuit is shown in Fig. 14a. Asi pb is clamped toI bn

, the slope ofi N changes from3VdcL lk

to2VdcL lk

in this interval.Phaseb has completed its zero to active state transition. Othertwo primary phase currents changes with same slope as inSub-mode 1.

Fig. 15. Simpli�ed circuit diagram inSub-mode 2(t81 < t < t 82 in Fig.12)

Fig. 16. Simpli�ed circuit diagram inSub-mode 3(t82 < t < t 9 in Fig. 12)

3) Sub-mode 3 (t82 < t < t 9): At t82 , i pa reaches the active

state valueI an

. In secondary,I a is transferred completely fromDa3 to Da1 and Da3 is reverse biased (Fig. 16). Equivalentcircuit is shown in Fig. 14b. As,i pb and i pa are clamped toI bn

andI an

respectively, the slope ofi N changes from2VdcL lk

toVdcL lk

in this interval. Phasea has completed its zero to activestate transition. Phasec current changes with same slope asin Sub-mode 2.

In mode 9, the slope ofi N is 3ms in Sub-mode 1,2msin Sub-mode 2and ms in Sub-mode 3, wherems =

VdcL lk

. In



Fig. 17. Figure showing envelopes of HFT primary and neutral currents

mode 8-9,i N is changed from�I a + I b + I c

nto

I a + I b + I cn

.i N reaches zero attN (see Fig. 12). To achieve ZVS turnON of S2, it must be turned ON in some time betweent8and tN when the anti-parallel diode ofS2 is in conduction.So, it is important to �nd minimum of(t N � t7) = (t N �t8) + (t 8 � t7). (t 8 � t7) is given in (7).4t N is de�ned as4t N = (t N � t8). The objective of the following analysis isto �nd 4t N;min . In this analysis,(t 8 � t7) and the changein current magnitude,ji pj (t 7) � i pj (t 8)j are considered to benegligible. So,4t N depends onms, I a , I b and I c. Assumingnegligible current ripple, the line currents are given as-i j =

I pk sin�

! ot + M j2�3

�(from (1)). So,4t N depends onI pk

and � where � = (! ot � 90� ). Let, i max is maximum ofI a , I b and I c. Similarly, i mid and i min can be de�ned. Asi a + i b + i c = 0, i max = i min + i mid . The waveforms ofi pa and i N are square waves at switching frequencyTs andhave envelopes asi pae and i N e respectively over a line cycle(� = ! ot) as shown in Fig. 17.i max has similar envelopeas the positive half ofi N e . Due to symmetry, the analysisof 4t N;min is carried out for0� < � < 30� . From above

assumption,i N (t 8) ’ �2imax

n. The time interval ofSub-mode

1 can be expressed as-(t 81 � t8) =2iminnms

. At t81 , i N (t) canbe expressed as in (10).

i N (t 81 ) = �2(i max )

n+ 3m s

�2iminnms

�

=I pkn

(3p

3 sin� � cos� )(10)

i N (t 81 ) is monotonic in� and reaches zero at� � = 10:89� .So, for � < � � , 4t N is given in (11).

4t N =�

2imaxn

� �1

3ms

�

=2Ipk

3nmscos� 0� < � < � �

(11)

For � > � � , it is possible to showi N will reach zero inSub-

mode 2.i N will takei N (t 81 )

2msamount of time to become zero

in Sub-mode 2.4t N is given in (12).

4t N =�

2iminnms

�+

�i N (t 81 )

2ms

�

=I pk

nmssin(� + 30 � ) � � < � < 30�

(12)

From (11) and (12),4t N;min occurs at � = � � and

4t N;min = 0 :655I pk

nms. To achieve ZVS turn ON of the

primary half-bridge legS1 � S2 over the complete line cycle,the dead-time,DT should be less than4t N;min . Using (7),complete soft-switching condition ofS1 � S2 is given in (13).

1! r

sin�1 p

3nVdc! r L lk I pk

!

� DT � 0:655I pk L lknVdc

(13)

H. Mode 10 (t9 < t < t 10)


Fig. 19. Equivalent circuit diagram inMode 10

At t9, i pc reaches the active state valueI cn

. In secondary,I cis transferred completely fromD c2 to D c4 andD c2 is reversebiased (Fig. 18). Equivalent circuit is shown in Fig. 19. All thephases are in active state and transferring power. The circuitcon�guration is similar as inMode 1.

In above discussion, polarity reversal of HFT primaryvoltages and currents are shown in one half of the switchingcycle. Similar switching sequence will be followed in rest halfof the switching cycle with other symmetrical switches. It isseen that during active to zero state transitions3� VSI legs areswitched. And the half-bridge leg (S1 � S2) is switched duringzero to active state transition. The above discussion shows, allswitches in the3� VSI are zero voltage switched (ZVS) formost part of the line cycle whereas the ZVS of the half-bridgeleg (S1 � S2) can be ensured over complete line cycle.

IV. EXPERIMENTAL VALIDATIONA. Setup and operating condition

The modulation strategy and switching process of theproposed topology (Fig. 2a) are experimentally veri�ed in alaboratory scale hardware prototype (Fig. 20). Four primaryHF legs and three secondary line frequency switched legs areimplemented using 1200 V, 75 A SEMIKRON IGBT modulesSKM75GB123D. 1200 V, 75 A IXYS fast recovery diodemodules MEE 75-12 DA are used to implement secondary



Fig. 20. Laboratory prototype

TABLE IOPERATING CONDITION OF THE 3� TOPOLOGY

Parameter ValuesOutput Power,P 4 kW

DC input, Vdc 350 Voutput voltage peak ,Vgpk 200 V

Output frequency,f o 50 HzSwitching frequency,f s 20 kHz

diode bridges. The IGBT modules are driven with opticallyisolated gate driver IC, ACPL 339J with driving voltage level�15 V. The primary modules are switched at 20 kHz where assecondary modules are switched at 50 Hz. A 600 ns dead time(DT ) is provided between the gating pulses of the top and thebottom IGBTs of an IGBT module. EPCOS ferrite E cores (E80/38/20) are used for three winding HFTs. The turns ratio isselected as 51:34:34. The leakage inductance of HFTs are inthe range of 6-8�H. A series inductance of 48�H is connectedto each primary of the HFTs. To implement the modulationstrategy and generate the gating signals a ARM-FPGA basedSystem on Chip (SoC) controller platform (Xilinx Zynq-7000)is used. The operating condition of the converter is given inTable I.

Fig. 21. Phasor diagram of the converter connected to the AC source

Phasor diagram is shown in Fig. 21 whereVpk and I pk arethe peak ofvan g and i a , respectively.Vgpk is the AC sourcepeak value andX f = 2�fL f is the line reactance and� isthe phase angle. From the phasor diagram (Fig. 21) followingequations can be written.

Vpk \� = Vgpk \0 � + j (2�fL f )I pk \�P = 1:5Vgpk I pk cos� = 1:5Vpk I pk

(14)

Solving (14),

Vpk =

0

@V2

gpk

2+

sV 4gpk

4�

�X f P1:5

� 21

A1=2

� = sin �1�

2�fL f I pkVgpk

�(15)

The voltage at pointa0; b0; c0 are sensed and modulation index(m) and the phase angle (�) are adjusted for a given power�ow (P ) to synthesized converter output voltagev(a;b;c)n g . Forthe operating condition given in Table I, modulation index andphase angle are calculated as� = 3 � , m = 0:86. So, powerfactor cos� = 0:998 � 1.

(a)

(b)

Fig. 22. (a) Converter pole voltages- [CH1]vAN (500V/div.), [CH2]van t (250V/div.), [CH3] van g (250V/div.), [CH4] va0n g (250V/div.). Timescale 2ms/div., (b) Converter output voltage and line currents- [CH1]va0n g(100V/div.), [CH2] i a (20A/div.), [CH3] i b (20A/div.), [CH4] i c (20A/div.).Time scale 4ms/div.

B. Veri�cation of modulation strategy

The output of the converter is connected to a balanced3�voltage source (va0n g , vb0n g andvc0n g ) with phase peak (Vgpk )200 V and frequency 50 Hz. The converter is modulated togenerate balanced3� average output voltages (van g , vbng andvcn g ) at 50 Hz following the strategy described in section IIso that it supplies active power of 4 kW at unity power factor.van g leadsva0n g . As the impedance ofL f = 2:5mH at 50 Hzis relatively small,van g approximately followsva0n g .

In Fig. 22a, the pulse width modulated HF AC across HFTprimary of phasea (vAN ) is shown.vAN has voltage levels of



�350 V and zero. The unipolar PWM pole voltage (van t ) withrespect to HFT secondary neutralnt is also shown in CH2.van t has voltage levels of�233 V and zero. The experimentalwaveforms ofvAN andvan t have matched with the analyticalwaveforms shown in Fig. 2c. The pole voltage (van g ) withrespect to load neutralng is presented in CH3. Due to presenceof HF common mode voltage, the waveforms ofvan t andvan gare different though they have same average component. Theload voltage waveform (va0n g ) after line �lter L f is shown inCH4. As in table I,va0n g has a peak value (Vgpk ) of 200 V.

Fig. 22b shows load voltage of phasea, va0n g and balanced3� line currentsi a;b;c over two line cycles.va0n g is almostin phase withi a and the line currents contain very low highfrequency ripple due to �ltering action ofL f . The line currents

have an estimated peak ofI pk =P

1:5Vgpk cos�= 13:33A.

Experimentally measured peak is 13.4 A. These set of resultscon�rm the three phase operation of the proposed converter.

Line frequency switching of secondary switches are shownin Fig. 23a. The gate emitter voltage ofQa1 (vGE;Q a 1 ) is high(+15V) when the line currenti a > 0. This experimental resultvalidates line frequency switching described in the modulationstrategy and shown in Fig. 2c. Fig. 23a also presents theprimary current corresponding to phasea (i pa ) and the HFTneutral currenti N over a line cycle. The waveform ofi pais high frequency square wave with magnitude sinusoidallyvarying over line cycle. The envelope ofi pa has a peak of

i pa;pk =I pkn

= 8:9 A. Unlike i pa , the envelope ofi N never

becomes zero. The envelope ofi N has a periodicity ofT06

withpeak valuei N;pk = 2i pa;pk = 17:8 A and minimum valuep

3iN;pk2

= 15:4 A. Such envelope ofi N helps to achievecomplete soft-switching of legS1-S2 over a line cycle.

Fig. 23b presents HFT primary voltage (vAN ) and current(i pa ) waveforms over two switching cycle (2Ts). HFT primarycurrent polarity changes when applied voltage changes fromzero to�V dc (zero to active state) as discussed in section IIIand shown in Fig. 3. Fig. 23b con�rms that HFT �ux balanceis achieved in one switching cycle.

Fig. 24a shows3� primary voltages (vA;B;C �N ) of HFTsalong with neutral currenti N over two switching cycles.The experimental waveforms are matched with the analyticalwaveforms shown in Fig. 3. From the �gure, the zero to activestate transition occurs simultaneously in all the three phasesand during this timei N also changes its direction. The legS1 � S2 are switched at this instant. Active to zero transitionsare not synchronised.

C. Veri�cation of converter switching processThe switching strategy of phase legsSA1 �A2 , SB 1�B 2

and SC 1�C 2 are similar. Hence phaseA leg SA1�A2 areconsidered for discussion. In a high frequency switching cycle(Ts), SA1 �A2 are switched twice during active to zero statetransitions of phaseA. During one transitionSA2 is turnedON andSA1 is turned OFF and in the next transitionSA2 isturned OFF andSA1 is ON. The switching process in both thetransitions are same. Similarly, in a switching cycle (Ts) there

(a)

(b)

Fig. 23. (a) Line frequency switching of secondary switch- [CH1]vGE;Q a 1(25V/div.), [CH2] i a (35A/div.), [CH3] i pa (35A/div.), [CH4] i N (35A/div.).Time scale 2ms/div. (b) HFT primary voltage and current- [CH1]vAN(250V/div.), [CH2] i pa (10A/div.). Time scale 10�s/div.

(a)

(b)

Fig. 24. (a) HFTs input voltages and neutral current- [CH1]vAN (500V/div.),[CH2] vBN (500V/div.), [CH3]vCN (500V/div.), [CH4] i N (20A/div.). Timescale 10�s/div., (b) Converter primary currents- [CH1]i pa (5A/div.), [CH2]i pb (5A/div.), [CH3] i pc (5A/div.), [CH4] i N (5A/div.). Time scale 1�s/div.



are two zero to active state transition during which legS1 � S2are switched. And here also, the switching process wise boththe transition ofS1 � S2 is similar. So, it is suf�cient to checkany one transition in legsSA1�A2 and S1 � S2 to verify thesoft-switching process.

(a)

(b)

(c)

(d)

Fig. 25. Switching transition waveforms of legS1 � S2 -(a) turn ON ofS1 ,(b) turn OFF ofS2 . Switching transition waveforms of legSA1 � SA2 -(c)turn ON of SA1 , (d) turn OFF ofSA2

In Fig. 25a shows the turn ON transition ofS1. It is seen

Fig. 26. Hard-switching transition ofSA1 � SA2

from the �gure that the collector emitter voltagevCE;S 1 �rstfalls to zero and the pole currenti N is negative which indicatesthe anti parallel diode ofS1 is in conduction. Before thedirection of i N is changed, the gate-emitter voltagevGE;S 1is applied to achieve zero-voltage turn ON ofS1. Fig. 25bshows the turn OFF transition ofS2. It is seen that the voltageacrossS2, vCE;S 2 starts rising some time after the removal ofthe gating pulse,vGE;S 2 (whenvGE;S 2 is approximately zeroor is negative). ThevGE;S 2 represents the channel current ofS2. Below threshold voltage the channel current is zero. Dueto presence of capacitance acrossS2 the channel current falls�rst and then the voltage acrossS2 starts rising which resultsin zero voltage turn OFF ofS2. These results show the ZVSoperation ofS1 � S2.

Fig. 25c shows the turn ON transition ofSA1 . From the�gure it is seen that the gating pulsevGE;S A1 is appliedafter the collector emitter voltagevCE;S A1 becomes zero. Asthe pole current (ipa ) direction does not change during thetransition, the anti-parallel diode ofSA1 is in conduction. Sothe turn ON ofSA1 is a zero voltage transition. In Fig. 25dthe turn OFF transition ofSA2 is shown. The collector emittervoltage (vCE;S A2 ) starts rising some time after the gating pulsevGE;S A2 is removed and whenvGE;S A2 is approximately zeroor negative. This indicates the channel current throughSA2 iszero whenvCE;S A2 starts rising, results in zero voltage turnOFF transition. The delay in rise ofvCE;S A2 is caused by thecapacitance presents acrossSA2 . These results show the ZVSoperation ofSA1 �A2 .

TheSA1 � SA2 are hard switched in the shaded zone shownin Fig. 17. Fig. 26 presents the hard turn ON ofSA1 . Themagnitude ofi pa is very low. After the gating pulse ofSA2 ,vGE;S A 2 is removed, the voltage acrossSA1 , vCE;S A1 startsfalling linearly. A sharp fall invCE;S A1 is observed whenthe SA1 is turned ON before the device capacitanceCs iscompletely discharged. This results in hard turn ON ofSA1 .

V. CONVERTERPOWER LOSS ANDEFFICIENCY

In this section, power loss of different stages of the converteris estimated and also obtained experimentally for a variationof load power in the range of 1kW-4kW.

a soft-switched high frequency link single-stage three ... · three-phase inverter for grid...

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