1

A Study on Metal Gate Electrodes with

Nano-Sized Grains for Scalable

La-silicate Gate Dielectrics

Supervisor: Prof. Hiroshi Iwai

Supervisor: Associate Prof. Kuniyuki Kakushima

2014/02/06

Kamale Tuokedaerhan

Dissertation defense

2

I. Introduction

II. Device fabrication process and characterization method

III. Metal carbides for gate electrodes application

(propose a novel process for metal carbide)

VI. Conclusion

V. Reliability of La-silicate

high-k with tungsten

carbide gate electrodes

IV. Electrical properties

of La-silicate high-k with

tungsten carbide gate

electrodes

Dissertation outline

3

I. Introduction

II. Device fabrication process and characterization method

III. Metal carbides for gate electrodes application

(propose a novel process for metal carbide)

VI. Conclusion

V. Reliability of La-silicate

high-k with tungsten

carbide gate electrodes

IV. Electrical properties

of La-silicate high-k with

tungsten carbide gate

electrodes

Dissertation outline

4

Downscaling of MOSFET

Downscaling of the MOSFET has been the driving force for

circuit performance evolution.

However, power consumption increased to unacceptable level

Suppression of subthreshold leakage, variability and gate

leakage is necessary

1 0.010.1

1

10

100

1000

0.1

0.01

0.001

Po

we

r D

en

sit

y [

W/c

m2]

Gate Length [m]

Active Power

Passive Power

Gate

Leakage

Scaling trend of MOSFET

Source: Intel

Further gate oxide scaling is possible by high-k gate dielectrics

Introduction of high-k gate dielectrics

SiO2

Poly-Si

S D

High-k

Metal

S D

Downsizing phystEOTkhigh

SiO

2

ox

ooxox

tC

EOT : Equivalent Oxide Thickness

N. Sugii, EUROSOI, 2011. T. Ghani, VLSI, 2000.

Selection of appropriate high-k materials is important

6

Direct contact high-k/Si for EOT scaling

0

0.2

0.4

0.6

0.8

1

1.2

2009 2014 2019 2024

ITRS 2009

Year

EO

T(n

m)

EOT=0.5 nm

bulk

MG

UTB FD

Si sub.

High-kHigh-k High-k

SiOx interfacial layer (typ.0.5~0.7nm)

Scaling in EOT

limitHf based oxide

High-k/Si direct contact is required for scaled EOT beyond 0.5 nm

Dielectric constant

J. Robertson, 2004.

Si

SiO2

High-kMetal

Si

High-k

Metal

With SiO2 IL High-k/Si direct contact

7

Reports on direct high-k/Si

IL scavenging

Si sub.

HfO2

metalO

SiO2

O O

direct high-k/Si

Vo control

Si sub.

HfO2

metalO

O

Odirect high-k/Si

K. Choi, et al., VLSI Symp. Tech. p.138 (2009).J. Huang, et al., VLSI Symp. Tech. p.34 (2009).

EOT=0.59nm EOT=0.55nm

negative

shift

Control of oxygen atoms by process is the key technology

to achieve a direct HfO2/Si structure.

8

Issue of Hf-based oxide

Hf-based oxide suffer from crystallization

J. Robertson, Eur. Phys. J. Appl. Phys., 28, 265-291 (2004).

HfO2(40%)+SiO2(60%)

Plane TEM

Lg

Grain boundary

A. I. Kingon, et al., IWGI, p.36 (2001).

Phase separation

Amorphous gate oxide for gate

dielectric application

Direct high-k/Si by La-silicate formation

1837184018431846

Binding energy (eV)In

ten

sit

y (

a.u

)

300 oC

annealing

Si sub.

La-silicateas depo.

500 oC

annealing

Si substrate

XPS (Si 1s)

La2O3 + nSi + mO2

→ La(SiO4)n

La-rich Si-rich(k~20) (k~8)

(La-silicates)

Supply of oxygen atoms

nsmall large

K. Kakushima, Solid-state

electro 54., (2010).

Eg (eV) Structure

La2O3 5.5~5.6 hexagonal

La-silicate 6.2 amorphous

K. Kakushima, ゲートスタック研究会資料 (2012)

Direct contact of high-k/Si can be achieved with La-silicate

formation

La-silicate formed by reaction of La2O3 and Si substrate

Metal gate

Si

Metal gate

Si

La2O3 La-silicate

Before annealing After annealing

MIPSW TiN/W

Kav ~ 8 Kav ~ 12 Kav ~ 16

Si 2nm2nm2nm

HK

MG

800oC, 30min

La-silicate

(k~16)

10

stress relaxation at interface

La atom

La-O-Si bonding

Si sub.

SiO4tetrahedron network

FGA800oC is necessary to

reduce the interfacial stressS. D. Kosowsky, et al., APL, 73, p.3119 (1997).

High-temperature for small Dit

10-9

10-8

10-7

10-6

Ch

arg

e p

um

pin

g c

urr

en

t [A

]

104

105

106

Frequency [Hz]

Dit = 2 x 1012 [cm-2/eV]

Dit = 5 x 1011 [cm-2/eV]

Dit = 1.6 x 1011 [cm-2/eV]

500oC

700oC

800oC

T. Kawanago, IEEE Trans. ED, (2012)

K. Kakushima, ゲートスタック研究会資料 (2012)

With high temperature annealing,

Dit can be as low as 1011 cm-2/eV

11

300

250

200

150

100

50

0

Ele

ctr

on

Mob

ility

[cm

2/V

sec]

1.31.21.110.90.80.70.60.5

EOT [nm]

at 1MV/cm

T = 300KW/La-silicate

Hf-based

oxides

① Coulomb(Dit, Qfix) scattering

Mobility degradation trend with EOT scaling

② roughness scattering

Metal induced defects;

metal atom, oxygen vacancy formation

metal/high-k and high-k/Si roughness

Suppression of the formation of metal induced defects

in the high-k layer is important

T. Kawanago, IEEE Trans. ED, 2012

Scaling issues for La-silicates

①

②

12

Influence of metal gate to EOT scaling

Metal diffusion or/and metal induced defects increase

interface state density

K. Kakushima, Solid-state electro., 2010

Influence of metal gate to bulk/interface should

be minimized

W gate

Distance (nm)

Inte

nsity (

a.u

)

W

La

Si

O

N

Ti

Metal diffusion or/and metal

induced defects

Issues on direct contact of high-k/Si

20nm

Metal

Si sub.

High-k

field-SiO2

strain no strain under

field-oxide

Stress applied below high-k layer, and not under SiO2

Possible reasons

- Thermal expansion difference

- Less viscous flow of high-k dielectric

- Stress from high-k or/and metal gate

W/Tm2O3/n-Si,

annealed at 500 oC

M. Kouda, et al., J.

Vac. Sci. Technol. B

29 , 062202 (2011)

14

Metal gate

- Thermal stability against agglomeration

- Stability against phase separation

- Small resistivity

- Proper workfunction for n/p-FETs

- Small grain size less than 5 nm

- Less orientation dependent workfunction

Lg

H. F. Dadgour, Trans. ED, 57, 2515 (2010)

sVth

General requirements for metal gate material

Along with EOT scalability, these requirements should be

satisfied at the same time

Commonly nitrides (TiN, TaN, etc) with midgap WF are used

15

Material Orientation Probability Workfunction (eV) Grain size (nm)

TiN(100) 60% 4.6

22(111) 40% 4.4

TaN

(100) 50% 4.0

7(200) 30% 4.2

(220) 20% 4.8

WN

(111) 65% 4.5

10(200) 15% 4.6

(220) 15% 5.3

(311) 5% 4.2

Reported orientation dependent work function

H. F. Dadgour, Trans. ED, 57, 2515 (2010)

Need for metals with less orientation dependent

work function with small grain size or amorphous

Sputter TiN

CVD TiN

A. Yagishita, et al., TED, 48(8), pp. 1604-1611 (2001).

Reports on DVth by metal gates

Sputter TiN

CVD TiN

Oriented growth of CVD-TiN effective for suppress

DVth

T. Matsukawa, IEDM, 2012.

Reports on amorphous metal gate

Amorphous metal gate effective for suppress variability

1. Oxygen atoms required for La-silicate reaction

La2O3+Si+xO → LaSiOy(Proper oxygen atom supply is needed)

2. Grain size should be less than 5 nm (Lg=16nm)

Work function variability

W, Mo, etc.

Oxygen atoms should be released after annealing

Too much oxygen → lower k-value

Less oxygen → residual La2O3 layer

Nitrides, Carbides, Borides

Metal material candidates for La-silicate

TiN, TaN do not contain oxygen, they react to form TiOx, TaOx, instead

Pei-Chuen Jiang, et al., Appl. Phys. Let., 89, 122107 (2006).

Properties of WNx films are sensitive to N atom contents

difficult to control: N is introduced as gas (N2 or NH3)

W nitrides for La-silicate

Borides: WB, WB2, Mo2B, MoB, Mo2B5, MoB4

Carbides: W2C, WC, Mo2C, MoC

Carbides and Borides for La-silicate

How we can obtain carbides at low temperature (~800oC) ?

21

Purpose of the doctoral thesis

Proper metal gate material selection for scalable

La-silicate gate dielectrics

La-silicate

Si sub.

Metal gate

A process for metal

gate formation with

nano-sized grains

Interface property

improvement

Reliability

improvement

22

I. Introduction

II. Device fabrication process and characterization method

III. Metal carbides for gate electrodes application

(propose a novel process for metal carbide)

VI. Conclusion

V. Reliability of La-silicate

high-k with tungsten

carbide gate electrodes

IV. Electrical properties

of La-silicate high-k with

tungsten carbide gate

electrodes

Dissertation outline

23

Process for tungsten carbide formation

Deposition of several sets of carbon

and tungsten layers

1. Layered reaction to suppress

excess growth of grain size

2. Content of carbon can be controlled

3. Tungsten carbide can be formed at

low temperature

Advantage Carbide formation

annealing

multi-stacking of

Metal/Carbon layers

1. Sputtering from carbide alloy target

Deposition methods of carbides

Carbon deficiency formation during annealing

2. Sputtering with CH4 gas

3. Solid reaction of C and W layersHydrogen to produce carbon deficiency

Interface reaction and grows grains

metal

Gate oxide

Si sub.

carbon

metal

carbonmetal

carbon

H, Romanus, Thin solid Films 146, (2000)

M. Sakaki, Int. Journal of refractory metals and

hard materials, 36, (2013)

24

Process for Tungsten carbide formation

W/C

ratio

W/C=

1:0.5

W/C=

1:0.6

W/C=

1:0.8

W/C=

1:1

W 0.7nm 0.7nm 0.7nm 0.7nm

C 0.22nm 0.26nm 0.35nm 0.45nm

Si sub.

SiO2

Si sub.

SiO2

annealing

18sets

One set

Tungsten Carbide

C/W

Easily control of carbon content

25

Formation of tungsten carbide

hex-WC

Lo

g (

cou

nts

)

hex-W2C

30 40 50 60 70 9080

-2 (deg)

W/C=1:1

hex-W2C

W/C =1:0.5

Pure W

Temperature (oC)

sh

(/s

q.)

0 200 400 600 800 1000

0

50

200

150

100

W/C=1:0.8

W/C=1:0.5

W/C=1:0.6

W/C=1:1

SiO2

Si

・・・

WC

WC

W2C with small grain size can be obtained at 725oC~825oC

Grain size

= 1.9nm

Grain size

= 18nm

Grain size

= 20nm

cos2

L

KB

26

Formation of tungsten carbide

Formation of oriented growth of hexagonal W2C layer

with columnar shaped nano-sized grains(oriented growth is commonly achieved with CVD in 10-nm-thickness region)

h-W2C

20nm

columnar growth

preferred orientation

<001><001> h-W2C

<110><100>

SiO2

growth

direction

h-W2C

growth

direction

27

Process for TaC and TiC formation

Si sub.

SiO2

Si sub.

SiO2

annealing

18sets

One set

TaC or TiC

C/Ta (Ti)

C Ta Ti

0.44nm 0.82nm 0.8nm

Multi-stacking of Metal/Carbon layers

Easily control of carbon content

28

TaC and TiC with small grain size can be obtained

(3.2 and 3.9 nm, respectively)

Formation of TaC and TiC

Temperature (oC)

Ti/C

Ta/C

0 200 400 600 800 1000

100

200

500

400

300

0

sh

(/s

q.)

SiO2

・・・

Si

Ti

Ti

C

C

SiO2

・・・

Si

C

CTa

Ta

Log (

cou

nts

) 30 40 50 60 70 9080

-2 (deg)

TaC 750oC

TaC 500oC

TiC 500oC

29

Comparing with powder diffraction database

Random orientation is assumed, preferred orientation of (220)

and (311) planes can be confirmed for TiC and TaC layers.

30

Work function of Metal carbides

A high effective work function (WF) of 4.9 eV was

extracted for W2C.

High WF can be attributed to oriented grain growth

SiO2 thickness (nm)

Vfb

(V)

0 105 15 2520

0.8

-0.4

1.0

0.6

0.4

0.2

0.0

-0.2

TaC (750oC)

W2C (750oC)

TiC (500oC)

m,TaC=4.7eV

m,TiC=4.3eV

m,W C=4.9eVm,W C=4.9eV2

SiO2

Si sub.

Metal gate

31

Yes; <001>//sub.

No

No

No

Yes; <100> sub.

No

Oriented growth

CVD

this workSput.+Reaction1.9 nmW2C

Sput.+Reaction

Sput.+Reaction

CVD

Sput.

Process

this work

this work

[6]

[5]

Ref.

3.2 nm

3.9 nm

9.2 nm

22 nm

Grain size

TaC

TiC

TaN

TiN

Metal gate

Yes; <001>//sub.

No

No

No

Yes; <100> sub.

No

Oriented growth

CVD

this workSput.+Reaction1.9 nmW2C

Sput.+Reaction

Sput.+Reaction

CVD

Sput.

Process

this work

this work

[6]

[5]

Ref.

3.2 nm

3.9 nm

9.2 nm

22 nm

Grain size

TaC

TiC

TaN

TiN

Metal gate

1. A novel sputtering process to form W2C at low temperature

2. A grain size of 1.9 nm can be obtained with W2C gate

3. Oriented growth of W2C can be obtained easily

Conclusions of chapter 3

A. Yagishita,

TED, 2001

M. H. Tsai, APL, 1995

Originality

32

I. Introduction

II. Device fabrication process and characterization method

III. Metal carbides for gate electrodes application

(propose a novel process for metal carbide)

VI. Conclusion

V. Reliability of La-silicate

high-k with tungsten

carbide gate electrodes

IV. Electrical properties

of La-silicate high-k with

tungsten carbide gate

electrodes

Dissertation outline

33

Devices fabrication process

W/C multi-stacking layer

Gate patterning (RIE)

SPM and HF cleaning

TiN and Si deposition by RF sputtering

n-Si(100) wafer (Na=1015cm-3)

La2O3 deposition(300oC) by EB

Annealing at 800 oC for 30min to form W2C

Backside Al contact

FGA at 420 oC for 30min

Si removal by TMAH

Si sub.

La2O3

W/C 18sets

TiN

Si

Si sub.

La-silicate

W2C

TiN

Si

W2C and La-silicate both formed at the same time

34

Capacitance-voltage characteristics

Comparable EOT;

little difference in silicate reaction rate

35

Dit and Vfb dependency on EOT

EOT (nm)

W2C gate

W gate

Dit

(cm

-2/e

V)

x1011

10

4

12

8

2

0

6

0.65 0.900.800.70 0.850.75

0.0

Vfb

(V)

EOT (nm)0.65 0.900.800.70

-0.1

-0.2

-0.3

-0.4

W2C gate

W gate

0.850.75

Qfix=1010/cm2

Constant Vfb by W2C gate electrode; no difference in defect

creation

Large improvement in interface state density with W2C gate

electrode in all the studied EOT range

36

TEM images with W2C gate electrode

W/La-silicate/n-Si W2C/La-silicate/n-Si

Atomically flat metal/high-k (Ra=0.26nm) and high-k/Si

(Ra=0.12nm) interfaces can be obtained with W2C

gate electrode

Comparable to bare Si wafers

37

Stress in Si substrate

A large stress presented below La-silicate layer down to

several hundreds deep in Si substrate with W gate

W/La-silicate/n-Si W2C/La-silicate/n-Si

100nm 100nm

No apparent stress with W2C gate

38

FFT analysis of the interface position

Spatial frequency corresponding to period of 20 nm,

comparable to the grain size of W gate electrode is

suppressed with nano-sized grain W2C gate electrode

0

5

2

4

3

1

0.20.050.01 0.1 0.5

Pow

er

spectr

al

density (

a.u

.)

Spatial frequency (nm-1)

distance (nm)20 1033

W gate

W2C gate

50 25 14

39

Reports on stress induced reaction

Tensile stress to increase the reaction; compressive

stress to decrease the reaction

Reaction rate change due to applied stress can be

interpreted as change in activation energy

High possibility that silicate reaction rate can be

modified under applied stress

Solid-phase epitaxy of amorphous Si on crystalline Si

40

Mechanism of roughness formation

During annealing

processas-depositedLa-silicate formation

completed

Si sub.

La2O3

W gate

Si sub.

La2O3

W2C gate

La-silicate

La-silicate

Stress induced by grains

W gate

electrode

W2C gate

electrode

Nano-sized grains help elimination of inhomogeneous

stress applied to the interface to form uniform La-

silicate gate dielectrics

41

Explanation of Dit-EOT relation

EOT

Dit

0 1nm

Less stress during silicate reaction,

owing to metal gate with nano-sized

grains

Effect of stress from metal gate to roughen

the La-silicate/Si interface

Inhomogeneous stress applied to the Si surface during

reaction can be eliminated by W2C gate electrode with

oriented nano-sized grains

42

0

20

40

60

80

100

120

140

160

180

200

0 0.15 0.3 0.45 0.6 0.75

100

120

140

160

180

200

220

240

0.4 0.6 0.8 1 1.2

L/W=10/10m

ef

f(c

m2/V

sec)

EOT (nm)

TiN/W2C/La-silicate/nFET

EOT~0.75nmef

f(c

m2/V

sec)

Eeff (MV/cm)

W:C=1:0.5

W:C=1:1

W:C=1:0.5

Electrical characteristics of MOSFET

Higher effective mobility of 163cm2/V.s with small EOT=0.63nm

were achieved by W2C gate electrode

43

A benchmark fo high-field electron mobility

W2C gate with La-silicate gate stack exhibit higher

eff beyond the eff-EOT trend line

Conclusion of chapter 4

High eff with atomically flat metal/high-k and high-k/Si

interfaces can be achieved with reactively formed La-silicate

and highly-oriented W2C gate electrodes.

This

work0.12 nm0.26 nm163 cm2/Vs0.63 nm

Oxygen controled reacitveformation with oriented nano-sized W2C grains

(W2C/La-silicate)

0.62 nm

0.55 nm

0.59 nm

EOT

155 cm2/Vs

140 cm2/Vs

130 cm2/Vs

Mobility

at 1MV/cm

0.36 nm

0.54 nm

0.50 nm

High-k/Si

interface

roughness

[7]

[11]

[10]

Ref.

0.61 nm

0.66 nm

0.46 nm

Metal/high-k

interface

roughness

Oxygen controled

reacitve formation

(W/La-silicate)

IL scavenging by

metal incorporation

(TaN/cap/HfO2)

Oxygen controled

deposition (HfO2)

Process for

direct high-k/Si

This

work0.12 nm0.26 nm163 cm2/Vs0.63 nm

Oxygen controled reacitveformation with oriented nano-sized W2C grains

(W2C/La-silicate)

0.62 nm

0.55 nm

0.59 nm

EOT

155 cm2/Vs

140 cm2/Vs

130 cm2/Vs

Mobility

at 1MV/cm

0.36 nm

0.54 nm

0.50 nm

High-k/Si

interface

roughness

[7]

[11]

[10]

Ref.

0.61 nm

0.66 nm

0.46 nm

Metal/high-k

interface

roughness

Oxygen controled

reacitve formation

(W/La-silicate)

IL scavenging by

metal incorporation

(TaN/cap/HfO2)

Oxygen controled

deposition (HfO2)

Process for

direct high-k/Si

Conclusion of chapter 4

1. Low Dit of 2.5x1011 cm-2/eV was achieved with EOT of 0.75nm

2. Atomically flat W2C/La-silicate, La-silicate/Si interfaces

3. Origin of Dit is due to La-silicate/Si interface roughness due to

grains in metal gate electrode

Originality and findings

Metal gate with nano-sized grain is effective for direct

high-k/Si contact with low Dit

46

I. Introduction

II. Device fabrication process and characterization method

III. Metal carbides for gate electrodes application

(propose a novel process for metal carbide)

VI. Conclusion

V. Reliability of La-silicate

high-k with tungsten

carbide gate electrodes

IV. Electrical properties

of La-silicate high-k with

tungsten carbide gate

electrodes

Dissertation outline

47

Reliability measurement

Si sub.

La-silicate

W

TiN

Si sub.

La-silicate

W2C

TiN

800oC, FG ambient, 30min

48

Reliability measurement by PBTI

Stress time (s)

0.001

1 10 100 1000 10000

0.1

0.01

1

DV

fb(V

)

W : ≃0.28

W2C : ≃0.39

W2C Vs=1.7(V)

W2C Vs=1.8(V)

W2C Vs=1.9(V)

W Vs=1.7(V)

W Vs=1.8(V)

W Vs=1.9(V)

W2C Vs=1.7(V)

W2C Vs=1.8(V)

W2C Vs=1.9(V)

W Vs=1.7(V)

W Vs=1.8(V)

W Vs=1.9(V)

EOT=0.75nm

RT

W

W2C

DVfb= DVmax(1-exp[-(t/t0)])

Better reliability with W2C gate electrode owing to

atomically flat high-k/Si interface

: hydrogen diffusion dispersion

0<<1

The dispersion decrease as

increase

t: degradation rate

DVmax: maximum shift

49

Conclusion of chapter 5

Structure Ref.

SiO2/Si 1 S. Zafer, VLSI, 2006

TiN/HfO2/SiON/n-Si 0.16~0.19 A. Kerber, Tran. On

Device and Materials

reliability, Vol. 9, 2009

TiN/W/La-silicate/n-Si 0.27 This work

TiN/W2C/La-silicate/n-Si 0.39 This work

Better reliability with W2C gate electrode can be

obtained owing to atomically flat high-k/Si interface

50

I. Introduction

II. Device fabrication process and characterization method

III. Metal carbides for gate electrodes application

(propose a novel process for metal carbide)

VI. Conclusion

V. Reliability of La-silicate

high-k with tungsten

carbide gate electrodes

IV. Electrical properties

of La-silicate high-k with

tungsten carbide gate

electrodes

Dissertation outline

51

4. W2C has large advantages in terms of grain size and

oriented growth for scaled devices

Conclusions of thesis

III. Metal carbides for gate electrodes application

1. A novel stacked carbon/metal process was introduced and

formation of carbides were confirmed

2. Grain sizes of the carbides are as small as 3.9, 3.2, and 1.9nm

for TiC, TaC, and W2C, respectively

3. Work functions of TiC, TaC and W2C layers have been

extracted as 4.3, 4.7, and 4.9 eV, respectively

52

2. Atomically flat metal/high-k and high-k/Si interfaces

can be obtained by W2C gate electrode

Conclusions of thesis

IV. Electrical properties of La-silicate high-k with tungsten

carbide gate electrodes

1. Interface state density was suppressed by W2C gate

electrode

3. Inhomogeneous strain in Si substrate was eliminated

by W2C gate electrode

4. Higher effective mobility of 163cm2/V.s with small EOT

0.63nm were achieved by W2C gate electrode

5. Origin of Dit is due to La-silicate/Si interface roughness

due to grains in metal gate electrode

53

Better reliability with W2C gate electrode can be obtained

owing to atomically flat high-k/Si interface

Conclusions of thesis

V. Reliability of La-silicate high-k with tungsten carbide

gate electrodes

54

Approaches and Originality

2. The effect of metal gate on bottom high-k/Si interface

have been experimentally investigate

4. Reliability of La-silicate have been improved by nano-grain

sized metal gate owing to atomically flat high-k/Si interface

1. Oriented growth of W2C with 1.9nm grain size can be

obtained easily at low temperature

3. Metal gate with nano-sized grain is effective for direct

high-k/Si contact with low Dit and flat interface

55

Publication and PresentationJournals

1. K. Tuokedaerhan, R. Tan, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N.

Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, Stacked sputtering

process for Ti, Ta, and W carbide formation for gate metal application, Appl. Phys.

Lett., Vol. 103, 11908, 2013.

2. K. Tuokedaerhan, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.

Wakabayashi, K. Tsutsui, K. Natori, and H. Iwai, Atomically flat La-silicate/Si

interface using tungsten carbide gate electrode with nano-sized grain, under

reviewing process at Appl. Phys. Lett. Vol. 104, 021601, 2014.

Presentation at international conference and symposium

1.K. Tuokedaerhan, S. Hosoda, Y. Nakamura, K. Kakushima, Y. Kataoka,

A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, and H. Iwai,

Influence of carbon incorporation in W gate electrodes for La-silicate gate dielectrics,

IWDTF-13, University of Tsukuba, Japan, November 7-9, 2013.

2. K. Tuokedaerhan, R. Tan, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama,

N. Sugii, K. Tsutsui , K. Natori, T. Hattori, H. Iwai. Interface properties of La-silicate

MOS capacitors with tungsten carbide gate electrode for scaled EOT.

222nd ECS Meeting, Hawaii, USA, October 10, 2012.

56

Publication and Presentation

3. K. Tuokedaerhan, S. Hosoda, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama,

N. Sugii, K. Natori, T. Hattori, H. Iwai. Work Function Extraction of W, Ta and

Ti Carbides Formed by Multi Stacked Process. IEEE EDS WIMNACT-37,

Tokyo Institute of Technology, Japan, February 18, 2013.

4. K. Tuokedaerhan, T. Kaneda, M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui,

A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai. Impact of annealing ambient for

La2O3/Si capacitor. G-COE PICE international symposium and IEEE EDS mini

colloquium on Advanced Hybrid Nano Devices: Prospects by World’s Leading

Scientists. Tokyo Institute of Technology, Japan, October 4-5, 2011.

5. K. Tuokedaerhan, S. Hosoda, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii,

H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai. Mobility improvement of La-silicate

MOSFET by W2C gate electrode, WIMNACT 39, Tokyo Institute of Technology,

Japan, February 7, 2014.

57

Publication and Presentation

Presentation at domestic conference

1. K. Tuokedaerhan, T. Kaneda, M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui,

A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai. Effects of post deposition

annealing on electrical characteristics of MOS device with La2O3/n-Si structure,

The 72th JSAP Autumn Meeting, the Japan society of Applied Physics,

Yamagata University, September 1, 2011.

2. K. Tuokedaerhan, Y. Tanaka, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama,

N. Sugii, K. Tsutsui , K. Natori, T. Hattori, H. Iwai. Work function measurement of

C/W stacked structure on SiO2 gate dielectrics. The 59th JSAP Spring Meeting,

the Japan society of Applied Physics, Waseda University, March 18, 2012.

3. K. Tuokedaerhan, R. Tan, S. Hosoda, K. Kakushima, P. Ahmet, Y. Kataoka,

A. Nishiyama, N. Sugii, K. Tsutsui , K. Natori, T. Hattori, H. Iwai. Influence of

Si/TiN capped annealing on the interfacial properties of W2C/La-silicate/n-Si

capacitors for EOT scaling. The 73th JSAP Autumn Meeting, the Japan society

of Applied Physics, Ehune University/ Matsuyama University, September 12, 2012.

58

Back up

59

Amorphous La-silicate with large band gap

10 15 25 30

-2 (deg)20

Inte

nsity (

a.u

.)

Si sub.h=15keV, GIXD

900oC

500oC

544 540 532 528

Binding energy (eV)536

La-O-LaLa-O-SiSi-O-Si

700oC

as-depo.

300oC

500oC

5.54eV

5.58eV

5.52eV

6.17eV

hex-La2O3

Eg (eV) Structure

La2O3 5.5~5.6 hexagonal

La-silicate 6.2 amorphousLa-silicate amorphous

C(20nm)/La2O3(4nm)/n-Si

K. Kakushima, ゲートスタック研究会資料 (2012)

60

Scaling issues for La-silicates

Mobility degradation trend with EOT scaling

T. Ohmi, IEEE Trans. ED, 1992

220

200

180

160

140

120

Ele

ctr

on

Mo

bili

ty [

cm

2/V

se

c]

10.90.80.70.60.5EOT [nm]

at 1MV/cm

T = 300K

Open : HfO2 ref [?]

Fill : La-silicate ref [?]

T. Kawanago, IEEE Trans. ED, 2012

61

Metal with small grains or amorphous metal

M. E. Grubbs, Appl. Phys. Lett., 223505 (2010)

Ta40W40Si10C10Ru30Mo70

K. Ohomori, IEDM, 409 (2008)

amorphous metal small grain size (<10nm)

XRD

plan TEM

Amorphous up to 1120 oC

Complex deposition system (4 elements)

Composition control (depth profile)

Simple process (2 elements)

Variability in grain size

Our approach

We attempt to use W2C with grain size (<2nm) as metal gate electrodes

62

Metal material candidates for La-silicate

・Metal layer should contain proper oxygen atoms for

silicate reaction

TiN, TaN do not contain oxygen, they react to form TiOx, TaOx, instead

・Metal atoms should not diffuse into La-silicate layer

Avoid degradation of metal/high-k interface and fixed charge generation

Base upon the above conditions with requirements

on metal gate for scaled devices, carbides can be

strong candidates (W carbides, Mo carbides)

63

64

h-W2C

20nm

columnar growth

W2C/SiO2

Ra=0.30nm

surface

Ra=0.64nm

<001><001> h-W2C

<110><100>

SiO2

growth

direction

h-W2C

growth

direction

65

S. Ogata, et al.,

APL, 98,

092906 (2011)

Surface orientations strongly affect interface state density.

66

EOT

eff

0

67

Electrical characteristics of MOSFET

Higher effective mobility of 163cm2/V.s with small EOT=0.63nm

were achieved by W2C gate electrode

0.0 0.2 0.6 0.8 1.00.4

Vd (V)

Ids (

A)

0.0E+00

L/W=10/10m

Vg= 0 to 1V

5.0E-05

1.0E-04

1.5E-04

2.0E-04

2.5E-04

3.0E-04