a study on qpsk modulator architectures for ultra low

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

A Study on QPSK Modulator Architectures for UltraLow Power Transmitters

Examensarbete utfört i Elektroniska komponentervid Tekniska högskolan i Linköping

av

Per Eidenvall, Nils Gran

LiTH-ISY-EX--10/4357--SE

Linköping 2010

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

A Study on QPSK Modulator Architectures for UltraLow Power Transmitters

Examensarbete utfört i Elektroniska komponentervid Tekniska högskolan i Linköping

av



Handledare: Atila Alvandpour, Linköpings universitet

Examinator: Atila Alvandpour, Linköpings universitet

Linköping, 22 November, 2010

Avdelning, InstitutionDivision, Department

Division of Electronic DevicesDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

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2010-11-22

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URL för elektronisk versionhttp://www.ek.isy.liu.se

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-62656

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TitelTitle A Study on QPSK Modulator Architectures for Ultra Low Power Transmitters

FörfattareAuthor


SammanfattningAbstract

Today, medical implants such as cardiac pacemakers, neurostimulators, hearing aids anddrug delivery systems are increasingly more important and frequently used in the health caresystem. This type of devices have historically used inductive coupling as communicationmedium. New demands on accessibility and increased performance in technology drives newresearch toward using radio communications. The FCC MICS radio standard are specificallydevoted for implantable devices.

Basically all published research on transmitters in this area are using frequency shift keying(FSK) modulation. The purpose of this thesis is to explore the viability of using phase shiftkeying (PSK) modulation in ultra low power transmitters and suggest suitable architectures.

NyckelordKeywords Ultra Low Power, MICS, PSK, QPSK, Radio Transmitter, QPSK Modulator

AbstractToday, medical implants such as cardiac pacemakers, neurostimulators, hearing

aids and drug delivery systems are increasingly more important and frequentlyused in the health care system. This type of devices have historically used in-ductive coupling as communication medium. New demands on accessibilityand increased performance in technology drives new research toward using ra-dio communications. The FCC MICS radio standard are specifically devoted forimplantable devices.

Basically all published research on transmitters in this area are using frequencyshift keying (FSK) modulation. The purpose of this thesis is to explore the viabilityof using phase shift keying (PSK) modulation in ultra low power transmitters andsuggest suitable architectures.

v

Acknowledgments

We would like to thank:

Atila Alvandpour, ProfessorHåkan Bengtsson at Zarlink Semiconductor Inc.Amin Ojani, Ph.D. studentJonas Fritzin, Ph.D. studentJohan Bengtsson

for their help in this thesis

Per Eidenvall and Nils Gran

vii

Contents

Abbreviations and Acronyms xv

1 Introduction 11.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5 Delimitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.5.1 High Level Architectures . . . . . . . . . . . . . . . . . . . . 21.5.2 Mixer-Less Architectures . . . . . . . . . . . . . . . . . . . . 31.5.3 MICS Standard . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.6 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.7 Report Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Related Theory 52.1 Quadrature detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Spectrum, Power and Data Rate . . . . . . . . . . . . . . . . . . . . . 7

2.2.1 Power and Bit Error Rate . . . . . . . . . . . . . . . . . . . . 72.2.2 Theoretical limits on data rate . . . . . . . . . . . . . . . . . . 9

2.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.4 Minimum Tone Spacing for Orthogonal FSK . . . . . . . . . . . . . 13

2.4.1 Orthogonal FSK and Coherency . . . . . . . . . . . . . . . . 132.4.2 Alternative Approach to non-Coherent Orthogonal FSK . . 15

2.5 Spectral Regrowth Issues . . . . . . . . . . . . . . . . . . . . . . . . . 152.6 Constant Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.1 Frequency Modulation . . . . . . . . . . . . . . . . . . . . . . 172.6.2 Phase Modulation . . . . . . . . . . . . . . . . . . . . . . . . 19

3 A Brief Overview of Current Architectures 213.1 A Brief Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1.1 Distributed Frequency Correction . . . . . . . . . . . . . . . 213.1.2 Frequency Multiplying Power Amplifier . . . . . . . . . . . 223.1.3 Direct VCO Modulation Using Low Supply Voltage . . . . . 22

3.2 65 nm Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.3 Concluding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ix

x Contents

4 The MICS Standard and PSK Bandwidth Efficiency Issues 274.1 MICS Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.1 MICS Transmitter from Paragraph §95.628 . . . . . . . . . . 274.1.2 Emission Types from Paragraph §95.631 . . . . . . . . . . . . 284.1.3 Emission bandwidth from Paragraph §95.633 . . . . . . . . . 284.1.4 Unwanted Radiation from Paragraph §95.635 . . . . . . . . 284.1.5 Maximum Transmitted Power from Paragraph §95.639 . . . 294.1.6 Additional Power Constraint from Paragraph §95.649 . . . . 294.1.7 Crystal Control Requirements from Paragraph §95.651 . . . 294.1.8 Resulting Spectral Mask . . . . . . . . . . . . . . . . . . . . . 29

4.2 PSK Bandwidth Efficiency Issues . . . . . . . . . . . . . . . . . . . . 30

5 Testbenches 335.1 Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1.1 PSK Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.1.2 FSK Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345.3 Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6 Designed Architectures 396.1 PSK Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.1.1 Simple QPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . 396.1.2 PLL Based QPSK Modulation . . . . . . . . . . . . . . . . . . 396.1.3 PLL Based QPSK Modulation with Dither . . . . . . . . . . . 416.1.4 Direct Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . 43

6.2 FSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7 Simulation Results 477.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.2 Unfiltered QPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487.3 PLL Based QPSK Modulation . . . . . . . . . . . . . . . . . . . . . . 487.4 PLL Based QPSK Modulation with Dither . . . . . . . . . . . . . . . 517.5 Direct Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8 Conclusion 558.1 Evaluating the Results . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1.1 PLL Based Modulator . . . . . . . . . . . . . . . . . . . . . . 558.1.2 PLL Based Modulator with Dither . . . . . . . . . . . . . . . 568.1.3 Direct Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . 56

8.2 Final Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Bibliography 59

Contents xi

List of Tables

3.1 Summary of power consumption. . . . . . . . . . . . . . . . . . . . . 243.2 Overview of ten ultra-low power radio transmitters. . . . . . . . . . 253.3 Ten ultra-low power radio transmitters ordered by energy per bit. . 263.4 PA efficiency for ultra-low power transmitters. . . . . . . . . . . . . 26

4.1 Attenuation of signal 250 kHz outside the MICS band. . . . . . . . 28

6.1 Parameter values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1 Additional hardware needed in PSK modulation. . . . . . . . . . . 57

xii Contents

List of Figures

2.1 Quadrature detector block diagram. . . . . . . . . . . . . . . . . . . 62.2 Examples of IQ-diagram. a) Constellation diagram, b) Transition

diagram, c) Constellation diagram with phase shift, d) Constella-tion diagram of 16-QAM and e) Constellation diagram of 16-QAMwith gain compression. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Illustration of the interdependency between power, bandwidth anddata rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Quadrature PSK architecture using Raised Cosine pulse shaping. . 82.5 BER for BPSK, QPSK, coherent BFSK and non-coherent BFSK as a

function of Eb/n0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.6 BER for multi-valued FSK and PSK . . . . . . . . . . . . . . . . . . . 112.7 Second order PLL with charge pump. . . . . . . . . . . . . . . . . . 122.8 Minimum frequency separation for non-coherent FSK signaling. . . 152.9 Low-pass time domain filtering of the baseband signal. . . . . . . . 162.10 Unfiltered and filtered QPSK waveforms. . . . . . . . . . . . . . . . 162.11 Analog frequency modulation waveform. . . . . . . . . . . . . . . . 172.12 Discontinuous and continuous FSK waveforms . . . . . . . . . . . . 182.13 Continuous and discontinuous phase architectures. . . . . . . . . . 182.14 Constellation diagrams of QPSK, π/4-DQPSK, OQPSK and MSK . . 19

3.1 DCO based transmitter with distributed frequency correction. . . . 223.2 Transmitter based on a frequency multiplying edge combiner. . . . 233.3 Direct VCO modulated transmitter. . . . . . . . . . . . . . . . . . . . 233.4 65 nm weak inversion MICS receiver. . . . . . . . . . . . . . . . . . . 24

4.1 In band frequency mask for MICS standard . . . . . . . . . . . . . . 294.2 QPSK and MSK Spectrum . . . . . . . . . . . . . . . . . . . . . . . . 304.3 Unfiltered QPSK spectra using RBW of 3 kHz. . . . . . . . . . . . . 31

5.1 PSK demodulator block diagram. . . . . . . . . . . . . . . . . . . . . 345.2 Block diagram of non-coherent FSK demodulator . . . . . . . . . . 355.3 Signal after mixer stage. . . . . . . . . . . . . . . . . . . . . . . . . . 365.4 Eye diagram used for timing of reset and sample-and-hold control

signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365.5 Test methodology for determining the SNR given a certain data rate. 38

6.1 Switch based QPSK with discontinuous output. . . . . . . . . . . . 406.2 Basic PLL architecture modified with quadrature feed back. . . . . 406.3 Basic PLL architecture with quadrature feed back. . . . . . . . . . . 416.4 Functional block diagram over the shaping logic. . . . . . . . . . . . 426.5 Direct multiplexing between multiple phases. . . . . . . . . . . . . . 446.6 How symbol changes are performed when only one (a) or both (b)

bits are changed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456.7 FM modulator based FSK architecture. . . . . . . . . . . . . . . . . . 45

Contents xiii

7.1 Plot of the Eb/n0, the ratio between required energy per bit and thesingle ended thermal noise, using the bandwidth containing 98%of the signal power. The gray bands represent the theoretical Eb/n0for coherent and non-coherent FSK. . . . . . . . . . . . . . . . . . . . 48

7.2 IQ and phase diagram for simple QPSK architecture, phase diagramfor a data rate of 80 kbit/s. . . . . . . . . . . . . . . . . . . . . . . . . 49

7.3 Frequency spectrum of QPSK transmitted at 80 kbit/s. . . . . . . . . 497.4 IQ and phase diagram for PLL architecture, phase diagram for a

data rate of 150 kbit/s. . . . . . . . . . . . . . . . . . . . . . . . . . . 507.5 Frequency spectrum of the PLL-shaped QPSK signal. . . . . . . . . 507.6 IQ and phase diagram for PLL with dither based architecture, phase

diagram for a data rate of 250 kbit/s. . . . . . . . . . . . . . . . . . . 517.7 Ramp-up ratio for PLL based modulation with dither. . . . . . . . . 517.8 Frequency spectrum of the PLL- and dither-shaped QPSK signal. . 527.9 IQ and phase diagram for direct multiplexing architecture, phase

diagram for a data rate of 250 kbit/s. 4 intermediate steps areshown in (a) and (b) and 8 are shown in (c) and (d). . . . . . . . . . 53

7.10 Ramp-up ratio for the direct multiplexing architectures. . . . . . . . 537.11 Frequency spectrum for the direct multiplexing architectures. . . . 54

8.1 Graph showing what data rates could be considered for whicharchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

xvi Abbreviations and Acronyms

Abbreviations and Acronyms

Acronyms ExplanationADS Advanced Design System (Agilent)AWGN Additive White Gaussian Noisebps Bit Per SecondCB Radio Citizens Band RadioCoherent detection Phase aligned- or synchronized detectionCPFSK Continuous Phase Frequency Shift KeyingCPM Continuous Phase ModulationDCO Digital Controlled OscillatorDQPSK Differential Quadrature Phase Shift KeyingEIRP Equivalent Isotropically Radiated PowerFLL Frequency Locked LoopFRS Family Radio ServiceFSK Frequency Shift KeyingFSM Finite State MachineGMSK Gaussian Minimum Shift KeyingI In-phase SignalLO Local OscillatorLPRS Low Power Radio ServiceMICS Medical Implantable Communications SystemMSK Minimum Shift KeyingMURS Multi-Use Radio ServiceOQPSK Offset Quadrature Phase Shift KeyingPA Power AmplifierPFD Phase Frequency DetectorPLL Phase Locked LoopPSK Phase Shift KeyingQ Quadrature SignalQAM Quadrature Amplitude ModulationQPSK Quadrature Phase Shift KeyingR/C Radio Control (also Radio Control Radio Service)RBW Resolution BandwidthRF Radio FrequencyROM Read Only MemorySNR Signal to Noise RatioVCO Voltage Controlled OscillatorWMTS Wireless Medical Telemetry Service

Chapter 1

Introduction

This chapter presents the introduction of the thesis. The introduction describes thepurpose, background, goal, method and delimitations and gives a report outline.

1.1 Purpose

The division of Electronic Devices at the Department of Electrical Engineeringat the Linköping University has a long history of researching and working withhigh-speed and low power CMOS devices. Recently the division has turned focustoward ultra-low power radio transmitters used in e.g. medical implants. Todaybasically all published research on transmitters in this area are using frequencyshift keying (FSK) modulation. The purpose of this thesis is to explore the viabilityof using phase shift keying (PSK) modulation in ultra-low power transmitters andsuggest suitable architectures.

1.2 Background

Today medical implants such as cardiac pacemakers, neurostimulators, hearingaids and drug delivery systems are increasingly more important and frequentlyused in the health care system. The implant must be able to communicate withthe outside world to enable evaluation and configuration of its performance andto study medical events that a patient is experiencing or has experienced. Tra-ditionally communication, i.e. transmission of information, was carried out bymagnetic coupling1 [19]. With magnetic coupling a reader/transmitter head mustin general be placed directly on the patients skin in the absolute proximity of theimplant. The reading of data from the device takes relative long time. The datarate could range about 50 kbit/s [19] over a distance of only a few inches. Thebenefit of using magnetic coupling is the relatively low power consumption.

1Also often referred to inductive coupling.

1

2 Introduction

Today new demands on accessibility and advances in technology drive theattention toward radio transmission instead of magnetic coupling. Radio hasthe benefit of higher data rates and longer transmission distances. Radio is notaffected by electromagnetic interference which inductive coupling is. Therebythe safety of the patient is improved. The major challenge is however to achievethe same low power consumption as the magnetic coupling. Because of thedifficulty of changing or recharging the power source of medical implants, thepower consumption is a major issue.

1.3 Goal

The goals of this thesis are:

1. Provide a summary on current ultra-low power transmitters for the MICSstandard in terms of modulation scheme, power consumption, data rate andoutput power.

2. Suggest high level, mixer-less, PSK architectures relevant for future work.

3. Describe the benefits and drawbacks of using PSK in ultra-low power trans-mitters used in compliance with the MICS standard.

1.4 Method

In order to achieve the goals presented in the previous section 1.3, a method hasbeen designed. The method is divided into the following three phases.

Phase 1: Perform a literature study on current ultra-low power designs to gatherspecifications and give inspiration for new ideas to be used in the next phase.The study should be based on the most relevant IEEE papers.

Phase 2: Design and implement mixer-less high level phase shift keying architec-tures for computer simulations in ADS.

Phase 3: Simulate and evaluate the implemented PSK architectures.

1.5 Delimitations

1.5.1 High Level Architectures

This thesis is restricted to the investigation and design of high level phase-shift-keying architectures for simulation in ADS viable for ultra-low power operation.Hence, this thesis does not give any suggestions or examples of on chip imple-mentations. This is left for future work.

1.6 Tools 3

1.5.2 Mixer-Less Architectures

At the beginning of the work a decision was made to focus on mixer-less architec-tures. Mixers typically require linear signal paths both at their inputs and outputswhen used in PSK transmitters with phase shaping. This also affects the powerconsumption of the power amplifier since linear PA:s tends to consume morepower than their non-linear counterpart. Mixers were also recognized as a maincontributor to the global power consumption. For these reasons it was decidedto narrow the field and focus on mixer-less architectures.

1.5.3 MICS Standard

The MICS standard has become the major radio standard for medical implantssince FCC introduced it in 1999 (see chapter 4). Most current papers on ultra-lowpower radio transmitters for medical implants states that they conform to theMICS standard to some degree. This thesis will for this reason focus primarily onPSK transmitters complying with the MICS standard.

1.6 Tools

The following tools has been used during the work:

ADS 2009 Advanced System Design from Agilent has been the main tool duringthe work. All architectural models have been designed and simulated inADS. Ptolemy functional blocks, i.e. blocks from the DSP design type, havebeen used when possible in order to minimize simulation time.

Matlab 7.7.0 (R2008b) Matlab has been used for verifying our models used inADS and calculating appropriate input parameters. Matlab has also beenused to generate many of the plots in the thesis. Appart from standardfunctions, functions from the System Toolbox have been used.

1.7 Report Outline

Chapter 1 presents the introduction of the thesis. The introduction describes thepurpose, background, goal, method and delimitations and gives a reportoutline.

Chapter 2 cover some of the basic theory related to this thesis. The chapterdiscuss: common trade-off issues in radio frequency (RF) design related tobandwidth, power and data rate; frequency synthesis using charge pumpbased phase locked loops; minimum tone spacing in FSK systems; spectralregrowth issues and constant envelope behavior. The chapter is foremostintended for the novice RF reader.

4 Introduction

Chapter 3 presents an overview of ten low-power transmitters, a description ofthe three most power-efficient architectures and a short discussion on using65 nm technology in MICS applications.

Chapter 4 presents a summary of the Medical Implantable Communications Ser-vice (MICS) radio standard introduced by Federal Communications Com-mission (FCC). It also points out bandwidth efficiency issues for PSK mod-ulation complying to the MICS standard, which will be a major challengethroughout the thesis.

Chapter 5 describes the two testbenches used during simulations, the availablemeasurements and the test methodology.

Chapter 6 presents the architectures designed and simulated during the thesis.A short description of the idea leading up to each architecture is also givenalong with some brief details of the implementation.

Chapter 7 summarizes the performance of the simulated architectures. The pre-sented measurements includes: phase- and IQ-transition characteristics;Eb/n0 and ramp up ratio for different data rates. Conclusions from theresults are discussed in chapter 8.

Chapter 8 presents the conclusions made from the simulations and the overviewof architectures presented in chapter 3.

Chapter 2

Related Theory

This chapter cover some of the basic theory related to this thesis. The chapterdiscuss: common trade-off issues in radio frequency (RF) design related to band-width, power and data rate; frequency synthesis using charge pump based phaselocked loops; minimum tone spacing in FSK systems; spectral regrowth issuesand constant envelope behavior. The chapter is foremost intended for the noviceRF reader.

2.1 Quadrature detection

One common QPSK receiver architecture is the quadrature detector, see figure 2.1.The received signal is down converted by a mixer using a phase aligned oscillator.Using the trigonometric function

cos(a) cos(b) =cos(a − b) + cos(a + b)

2(2.1)

the output from the upper mixer in figure 2.1 will be

cos(ωt + ϕ) cos(ωt) =cos([ωt + ϕ] − [ωt]) + cos([ωt + ϕ] + [ωt])

2

=cos(ϕ) + cos(2ωt + ϕ)

2

(2.2)

and in the same way the output from the lower mixer will be

cos(ωt + ϕ) cos(ωt + π/2) =cos(ϕ + π/2) + cos(2ωt + ϕ + π/2)

2

=sin(ϕ) + sin(2ωt + ϕ)

2

(2.3)

The output from the mixers hence contain one high frequency componentand one DC component proportional to the phase of the incoming signal. Since

5

6 Related Theory

in phase-modulation, the data is carried in the phase of the transmitted signalthe high frequency component is filtered out with a low pass filter. The DCcomponent is then integrated over one symbol time to filter out noise added bythe channel before it is sampled and converted into a digital value.

LO

+90°

I {0,1}

Q {0,1}

Reset Sample&hold

Figure 2.1: Quadrature detector block diagram.

IQ diagram

IQ diagrams can be useful when evaluating radio systems and will be used in thisthesis to evaluate the simulated architectures. An IQ diagram consist of the I andQ values for the demodulated signal. The I value is typically represented by thex-axis and the Q value by the y-axis. If the signal is sampled at discrete symboltimes, the diagram will contain the constellation diagram in figure 2.2 (a). If thesignal is sampled and plotted continuously the IQ diagram will also contain thetransitions between the constellation points as in figure 2.2 (b).

The diagram can show if the transmitter and receiver are not phase alignedas in figure 2.2 (c) and can help when aligning them. IQ diagrams can also beused to view other modulation schemes beside QPSK, see figure 2.2 (d) where thediagram contain the constellation of 16-QAM. It is also possible to view the effectof gain compression in the constellation, see figure 2.2 (e).

(a) (b) (c) (d) (e)

Figure 2.2: Examples of IQ-diagram. a) Constellation diagram, b) Transitiondiagram, c) Constellation diagram with phase shift, d) Constellation diagram of16-QAM and e) Constellation diagram of 16-QAM with gain compression.

2.2 Spectrum, Power and Data Rate 7

2.2 Spectrum, Power and Data Rate

The performance of radio communication systems are limited by the availablefrequency spectrum, power supply and the data rate. These three componentsare interdependent, hence improving one parameter results in the deteriorationof one or both of the other parameters. Maintaining this interdependency withoutviolating any given specification is a major design challenge in radio communi-cation systems.

Data rateBandwidth

Power

Figure 2.3: Illustration of the interdependency between power, bandwidth anddata rate.

The majority of the power consumption in radio transmitters are usuallycaused by the operation of the power amplifier. This is not necessarily the casein ultra-low power transmitters since the relative output power is very low1

compared to common transmitters at higher power levels. The global efficiencydeteriorates at these lower signal powers due to the frequency generation andmodulation overhead starts to compete with power amplifier dissipation. Forthis reason special care has to be taken in the design of the frequency synthe-sis and base band modulation in order to maintain an “ultra” low global powerconsumption. Hence common competitive transmitter architectures like e.g. theQuadrature Raised Cosine architecture depicted in figure 2.4 are likely to sufferfrom poor global efficiency when used in ultra-low power applications due to itsreliance on linear mixers.

2.2.1 Power and Bit Error Rate

The probability of bit error is directly determined by the signal-to-noise ratio(SNR). A larger signal-to-noise ratio reduces the error probability and vice versa.

SNR =Signal PowerNoise Power

=SN

(2.4)

The error probability is however usually not expressed in terms of signal-to-noise ratio but in terms of energy per bit to the single ended thermal noise densityi.e. Eb/n0. The relation between Eb/n0 and SNR is given by equation (2.5) [7].

1Maximum EIRP at 3 meter distance is according to the MICS standard 25 µW or -16 dBm.

8 Related Theory

LO

+90°

SpectrumAnalyzer

I: {-1,1}

Q: {-1,1}

Sine

Cosine

delay

Figure 2.4: Quadrature PSK architecture using Raised Cosine pulse shaping.

Eb

n0=

STb

n0=

SBRbn0B

=SN

( BRb

)(2.5)

Where Tb is the bit time, Rb = 1/Tb is the bit rate and B denotes the bandwidthin Hz.

The bit error probability for PSK is given by equation (2.6) [7, 6]. Most PSKmodulation schemes requires coherent (phase aligned) detectors2. Equation (2.6)is true for coherent PSK detection3.

Pe_PSKcoherent ' erfc(√

2Eb

n0

)(2.6)

Bit error probability for coherent BFSK is given by equation (2.7) [6] andequation (2.8) [6] gives the bit error probability for non-coherent BFSK.

Pe_BFSKcoherent '12

erfc(√Eb

2

)(2.7)

Pe_BPFSKnon−coherent '12

exp(−

Es

2

)(2.8)

Non-coherent detection is often used in FSK applications since it require a lesscomplex receiver. However, the required signal power for coherent detection islower than for non-coherent detection. Coherent BFSK requires approximately1.5 dB less signal power than non-coherent BFSK for any given bit error rate(BER). The signal power could be reduced even further with BPSK modulation.The total reduction using BPSK is approximately 4.5 dB compared to non-coherentBFSK and approximately 3 dB compared to coherent BFSK. The bit error rates areplotted as a function of Eb/n0 in figure 2.5. Quadrature PSK is a commonly usedform of PSK modulation4. It has a slightly worse SNR but offers higher data rates.

2Some differential PSK schemes are demodulated by non-coherent detectors [7].3All error probabilities in this chapter are calculated for AWGN type channels.4Bit error probability for QPSK is given in equation 2.14.

2.2 Spectrum, Power and Data Rate 9

QPSK needs an Eb/n0 ratio of 8.46 dB when BPSK has an Eb/n0 ratio of 8 dB inorder to maintain the same BER. The difference in required SNR between BPSKand QPSK decreases as the SNR increases.

2 4 6 8 10 12 14

10−8

10−6

10−4

10−2

Eb/no (dB)

Bit

Err

or R

ate

BPSKQPSKCoherent FSKNon−coherent FSK

Figure 2.5: BER for BPSK, QPSK, coherent BFSK and non-coherent BFSK as afunction of Eb/n0

2.2.2 Theoretical limits on data rate

In most cases higher data rates also means a higher bit error rate and widerbandwidth. Hence, bandwidth and bit error rate limits the data rate. In thesection below about the Shannon Capacity Theorem the theoretical limit on datarate is discussed in terms of bandwidth efficiency. A discussion on how data rateaffects the bit error rate for FSK and PSK modulation is presented in the sectionbelow about maximum data rates.

Shannon Capacity Theorem

The bandwidth efficiency is a major criteria when selecting modulation schemes.Bandwidth efficiency is measured in bps/Hz and is defined by equation (2.9) [7]

ηBW =RB

BWbps/Hz (2.9)

10 Related Theory

, where RB is the bit rate transmitted over an AWGN channel and BW is thechannel bandwidth in Hz. The Shannon Capacity Theorem gives the theoreticalmaximum capacity, i.e. the maximum bandwidth efficiency, of a channel for agiven bandwidth and signal-to-noise ratio. The theorem is given in equation(2.10) [7]

ηBWmax =C

BW= log2

(1 +

Signal PowerNoise Power

)bps/Hz (2.10)

, where C is the channel capacity in bps. C is also often referred to as theShannon Limit.

Maximum data rates

Determining the relationship between data rate and bandwidth could lead to aquite lengthy discussion about the definition of bandwidth and how to appropri-ately address base band filtering techniques. The following equations (2.11) and(2.12) are presented without any further discussion on these issues. The equa-tions provides a good basis for discussion about the trade-offs of multi-valuedmodulation schemes [21].

RB_MFSK

BT=

log2(M)(1 + r)M

(2.11)

RB_MPSK

BT=

log2(M)1 + r

(2.12)

Equations (2.11) and (2.12) give the bandwidth efficiency for multivalued FSKand PSK [21]. M denotes the number of symbols used in the modulation schemeand each symbol represents log2(M) number of bits. BT denotes the transmissionbandwidth in Hz, RB is the bit rate in bps and r is a constant related to the filteringtechnique and is typically in the range between 0 and 1.

Describing bandwidth efficiency as a function of the number of symbols (M)used in the modulation scheme gives opposite behavior for FSK and PSK mod-ulation. The bandwidth efficiency for PSK modulation is improved when M isincreased while the bandwidth efficiency is decreased for FSK modulation. De-scribing the bit error probability as a function of the number of symbols also givesopposite behavior for PSK and FSK.

Combining equations (2.7) and (2.13) with figure 2.6 (a) visualizes that the FSKbit error rate is improved when the number of symbols (M) is increased. Equations(2.6), (2.14) and (2.15) gives the behavior of the bit error rate for PSK modulationschemes illustrated in figure 2.6 (b). The bit error rate for PSK modulation isincreased when the number of symbols (M) is increased.

Pe_MFSK 'M − 1

2erfc

(√Eb log2(M)2n0

),M > 2 (2.13)

2.3 Phase Locked Loop 11

2 4 6 8 10 12 1410

−7

10−6

10−5

10−4

10−3

10−2

10−1

100

Eb/no (dB)

Bit

Err

or R

ate

Bit error probability

2 FSK4 FSK8 FSK

(a) Multilevel FSK (MFSK)

2 4 6 8 10 12 1410

−7

10−6

10−5

10−4

10−3

10−2

10−1

100

Eb/no (dB)

Bit

Err

or R

ate

Bit error probability

BPSKQPSK8−PSK

(b) Multilevel PSK (MPSK)

Figure 2.6: BER for multi-valued FSK and PSK

Pe_QPSK ' erfc(√Eb

n0

)[1 −

14

erfc(√Eb

n0

)](2.14)

Pe_MPSK ' erfc(√Eb log2(M)

n0

),M > 4 (2.15)

To conclude this discussion, PSK architectures can improve the bandwidthefficiency by increasing the number of symbols, at the expense of a deterioratedbit error probability. In contrast, when increasing the number of symbols usedby a FSK architecture, the bandwidth efficiency is deteriorated while the bit errorrate is improved.

2.3 Phase Locked Loop

Phase locked loops are a common type of architecture in frequency synthesizers.Phase locked loops are able to lock the output frequency to a reference frequencyby using a negative feedback loop. The ratio between the output frequency andthe reference frequency is determined by placing a frequency divider in the feed-back loop, thus providing a frequency synthesizer. A phase-frequency detectorcompares the divided frequency with the reference frequency and regulates thevoltage level at the input of the voltage controlled oscillator. A stable and accurateoutput frequency is often achieved by using a crystal oscillator for the referencefrequency.

There are several types of frequency dividers. The simplest type is theinteger-N divider that divides the output frequency by an integer N. Frequency

12 Related Theory

modulation can be achieved by altering the division ratio of the frequency di-vider5.

A second order PLL is characterized by its use of a first order low pass filter atthe input to the VCO. Second order indicates that the closed loop transfer functionis of second order.

Phase discontinuities during FSK and PSK modulation are unwanted sinceit causes spectral regrowth. This is however not a major concern when using aPLL for modulation since the phase of the signal at the VCO output is alwayscontinuous.

VCOPFD

Div.

Rp

Cp

C2

Ip

Ip

fref

Figure 2.7: Second order PLL with charge pump.

A closed loop transfer function of a second order PLL can be expressed as inequation (2.16).

HCL(s) =K(s + α)

s2 + Ks + α(2.16)

An advantage using second order PLLs is the similarity to other commonphysical systems. Basic knowledge from control theory can be used to expressthe transfer function in terms of natural frequency ωn and dampening factor ζ ascan be seen in equation (2.17).

HCL(s) =2ζωn(s + ωn

2ζ )

s2 + 2ζωn + ω2n

(2.17)

The following two equations hold for the second order PLL depicted in figure2.7 [17].

5There are of course more ways to produce frequency modulation with an PLL not discussed inthis thesis.

2.4 Minimum Tone Spacing for Orthogonal FSK 13

ωn =

√Ip

2πCP

KVCO

M(2.18)

ζ =Rp

2

√IpCp

2πKVCO

M(2.19)

The 3 dB cut-off frequency can be expressed in ζ andωn as follows in equation(2.20). The equation can be derived from (2.17), (2.18) and (2.19).

f3dB = ωn

√2ζ2 + 1 ± 2ζ

√ζ2 + 1 +

12ζ2

/2π (2.20)

The step response is proportional to the inverse exponential of ζωn and can beexpressed as in equation (2.21). The equation is derived by applying a unit stepto the closed loop transfer function in (2.17)

fresponse(t) = ∆ω

(1 − e−ζωnt

[cos(ωn

√1 − ζ2t) −

ζ√

1 − ζ2sin(ωn

√1 − ζ2t)

])(2.21)

The cut-off frequency and frequency response gives the main properties ofa PLL. The maximum symbol rate is limited by the cut off frequency in thecase where the modulation occurs within the frequency loop. A higher cut-offfrequency enables higher symbol rate but with the cost of a higher settling time.The settling time is hence dependent on the cut-off frequency (2.21) (2.20). Ashort settling time is generally preferred. Short settling time often results inhigher power consumption due to increased charge pump currents (2.19).

2.4 Minimum Tone Spacing for Orthogonal FSK

The maximum data rate in orthogonal FSK communication systems is limited bythe ”minimum tone spacing“, also known as ”minimum frequency separation“.Since the data rate is of great importance a discussion on minimum tone spacingis presented in this section. First a mathematical view of coherent and non-coherent FSK is given and then an alternative and a perhaps more intuitive wayof describing minimum frequency separation for non-coherent FSK is presented.

2.4.1 Orthogonal FSK and Coherency

As indicated in section 2.2.1, detection and demodulation of M FSK signals maybe accomplished phase-coherently or non phase-coherently.

Consider the sinusoids cos(2π f1t + φ) and cos(2π f2t). The phase φ is anarbitrary constant angle at the interval 0 to 2π. These sinusoids are orthogonal iftheir convolution, equation (2.22), equates to zero.

14 Related Theory

T∫0

cos(2π f1t + φ) cos(2π f2t)dt (2.22)

Integrating and applying the limits to equation (2.22) simplifies to equation(2.23) assuming f1 > f2. T is the symbol duration in seconds.

cosφ[

sin 2π( f1 + f2)T2π( f1 + f2)

+sin 2π( f1 − f2)T

2π( f1 − f2)T

]+ sinφ

[cos 2π( f1 + f2)T − 1

2π( f1 + f2)+

cos 2π( f1 − f2)T − 12π( f1 − f2)

]= 0

(2.23)

The following approximation can be done assuming f1 + f2 >> 1:

sin 2π( f1 + f2)T2π( f1 + f2)

≈cos 2π( f1 + f2)T

2π( f1 + f2)≈ 0 (2.24)

Combining (2.23) and (2.24) gives

cosφ sin 2π( f1 − f2)T + sinφ[cos 2π( f1 − f2)T − 1] ≈ 0 (2.25)

In the non-coherent case the phase φ can assume an arbitrary value from 0 to2π. This means that in order for the sum (of equation (2.25)) to equate to zero theterms sin 2π( f1 − f2)T and cos 2π( f1 − f2)T − 1 also have to equate to zero. Thisgives the following equivalence.

2π( f1 − f2)T = 2kπ⇔ f1 − f2 =kT

(2.26)

Hence, for non-coherent minimum frequency spacing k = 1 and f1 − f2 = kT .

However in the coherent case the phase φ is known which makes it possible forthe receiver to phase-align itself with the incoming signal. Since the phase isknown the tone spacing for orthogonality is found in equation (2.22) by settingφ = 0, which gives

sin2π( f1 − f2)T = 0⇔ f1 − f2 =n

2T(2.27)

Thus the minimum frequency separation for coherent FSK signaling occurswhen n = 1 as in

f1 − f2 =1

2T(2.28)

Concluding the results of the above equations, the coherent detected FSK can,for a given symbol rate, occupy less bandwidth than a non-coherent detected FSKand still be orthogonal. Remember that orthogonal FSK benefits from an optimalbit error rate for any given signal to noise ratio.

2.5 Spectral Regrowth Issues 15

2.4.2 Alternative Approach to non-Coherent Orthogonal FSK

When modulating a FSK signal by switching between the available frequenciesthe individual tones will assume the shape of a sinc according to Fourier transformtheory. This is visualized in figure 2.8 where the frequency spectra of binary, twotone, FSK signaling is depicted.

For a detected non-coherent tone to manifest a maximum output the peak ofthe tones in the corresponding frequency spectra has to align with a zero crossingof the adjacent tones. The distance from the peak of the tones main lobe and itsfirst zero crossing gives the minimum frequency separation. That is the smallestpossible separation between adjacent tones for which orthogonality is fulfilled.

Maximum bandwidth efficiency for non-coherent FSK is achieved by aligningthe centers of the main lobes with the first zero crossing of the neighboring toneor tones. The minimum frequency separation for non-coherent FSK is thereby1/T Hz where T is the symbol duration. The tones in figure 2.8 are separatedwith the “minimum frequency separation” distance and the highest bandwidthefficiency is therefore accomplished6. The tones are orthogonal, which means thatthe detected signal manifests a maximum output. Orthogonality between tonesgives an optimal bit error rate for any given signal to noise ratio.

1/T Hzf2

f1

T sinc(f-f2)T T sinc(f-f

1)T

f

Figure 2.8: Minimum frequency separation for non-coherent FSK signaling.

The required bandwidth of binary FSK can be derived from figure 2.8 as theminimum frequency spacing distance between the two tones plus one half of thetone spacing on both sides of the spectra. Hence the required bandwidth forbinary FSK is 2/T Hz. The required bandwidth for M-ary FSK can be derivedanalogous to M/T Hz.

2.5 Spectral Regrowth Issues

Spectral regrowth is caused by abrupt phase changes of the transmitted signal.Remembering Fourier Series Theory, a signal with abrupt phase transitions in-

6That is for non-coherent FSK signaling.

16 Related Theory

cludes a large number of high frequency components. These high frequencycomponents cause a higher percentage of the transmitted power to occur outsidethe designated frequency band leading to poor spectral efficiency. Base bandfiltering is often used to mitigate this effect by smoothering the transitions in thetime domain as illustrated in figure 2.9.

LPF Modulator PAxBB(t)

Figure 2.9: Low-pass time domain filtering of the baseband signal.

Filtering phase transitions reduces spectral regrowth and hence improves spec-tral efficiency. However, filtering also causes greater envelope variations, e.i.amplitude variations, of the transmitted carrier (see figure 2.10). The amplitudevariations increase as the filter narrows. The operation of the power amplifierbecomes a key factor in order to maintain the desired spectrum to the limited band-width. The PA must be able to follow the amplitude variations without distortingthe signal by adding frequency components to the spectra. This implies that thePA needs to be linear to some degree. Larger amplitude variations requires higherlinearity. The effect when a non-linear component distorts the shape of a filteredsignal and deteriorates the limited bandwidth is called “spectral regrowth”.

180° 180° 90°

UnfilteredQPSK

FilteredQPSK

t

Figure 2.10: Unfiltered and filtered QPSK waveforms.

Unfortunately, linear PAs are typically less efficient than their non-linear coun-terpart. The power efficiency of efficient linear PAs ranges about 40% and about60% for non-linear PAs [16]. These figures are usually significantly lower for ultralow power PAs.

2.6 Constant Envelope 17

2.6 Constant Envelope

As stated in the previous section, the term envelop is referring to the amplitudeof a signal. In this section, envelope refers to the amplitude of the carrier wavesignal specifically. Constant envelope simply states that the amplitude of thecarrier wave signal is constant.

2.6.1 Frequency Modulation

Analog FM and discrete FSK are both constant envelope. While analog FM isby nature phase continuous, this is not the case with FSK when considering aswitch based architecture (e.g. the architecture in figure 2.13 b). FSK modulationcauses phase discontinuities if no consideration is taken in respect to carrier wavefrequency and data rate.

FM(Analog)

Figure 2.11: Analog frequency modulation waveform.

Phase discontinuities can be avoided by choosing the difference of the carrierfrequencies to be multiples of 1/2T 7 where T is the symbol duration. Hence,equation (2.29) [9] must hold ∣∣∣∣ f1 − f2

∣∣∣∣ =N2T

(2.29)

, where N is an integer. Choosing the carrier frequency difference for binaryFSK to the “minimum frequency separation” 1/2T discussed earlier results in amodulation scheme called Minimum Shift Keying (MSK). The phase trajectoryof MSK is linear and hence also continuous. In order for the phase trajectory toalso be “smooth”, its derivative also needs to be continuous which is not the casefor MSK. Baseband filtering is often introduced to “smooth” the MSK signal. Acommon way of performing base band filtering on MSK is to introduce Gaussianfiltering. Gaussian MSK or GMSK are very popular and commonly used in theindustry and are found in e.g. GSM, Bluetooth and IEEE 802.11 devices.

Another way of dealing with the issues with the continuous phase duringFSK modulation is to use a different type of architecture than the switching typediscussed so far. By using a VCO based type of architecture, see figure 2.13 (a), acontinuous phase can be guaranteed independently of carrier frequency and thedata rate. The carrier frequency can be modulated by for example altering theimpedance of the ocillator resonant tank.

7E.i. for coherent FSK.

18 Related Theory

0 1 0

DiscontinuousFSK

ContinuousFSK

Message

Figure 2.12: Discontinuous and continuous FSK waveforms

CMod

Data

(a) VCO based FSK

f1

f2

Data(b) Switching based FSK

Figure 2.13: Continuous and discontinuous phase architectures.

2.6 Constant Envelope 19

2.6.2 Phase Modulation

PSK modulation is not regarded as being constant envelope. However, since theenvelope behavior is proportional to the amount of phase discontinuity, differentPSK modulation schemes exhibit different envelope characteristics.

The envelope behavior of a modulation scheme is captured by its constellationdiagram. The lines between symbol states represents possible symbol transitiontrajectories. The envelope behavior is determined by the distance from the trajec-tory to the origin. QPSK has the largest phase shifts of the constellation diagramsdepicted in figure 2.14 with a maximum phase shift of 180 degrees. A 180 degreephase transition is represented by a symbol trajectory crossing the origin. There-for, QPSK also displays the largest amplitude variations and hence the poorestenvelope characteristics. π/4-DQPSK has a maximum phase shift of 135 degreesand its symbol trajectories never crosses the origin which means that it has lessamplitude variations than QPSK.

QPSK π/4-DQPSK OQPSK MSK

Figure 2.14: Constellation diagrams of QPSK, π/4-DQPSK, OQPSK and MSK

In OQPSK in-phase and quadrature transitions are offset by half of a symbolperiod which reduces the maximum phase shift to 90 degrees compared to 180degree shift for QPSK. For constant envelope behavior the distance between theorigin and the trajectory must be constant, like in the case of MSK. MSK wasdescribed in section 2.6.1 as a FSK type of modulation scheme. One other way toview MSK modulation is to view it as a PSK modulation scheme with a constantphase shift.

Chapter 3

A Brief Overview of CurrentArchitectures

This chapter presents an overview of ten low-power transmitters, a descriptionof the three most power-efficient architectures and a short discussion on using65 nm technology in MICS applications.

3.1 A Brief Overview

An overview of existing ultra low-power transmitters and their characteristicfeatures is presented in table 3.2 where the transmitters are ordered by theirglobal power consumption. The transmitters are in table 3.3 ordered by the energydissipated per bit. Some of the architectures use conventional power amplifierswith specified power efficiencies. These architectures and their efficiencies arelisted in table 3.4.

The four most power efficient transmitters in table 3.3 represents three differenttypes of architectures. A short summary of these architectures is given in thefollowing subsections.

3.1.1 Distributed Frequency Correction

For implantable devices the MICS standard, paragraph §95.6281, specifies thefrequency stability to be maintained for ±100 ppm over a range of 25°C to 45°C.The ±100 ppm requirement is relatively relaxed compared to other standardssince the temperature of an implanted transmitter is constantly moderated by thehuman body. The architectures in [8] and [10] have taken advantage of the relaxedfrequency stability requirements and completely removed the on-chip frequencyloop back used for frequency correction. The frequency loop back is insteaddistributed to the base station, now responsible for tracking the frequency errors

1See section 4.1.1

21

22 A Brief Overview of Current Architectures

and periodically sending frequency correction bits to the implantable device. Botharchitectures utilize a digital controlled oscillator (DCO) for frequency synthesisand modulation. No crystal oscillator is needed. The frequency is controlled bycapacitor banks and both architectures employs FSK modulation.

CArray

CMod

DCO

PA

Data

Message Message + Correction bits

Figure 3.1: DCO based transmitter with distributed frequency correction.

The benefits of using a distributed frequency feedback could be questionedsince many applications would need to utilize a reference frequency for otherparts of the application than the transmitter. In that case the frequency loop backoverhead would have a less significant footprint on the global power consump-tion.

3.1.2 Frequency Multiplying Power Amplifier

In order to improve the global power consumption [18] presents an architecturethat operates entirely on the crystal frequency at 45.454 MHz. Basic buildingblocks are the crystal oscillator circuit, digital delay loop and the power amplifier.FSK modulation is performed at the crystal frequency by pulling the frequencywith a capacitor. The crystal frequency is then forwarded to a 9-state DLL con-trolled by two feedback loops for frequency and duty-cycle control, respectively.The power amplifier operates as an edge combiner, which combines the 9 edgesfrom the DLL producing a modulated output radio frequency at 9 × fXTAL. Thistopology offers crystal stability without the need of a PLL or DLL operating atradio frequencies. One major drawback is however the lack of channel selectivity.

3.1.3 Direct VCO Modulation Using Low Supply Voltage

Paper [4] presents a transceiver architecture for wireless sensor networks and notspecifically for use in MICS applications. The transmitter is designed to operatein the 2.4 GHz ISM band. The transmitter is of a direct VCO modulation typeand is designed for 400 mV supply voltage to enable it to be driven from a singlesolar cell. Frequency control is achieved by setting a 17 bit capacitor array in theVCO. Contributors to low power consumption are: the ability to operate at a lowpower supply (400 mV), stacked topology in order to reuse bias current and directVCO modulation. Further contribution is made by lowering the frequency at the

3.2 65 nm Designs 23

CP + LF1

PDF

CP + LF2

PDF

9xfXTAL

fXTAL

45.545 MHzFSK Data

A1

A2

A9

Delay Chain

Edge Combiner

Figure 3.2: Transmitter based on a frequency multiplying edge combiner.

counter input by preceding the counter with a dynamic ring divider. Customdynamic logic is also used in early high frequency parts of the counter.

PA/8Counter

FLLN

Tx bits

32 kHz Oscillator

50 OhmAntenna

Quadrature VCO

17 bits

To the receiver

Figure 3.3: Direct VCO modulated transmitter.

3.2 65 nm Designs

The papers covered in table 3.2 and 3.3 use technologies from 180 to 90 nm. Nopapers were found on transmitters using 65 nm or newer technologies duringthe thesis. However there is at least one paper [22] on a MICS receiver utilizingthe 65 nm technology. The receiver uses linear mixers and a VCO operatingat radio frequency which typically would lead to high power consumption (thearchitecture is depicted in figure 3.4). However ultra-low power consumptionis achieved by a wide use of sub-threshold devices. 90% of the transistors in allanalog building blocks are operating in deep week inversion region.

Sub-threshold design has historically been associated with low frequency de-vices. Sub-threshold device operation exhibit higher transconductance but witha worsened frequency ability limiting the operation to lower frequencies. Fortu-nately, the transit frequency is increased by 75 to 100% in all operation regionsfor each new generation of scaling [15]. The degree of sub-threshold operation orinversion can be approximated by the inversion constant in equation (3.1).


IC =ID

I0WL

(3.1)

This 65 nm device covered in [22] is driven to deep week inversion whichmeans that the inversion constant is less than 0.1. This in turn means that thehighest power efficiency (gm/ID) is achieved for this receiver during operation at400 MHz.

An overview of the power consumption is given in table 3.1.

PLL

900

LNA IF amp

IF amp

Real BPF

Complex BPF

Channel Selection

On chip MEMSresonator

RF inFSK Demod

Figure 3.4: 65 nm weak inversion MICS receiver.

Building Blocks Power Consumption (µW)LNA 370

Quadrature Mixers 240Complex IF BPF 500

Real IF BPF 95IF Gain Stage 1.6

BFSK Demodulator 8VCO 210PLL 160

Total (Quadrature channel + Complex IF BPF) 1490Total (Inphase channel only + Real IF BPF) 925

Table 3.1: Summary of power consumption.

3.3 Concluding Summary

All transmitters covered in section 3.1 are utilizing FSK modulation and are usingcapacitor banks for modulation and frequency selection. It is hard, if at all possi-ble2, to perform PSK modulation by pulling capacitors in order to alter the phase

2Opinion of the authors of this document.

3.3 Concluding Summary 25

of the signal using proposed types of architectures. Hence, modifications of theabove mentioned architectures are required for use in PSK applications.

Even though smaller modifications easily could be made to generate multiplephases for PSK modulation, these architectures does not facilitate any meansof filtering or smothering of the phase transitions, decremental to the overallperformance.

The architectures presented in table 3.2 offer a wide range of characteristics.The data rate ranges from 50 kbit/s to 1 Mbit/s, output signal power rangesbetween −16 and 0 dBm while the power efficiency lies between 13 and 44%.

Categorization by Total Transmitter Power Consumption

Paper Power (Tx) Transmitter Receiver

50

0 µ

W

A 350µW CMOS MSK Transmitter and 400µW OOK Super-Regenerative Receiver for Medical Implant Communications [8]

350 µW @ -16 dBm, 120 kbit/s

DCO based with distributed feedback. No external crystal.

DCO based. Super regenerative OOK demodulation.

A 490µW Fully MICS Compatible FSK Transceiver for Implantable Devices [10]

400 µW @ -16 dBm, 250 kbit/s

DCO based with distributed feedback. No external crystal.

DCO based with relaxation mixer, Q-enhanced low-IF FSK receiver.

A 500µW Neural Tag with 2µVrms AFE and Frequency-Multiplying MICS/ISM FSK Transmitter [18]

500 µW @ -16 dBm, 100 kbit/s

9x frequency multiplying power amplifier. (Edge combiner)

-

500

µW

to

1

mW

An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm CMOS with 400mV Supply and an Integrated Passive RX Front-End [4]

700 µW @ -8.5 dBm, 300 kbit/s

Direct FSK quadrature VCO modulation, PLL based.

Single phase or quadrature down conversion; passive mixer; PLL based; FSK demodulation.

1 t

o 5

mW

A 1V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications [3]

2.4 mW @ -10 dBm, 50 kbit/s

Sliding-IF; PLL based; FSK and GFSK modulation.

Sliding-IF; PLL based; FSK and GFSK demodulation.

A 2mW 400MHz RF Transceiver SoC in 0.18µm CMOS Technology [13]

1.8 mW @ -12 dBm, 128 kbit/s

Zero-IF; PLL and mixer based; FSK modulation.

Zero-IF; PLL and mixer based; FSK modulation.

5 t

o 1

0

mW

A 400-MHz CMOS Radio Front-End for Ultra Low-Power Medical Implantable Applications [5]

5.4 mW @ 0 dBm,

400 kbit/s

Programmable integer-N PLL with VCO, 6 IQ mixers.

Super regenerative OOK, PLL based with envelope detector.

10

to

15

m

W A Low-Power Asymmetrical MICS Wireless

Interface and Transceiver Design for Medical Imaging [12]

12.7 mW @ -15d Bm, 524 kbit/s

Pseudo-open-loop PLL, high speed phase selector, G/FSK modulation.

Super regenerative OOK, PLL based with envelope detector.

≥ 1

5 m

W A 400-MHz/900-MHz/2.4-GHz Multi-band FSK

Transmitter in 0.18µm CMOS [11]

16 mW @ -12 dBm, 1 Mbit/s

PLL based; 3-5 GHz VCO; Wide band, inductorless mixer; FSK modulation.

-

An Ultra-Low Power, High Performance Medical Implant Communication System (MICS) Transceiver for Implantable Devices [14]

16 mW @ -17 to -4 dBm,

400 kbit/s

PLL and mixer based, direct conversion, 2/4FSK modulation.

Direct conversion OOK PLL and mixer based receiver.

Table 3.2: Overview of ten ultra-low power radio transmitters.


Power Consumption Considering Data RateEnergy per Bit Paper

1.60 nJ/bit A 490 µW Fully MICS Compatible FSK Transceiver for Implantable Devices [10]∼2.33 - 3 nJ/bit An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm

CMOS with 400mV Supply and an Integrated Passive RX Front-End [4]2.9 nJ/bit A 350uW CMOS MSK Transmitter and 400uW OOK Super-Regenerative Receiver

for Medical Implant Communications [8]4.0 nJ/bit A 500µW Neural Tag with 2µVrms AFE and Frequency-Multiplying MICS/ISM FSK

Transmitter [18]13.5 nJ/bit A 400-MHz CMOS Radio Front-End for Ultra Low-Power Medical Implantable

Applications [5]14 nJ/bit A 2mW 400MHz RF Transceiver SoC in 0.18um CMOS Technology [13]16 nJ/bit A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-µm CMOS [11]24 nJ/bit A Low-Power Asymmetrical MICS Wireless Interface and Transceiver Design for

Medical Imaging [12]40 nJ/bit An Ultra-Low Power, High Performance Medical Implant Communication System

(MICS) Transceiver for Implantable Devices [14]48 nJ/bit A 1V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applica-

tions [3]

Table 3.3: Ten ultra-low power radio transmitters ordered by energy per bit.

PA Power EfficiencyEfficiency Paper

13% A 490µW Fully MICS Compatible FSK Transceiver for Implantable Devices [10]16% A 500µW Neural Tag with 2µVrms AFE and Frequency-Multiplying MICS/ISM FSK

Transmitter [18]31% A 1V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applica-

tions [3]32% A 400-MHz CMOS Radio Front-End for Ultra Low-Power Medical Implantable

Applications [5]44% An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm

CMOS with 400mV Supply and an Integrated Passive RX Front-End [4]

Table 3.4: PA efficiency for ultra-low power transmitters.

Chapter 4

The MICS Standard and PSKBandwidth Efficiency Issues

This chapter presents a summary of the Medical Implantable CommunicationsService (MICS) radio standard introduced by Federal Communications Commis-sion (FCC). It also points out bandwidth efficiency issues for PSK modulationcomplying to the MICS standard, which will be a major challenge throughout thethesis. The complete MICS standard can be found in [2].

4.1 MICS Standard

In 1999 the FCC introduced a new standard devoted to medical implantableservices called MICS. The specified frequency band for MICS is 402-405 MHz.There were a number of reasons for choosing this specific band. One reason isthat the propagation characteristics for frequencies in this band are favorable fortransmission through the human body [19].

A summary of the MICS standard is given in the following subsections. Thesummary is divided into the corresponding paragraphs related to the MICS stan-dard and the main features of each paragraph are listed by bullet points. Thereader is referred to “FCC Rules and Regulations Part 95” [2] for more detailedinformation. The related FCC paragraphs is stated in the corresponding subtitles.

4.1.1 MICS Transmitter from Paragraph §95.628

• Any frequencies from 402 to 405 MHz can be used (no channeling schemeexists).

• The emission bandwidth is 300 kHz and is measured at the points on eitherside of the carrier frequency situated 20 dB below the top value. Measure-ment resolution is 1% of the emission bandwidth (300 kHz).

27

28 The MICS Standard and PSK Bandwidth Efficiency Issues

• A communications session involving a MICS device shall not use more than300 kHz of bandwidth.

• Each transmitter shall maintain ±100 ppm frequency stability over a rangeof:

1. 25°C to 45°C for implanted transmitters.

2. 0°C to 55°C for programmer/controller transmitters.

4.1.2 Emission Types from Paragraph §95.631

• A MICS transmitter may transmit any emission type appropriate for com-munication. However, voice communication is not allowed.

4.1.3 Emission bandwidth from Paragraph §95.633

• Bandwidth limitations according to §95.628.

• Maximum EIRP is 25 µW (−16 dBm). See following paragraphs for mea-suring details.

4.1.4 Unwanted Radiation from Paragraph §95.635

• Emissions 250 kHz outside the MICS band shall be attenuated according tothe following table.

Frequency MHz Field Strength ( µV/m) Measurement Distance (m)33-88 100 388-286 150 3216-960 200 3960 and above 500 3Note - At band edges, the tighter limit apply

Table 4.1: Attenuation of signal 250 kHz outside the MICS band.

• The emission should be measured to at least the tenth harmonic of thehighest fundamental frequency to be transmitted.

• Emissions within the MICS band 150 kHz from the center frequency shallbe attenuated 20 dB bellow the transmitted output power.

• Any other frequencies shall be attenuated 20 dB bellow the transmittedpower.

4.1 MICS Standard 29

4.1.5 Maximum Transmitted Power from Paragraph §95.639

• The maximum EIRP for a MICS transmitter is 25 µW. Compliance may bedetermined by measuring the EIRP at 3 m. The equivalent radiated field at3 meters for 25 µW is 18.2 µV/m at an “open test area site”, or 9.6 µV/mwhich is equivalent to “free space”.

• Implantable transmitters shall be tested in a body/tissue-like medium.

• The power radiated in any 300 kHz bandwidth shall not exceed 25 µW EIRP.

• The antenna is considered as a part of the transmitter. Antenna and trans-mitter are tested as a unit.

4.1.6 Additional Power Constraint from Paragraph §95.649

• No CB, R/C, LPRS, FRS, MICS, MURS or WMTS unit shall incorporateprovisions for increasing its transmitter power to any level in excess of thelimits specified in §95.639.

4.1.7 Crystal Control Requirements from Paragraph §95.651

• No crystal control is required for MICS.

4.1.8 Resulting Spectral Mask

The following spectral channel mask can be derived from the preceding specifi-cations for the in band frequencies (see figure 4.1).

Figure 4.1: In band frequency mask for MICS standard

30 The MICS Standard and PSK Bandwidth Efficiency Issues

4.2 PSK Bandwidth Efficiency Issues

The rational for considering the use of PSK instead of FSK modulation is that PSKmodulation schemes, in common theory, require lower signal power1 than FSKbased modulation schemes. PSK is also generally regarded as more bandwidthefficient facilitating the possibility of higher data rates. However, the bandwidthefficiency is affected by the spectral mask and the performed filtering. A higheramount of filtering is also affecting the signal to noise ratio leading to higherrequired signal powers.

Spec

trum

(dB

)

-50

-40

-30

-20

-10

0

fC+f

Sf

C+2f

Sf

C+3f

Sf

C+4f

Sf

C+5f

Sf

C+6f

Sf

C

MSKQPSK

Figure 4.2: QPSK and MSK Spectrum

As described in chapter 2, MSK can be viewed as binary FSK modulation withminimal frequency separation. Comparing the MSK and QPSK frequency spectrain figure 4.2 reveals that MSK has a wider main lobe than QPSK and that the side-lobes in the QPSK spectra have a slower attenuation than the MSK spectra. Theattenuation of the side-lobes in the MSK spectra is proportional to f 4 while theattenuation in QPSK spectra is proportional to f 2 [20]. The main lobe is often thedeciding factor when determining the bandwidth efficiency. However, it is not thecase when using the MICS mask due to its 20 dB cut-offs. This drastically limitsthe unfiltered QPSK data rate since the first and second side-lobe fall within the300 kHz channel bandwidth of the MICS mask (see figure 4.2 where the amplitudeof the first and second side-lobe are attenuated less than 20 dB). During simulationwith a resolution bandwidth of 3 kHz, also the third side lobe has to be includedin the 300 kHz channel width. Limiting the theoretical data rate of the unfilteredQPSK signal to approximately 80 kbit/s. Other FSK modulation schemes withlarger frequency separation distances than the minimum distance used by MSKhave even higher attenuation of the unwanted side-lobes. Hence under the MICSmask, the data rate for FSK modulation is limited by the frequency separation

1See section 2.2.1 for reference.

4.2 PSK Bandwidth Efficiency Issues 31

while the data rate of QPSK signaling is limited by the influence of its side-lobes.The data rate of unfiltered MSK modulation is limited to about 230 kbit/s. Almostthree times higher than the data rate using QPSK modulation.

Figure 4.3: Unfiltered QPSK spectra using RBW of 3 kHz.

To improve the PSK bandwidth efficiency and increase the data rate one couldapply different filtering or shaping techniques in order to suppress the side-lobes.The competitiveness of using PSK modulation in MICS applications is determinedby the ability to shape the frequency spectrum to better fit the MICS mask whileminimizing the deterioration of the signal to noise ratio. Since additional hard-ware is most likely needed2 it is also crucial that the added power consumptiondue to the additional hardware does not exceed the power saved by reducing thesignal power.

2Compared to the FSK architectures discussed 3.

Chapter 5

Testbenches

This chapter describes the two testbenches used during simulations, the availablemeasurements and the test methodology.

5.1 Detectors

What differs the two testbenches used during this thesis are the detectors. Onetestbench uses a PSK detector and is used for simulating the PSK architectures.The other testbench uses a FSK detector. The FSK testbench is used to validatethe relative behavior of the PSK architectures by simulating FSK architectures.

5.1.1 PSK Detector

The detector that has been used is a coherent phase detector. The incoming radiofrequency is down-converted with a phase aligned local oscillator. The productfrom this multiplication consists of one high frequency component and one DCcomponent proportional to the phase of the input signal. The high frequencycomponent is discarded by low pass filtering and only the DC component is used.The detection and demodulation are analogous for the in-phase and quadraturepaths. They differ however in respect to the local oscillator which is shifted 90°between the paths.

After the multiplication and filtering, the DC component is integrated overat most a symbol period and then sampled. Different modulation techniquesrequires different timing. The timing for the two paths are controlled individuallyby an integrator reset and a sample-and-hold signal for each path respectively.The PSK demodulator is depicted in figure 5.1.

5.1.2 FSK Detector

The FSK detector used is a binary non-coherent quadrature detector. Hence, itdoes not track the phase of the transmitted carrier frequency. A non-coherent

33

34 Testbenches

LO

+90°

I {0,1}

Q {0,1}

Reset Sample&hold

Figure 5.1: PSK demodulator block diagram.

detector requires an Eb to n0 ratio which is 1.5 dB higher than its coherent equiv-alent1.

The binary modulated FSK signal is composed of two alternating carrier fre-quencies with a frequency spacing of ∆ f . The received signal is down-convertedin the mixer stages which in turn are followed by integrator stages acting aslow-pass filters by removing higher frequency components. The resulting DCcomponents are then sampled and squared. If the received carrier frequency isequal to fc the decision branch will assume a positive value while it will assumea negative value in the case where the carrier frequency is equal to fc + ∆ f . Thevalues in the decision branch are converted to a binary sequence by a comparator.The FSK detector is depicted in figure 5.2.

5.2 Measurements

To determine the performance of the architecture under test, the testbench mea-sures the spectrum of the modulated signal. Additive white Gaussian noise isadded before demodulation to simulate a noisy channel. The demodulated signalis then compared with the input data to test for bit errors under a predeterminedSNR. The following measurements are available in the testbench.

• MICS mask compliance

• BER measurement

• Eye diagram of the integrated signal to tweak the timing

• SNR measurement

• Eb/n0 measurement

• Channel power and Adjacent channel power

1See section 2.2.1.

5.2 Measurements 35

∫0

t

dt

cos 2 f c t

2

∫0

t

dt

sin 2 f c t

2

∫0

t

dt

cos 2 f c f t

2

∫0

t

dt

sin 2 f c f t

2

+

-

Samplet=T

Integrate

Decision

Figure 5.2: Block diagram of non-coherent FSK demodulator

MICS Mask Compliance

In-band frequencies are tested for MICS compliance according to section 4.1.4.

BER Measurement

Supplied for performing BER measurement, but also used to verify proper behav-ior of different architectures. The simulation environment used during the thesiswork limits the number of bits in the BER measurement to approximately 2000.Increasing the number of bits further causes sporadic crashes during simulation.

Eye Diagram

Eye diagram measurements are performed after the integration blocks. Thesemeasurements are useful when tweaking the timing control signals in order tominimize the bit error rate.

The timing of the reset signal to the integration block and sample-and-hold-signal needs to be adjusted to match the shape of the phase transition. Figure 5.3depicts a down-converted signal of one of the channels. The signal is integratedby the integrator and then sampled by the sample-and-hold block. Looking atfigure 5.3 the control signals are set to integrate each symbol between its zerocrossings. If the signal is unshaped, the integration can be performed during the

36 Testbenches

entire symbol length. The optimal integration duration are in some cases less thana symbol length, hence the possibility to set the control signals independently.

Shaped

Un-shaped

0

Vmin

Vmax

Figure 5.3: Signal after mixer stage.

Figure 5.4 depicts the eye diagram used when tweaking the control signals.To minimize the bit error rate the minimum amplitude, in the eye diagram, ismaximized at the time for sample-and-hold.

-2 0 2 4 6 8 10 12 14

0

-20

-40

-60

-80

20

40

60

80

time, usec

eye_

Q_i

nteg

rate

Reset

Sample & hold

Figure 5.4: Eye diagram used for timing of reset and sample-and-hold controlsignals.

SNR Measurement

Basic SNR measurement in linear and decibel scale. Used when calculating theEb/n0 measurement. The signal power measurement is performed with the built

5.3 Test Methodology 37

in function “Spec_power()” that uses data from an ADS spectrum analyzer com-ponent. This approach of calculating signal power is verified by also calculatingthe signal power in time domain using equation 5.1.

P =1

Simulation Time1Z

∫ ∣∣∣∣x(t)∣∣∣∣2dt (5.1)

Eb/n0 Measurement

This measurement calculates the energy per bit over the noise floor and is moreuseful than the SNR measurement since it also consider the data rate.

Channel Power/Adjacent Channel Power Measurement

Power measurements are performed for both in-channel and adjacent channelpower.

5.3 Test Methodology

There are basically two ways to decrease the power consumption for the givenhigh level architectures:

1. Decrease the transmission time by increasing the data rate.

2. Minimize the required signal power.

Thus, the idea behind the test methodology is to determine the minimumsignal power (i.e. Eb/n0) for different data rates in order to acquire the powercharacteristics for the designed architectures.

The minimum signal to noise ratio is determined for a specified data rate, seefigure 5.5. The test start with a short data sequence to determine starting pointsfor the amount of shaping that must be performed to comply to the MICS spectralmask. When the transmitter is complying to the spectral mask the noise in thechannel is increased to find the highest noise level while still being able to senddetectable data. In an ideal simulation environment increasing the power of theadded noise has the same effect as decreasing the power of the transmitted signal.

When the maximum noise level for this, short, data sequence is determineda longer sequence is simulated until 2000 symbols are sent and received withoutany bit errors. A test with 2000 error free symbols indicate a BER no higher than10−3 with a confidence level of 86% and a BER no higher than 1.5 ∗ 10−3 with aconfidence level of 95%, [1].

38 Testbenches

ZeroBER

Start

Simulate

MICSMask

2k Sym

Increase Noise

Simulate

ZeroBER

Latest Approved Noise Level

Simulate

More Symbols

Zero BER Less Noise Stop

More Shaping

Does Not MeetMinimum Data Rate

No

Yes No

Yes

No

Yes

No

Yes

Yes

No

Figure 5.5: Test methodology for determining the SNR given a certain data rate.

Chapter 6

Designed Architectures

This chapter presents the architectures designed and simulated during the thesis.A short description of the idea leading up to each architecture is also given alongwith some brief details of the implementation.

6.1 PSK Modulators

The different PSK architectures designed and simulated during the thesis arepresented in the following sections.

6.1.1 Simple QPSK

One seemingly obvious way to modulate a radio signal with QPSK is to generatefour signals, 90 degree apart, and simply switch between them in order to drivethe areal as in figure 6.1. However this type of architecture typically suffer fromspectral regrowth since the phase trajectory is discontinuous. Another drawbackis that the non-constant envelope behavior causes amplitude variations requiringa more linear and power consuming power amplifier.

This architecture is foremost included for reference purposes. The followingarchitectures are addressing the issues with discontinuous phase trajectory andthe lack of constant envelope behavior.

Implementation

The architecture was implemented in ADS using a standard QAM building blockset to four constellation points. The QAM component does not perform anytiming or filtering. Hence the output phase is discontinuous as described above.

6.1.2 PLL Based QPSK Modulation

PLLs are used in most radio transmitters to synthesize the correct frequency for thelocal oscillator. Direct QPSK modulation can be achieved by using a quadrature

39

40 Designed Architectures

QuadratureVCO

Phase Select

Figure 6.1: Switch based QPSK with discontinuous output.

VCO which produce four signals separated by 90 degree (see figure 6.2). Themodulation is performed by choosing which of these signals or phases to be usedin the feed back loop using a multiplexer. The feedback signal will after an initialsettling time be locked to the reference signal. Hence, the phase of the VCO willchange as switching is performed between the four phases. One of the signals arefed through to the power amplifier, or as in the testbench to a spectrum analyzer.The feedback loop in the PLL acts as a low-pass filter. By adjusting the filtercharacteristics of the feedback loop, the phase transitions could be smoothened,hence reducing the spectral regrowth. Constant envelope modulation is alsoachieved since the VCO always outputs a continuous phase.

PFD

Div N

fref

Spectrum Analyzer

Phase Select(I and Q)

Figure 6.2: Basic PLL architecture modified with quadrature feed back.

Implementation

The PLL was created by using existing behavioral models for phase-frequency-detector (PFD) and VCO. This drastically reduces simulation time but also reducesthe flexibility of the PLL model. The single phase output from the VCO were fedto a “custom made” block that produced four quadrature phase shifted signalsfrom the input signal. The binary I and Q signals were then used to select whichof the four phase shifted signals to be fed back to the phase detector.

6.1 PSK Modulators 41

6.1.3 PLL Based QPSK Modulation with Dither

To smoothen the phase transitions even further, compared to 6.1.2, an architecturewith dither is proposed in this thesis. This architecture is based on the previousdescribed PLL architecture but a multiplexer and shaping logic were added seefigure 6.3. The added hardware allows this architecture to dither1 between the newand old IQ-value according to a time varying pattern or shape. Since the ditheringfrequency is greater than the cut-off frequency of the closed loop filter, the outputto the spectrum analyzer will not change as fast as the dithering frequency, butinstead assume an average phase. This average phase will be changed from beingclose to the previous IQ-value to being close to the new IQ-value over time bychanging the portion of time that the new and old values are fed back into the loop.This could potentially reduce the spectral footprint compared to the previouslypresented simple architecture.

PFD

Div N

fref

Spectrum Analyzer

IQ new

IQ old

ShapingLogic

Figure 6.3: Basic PLL architecture with quadrature feed back.

The switching between symbol states are performed by 90 degree phase shifttransitions. A 180 degree phase shift is therefor performed in two 90 degree stepspassing an intermediate symbol state in each transition. The reason for this isto secure the performance of the PLL feedback. Dithering between two phases180 degree apart causes the PLL to loose its lock, leading to unpredictable PLLbehavior.

In radio designs a PLL is often used to synthesize a frequency from a reference.In this architecture the dithering must not interfere with the synthesis. Thesynthesis consist of a frequency divider, see figure 6.3. If the frequency divideris a digital counter this will most likely get a false count from the dithering fromthe shaping logic. There are other frequency dividers such as injection-lockedfrequency dividers that could be less sensitive to the dithering. For this thesis onlyhigh level simulation is performed and it is assumed that this QPSK modulatorcan be designed without interfering with the frequency synthesis.

1That is to rapidly alternate from one to the other.


Implementation

The PLL was implemented as in section 6.1.2 using behavioral models. Bit pre-cision Ptolemy was used for implementing the shaping logic. The main buildingblocks used are a finite state machine (FSM), a counter and a ROM memory (seefigure 6.4). The FSM starts a new phase transition by enabling the counter whena new IQ-value appears at its input. The FSM also controls the IQ-values at theinput to the multiplexer. The IQ-values are then multiplexed to the output usingthe overflow from the delta sigma accumulator as select-signal. The overflow-ratio of the accumulator is dynamically set by the ROM. Hence, the shape of thephase transition can be controlled by programming of the ROM.

The time duration for a phase transition can be altered. The maximum timeduration is typically not longer than a symbol duration. Increasing the timeduration results in a smoother phase transition and a narrower spectral foot-printbut with the expense of a higher bit error rate.

FSM1st Order

Sigma Delta

+ROMCounter

IQ

clk

Div. X

fraction

IQ old

IQ new

clk

div_clk

IQ out

overflow

Mux

Figure 6.4: Functional block diagram over the shaping logic.

The following parameters are used by the shaping logic:

• Ramp-up Ratio

• Clock Ratio

• ROM Precision

• Counter Width

The parameter “Ramp-up Ratio” determines the ratio between the duration ofthe phase transition and the symbol duration. The duration of the phase transitionshall not exceed the symbol duration, hence relation (6.1) must hold.

Ramp − up Ratio ≤ 100% (6.1)

6.1 PSK Modulators 43

The “Clock Ratio” parameter determines the ratio between clk and clk_divwhere 2Clock Ratio = clk/clk_div. The parameter “ROM Precision” determines thenumber of fractional bits at the input to the 1st order delta sigma accumulator.The Clock Ratio is set to be equal or greater than the ROM precision in order tonot loose accuracy. Hence, relation (6.2) must hold.

Clock Ratio ≥ ROM Precision (6.2)

The frequency for which the multiplexer changes value at the output is in thisthesis referred to as the “dithering frequency”. The lowest dithering frequencymust be greater than the PLL closed loop cut-off frequency. Hence relation (6.3)must hold.

PLL cut − o f f f requency < Lowest Dithering Frequency (6.3)

Too low PLL cut-off frequency deteriorates the signal beyond the point forwhich it can be successfully detected and demodulated. This pivotal point appearswhen the PLL cut-off frequency is about 30% lower than the symbol rate. Thisis true for the 1st order PLL used in this architecture. Hence, relation (6.4) musthold.

PLL cut − o f f f requency >Symbol Rate

1.3(6.4)

The chosen values for the parameters used in this architecture are listed intable 6.1. Among the parameters, Counter Width has the greatest impact of theoverall spectrum. Increasing the counter width suppresses the spectral powerfalling into adjacent and alternate channels. While the suppression scale with anincreasing counter width, the effect of suppression of unwanted radiation in the300 kHz channel of the MICS mask diminishes when the Counter Width equals 4.No further improvements could be detected during simulation, when increasingthe ROM precision and clock ratio beyond 4.

Parameter ValueCounter Width 4ROM Precision 4

Clock Ratio 4

Table 6.1: Parameter values.

The ramp-up ratio is chosen to be the smallest value possible for which thefrequency spectrum still comply to the MICS spectral mask. A small ramp-upratio is chosen in order to minimize the bit error rate.

6.1.4 Direct Multiplexing

The simple concept of switching between four phases to drive the power amplifierpresented in section 6.1.1 could be expanded to have more than four phases, i.e. toswitch between signals with less than 90 degree phase difference. One modulatorbased on this concept is proposed in this thesis.


When the symbols change the modulator switches between several intermedi-ate phases one after another to reach the correct phase shift. Since the modulatorswitches between signals that are closer in phase to each other than with the archi-tecture previously presented in 6.1.1, this modulator could potentially generateless spectral re-growth. Constant envelope behavior is also improved as the phasetrajectory becomes more continuous. The extra phases could be generated with aDLL or a poly-phase filter.

Spectrum Analyzer

DLL Chain/Polyphase Filter

ModulationLogic

Figure 6.5: Direct multiplexing between multiple phases.

Implementation

Two different modulator models were constructed in ADS Ptolemy. They havefour and eight intermediate phases within each symbol transition respectively.The models consist of signal generators, one for each phase, connected to switchesthat select the phase to be transmitted. The I and Q input is fed to a counter-basedlogic network that generates the switching sequence that carry out the symboltransition.

When only one bit is changed the phase changes between the two correspond-ing signal points, see figure 6.6 (a). But when both I and Q changes, both bitschange, the implemented logic only change the phase over certain paths, seefigure 6.6 (b). This was easier to realize.

6.2 FSK Modulator

A FSK modulator was constructed for comparison reasons in order to evaluatethe PSK architectures. The modulator is based on an FM modulator, or simply avariable oscillator, controlled by the data. The frequency separation and data ratecan be adjusted to accommodate different FSK modulation schemes.

Implementation

The modulator was implemented in ADS using a FM modulator building block.The modulation index is adjusted to produce FSK with a frequency separation

6.2 FSK Modulator 45

1110

00

01

(a)

1110

00

01

(b)

Figure 6.6: How symbol changes are performed when only one (a) or both (b) bitsare changed.

Spectrum Analyzer

FMData {0,1}

Figure 6.7: FM modulator based FSK architecture.

equal to the bit rate, non-coherent FSK, and half the bit rate, coherent FSK, respec-tively.

Chapter 7

Simulation Results

This chapter summarizes the performance of the simulated architectures. Thepresented measurements includes: phase- and IQ-transition characteristics, Eb/n0and ramp-up ratios for different data rates. Conclusions from the results arediscussed in chapter 8.

7.1 Overview

Simulations for measuring the required Eb/n0 i.e. the ratio between required en-ergy per bit and the single ended thermal noise, were performed at the data rates80, 120, 150, 223 and 250 kbit/s. The result is depicted in figure 7.1. The data rates80, 150 and 223 kbit/s were chosen as these are the maximum data rates where thesimple QPSK architecture, the non-coherent FSK modulation and MSK modula-tion respectively would fit the MICS spectral mask. To get more data points, thearchitectures were also simulated at 120 and 250 kbit/s. All data points includedin the results are from successfully demodulated signals and in compliance withthe specified spectral mask according to the methodology described in chapter 5.

An overview of the result from the Eb/n0 simulations is presented in figure7.1. The signal and noise energy were calculated over a bandwidth including98% of the total signal power. In the simulation the architectures were simulatedtransmitting 2000 symbols with no errors as described in 5.3. This test indicatesa BER of no more than 10−3 with a confidence level of 86% or 1.5 ∗ 10−3 with aconfidence level of 95%, [1].

From section 2.2.1 figure 2.5 the Eb/n0 required for a BER of 10−3 is 2.4 dBhigher for coherent FSK than for QPSK. This difference increase to roughly 3 dBat lower error rates. In figure 7.1, the results from the QPSK architecture withoutfiltering is used as a reference to the theoretical signal to noise ratio for FSKmodulation. The theoretical SNR for coherent FSK is marked by a gray band2.5 to 3 dB higher than the unfiltered QPSK for the same BER. Also a gray bandbetween 4 and 4.5 dB higher than the unfiltered QPSK is included to show thesame margin but for non-coherent FSK. When simulating FSK for reference the

47

48 Simulation Results

highest data rate with minimum tone spacing1 were 150 kbit/s and 223 kbit/sfor non-coherent and coherent FSK modulation respectively. In the figure this isshown by only marking the gray band for non-coherent FSK up to a data rateof 150 kbit/s. The band for coherent FSK is drawn up to 223 kbit/s after whichthe band is broadened to indicate that FSK would need to be filtered somehow inorder to reach higher data rates while maintaining the MICS mask.

80 120 150 223 2507

8

9

10

11

12

13

14

15

16

17

18

Data Rate (kbit/s)

Eb/n

0 9

8%

(dB

)

Direct Multiplexing 8


PLL + Dither

PLL

Unfiltered QPSK

Figure 7.1: Plot of the Eb/n0, the ratio between required energy per bit and thesingle ended thermal noise, using the bandwidth containing 98% of the signalpower. The gray bands represent the theoretical Eb/n0 for coherent and non-coherent FSK.

7.2 Unfiltered QPSK

The unfiltered QPSK architecture was tested at 80 kbit/s, which is the highestdata rate where this architecture comply with the MICS spectral mask.

The unfiltered phase transitions are sharp, as can be seen in the phase diagramin figure 7.2 (b). This is also reflected in the IQ diagram where the symbol phaseand amplitude change from one symbol to the next in straight lines causing largeamplitude variations, see figure 7.2 (a).

A data rate of 80 kbit/s is low compared to the performance of other MICStransmitters discussed in chapter 3. The unfiltered QPSK signal occupies only asmall portion of the in band spectrum due to the unfavorable shape of the MICSmask leading to poor bandwidth utilization, see figure 7.3.

7.3 PLL Based QPSK Modulation

In this architecture, the loop-filter bandwidth was used to shape the signal inorder to keep it within the bounds of the MICS spectral mask. To minimize the bit

1As described in 2.4

7.3 PLL Based QPSK Modulation 49

(a) IQ diagram (b) Phase diagram

Figure 7.2: IQ and phase diagram for simple QPSK architecture, phase diagramfor a data rate of 80 kbit/s.

Figure 7.3: Frequency spectrum of QPSK transmitted at 80 kbit/s.


error rate, the loop-filter bandwidth was set to the highest value possible, whilekeeping the spectrum inside the spectral mask.

At 80 kbit/s the bandwidth was set to about 800 kHz to maintain a stablesystem while still allowing as fast phase changes as possible to attain as lowEb/n0 as possible. At 120 kbit/s and 150 kbit/s the bandwidth of the loop-filter was set to 84 kHz and 69 kHz respectively. The maximum data rate fornoiseless transmission with the PLL-filtering QPSK architecture is approximately180 kbit/s.

The architecture is of constant envelope type since the VCO always produce asignal with a constant phase. Hence, the perfect circle in the IQ-diagram of figure7.4 (a).

To keep the frequency spectra within the MICS mask, higher data rates requiremore shaping. Figure 7.4 (b) depicts the phase transition for 150 kbit/s bit rate.

(a) IQ diagram. (b) Phase diagram.

Figure 7.4: IQ and phase diagram for PLL architecture, phase diagram for a datarate of 150 kbit/s.

The higher degree of bandwidth efficiency compared to the unfiltered QPSKcould be demonstrated by observing the frequency spectrum where the in-bandspectra is occupied to a larger degree. The frequency spectra of the PLL-shapedQPSK signal is depicted in figure 7.5.

Figure 7.5: Frequency spectrum of the PLL-shaped QPSK signal.

7.4 PLL Based QPSK Modulation with Dither 51

7.4 PLL Based QPSK Modulation with Dither

The shaping in this proposed architecture is performed both by dithering andby setting the bandwidth of the loop-filter. To minimize the bit error rate, thetransition time between two symbols is set to the smallest value possible whilethe loop-filter bandwidth is maximized. The maximum data rate for noiselesstransmission is approximately 285 kbit/s which is significantly higher than theunfiltered QPSK.

The IQ-diagram in figure 7.6 (a) indicates constant envelope behavior like inthe previous architecture described in section 7.3. Figure 7.6 (b) depicts a phasetransition diagram with a data rate of 250 kbit/s and ramp-up ratio with 72%.The phase transitions in this architecture are smother compared to the phasetransitions of the PLL-shaped signal in figure 7.4 (b).


Figure 7.6: IQ and phase diagram for PLL with dither based architecture, phasediagram for a data rate of 250 kbit/s.

The ramp-up ratio is the ratio between the transition time and the symbolduration. The transition time is the time during which the architecture is ditheringbetween the new and old symbol value, shaping the phase transition. Simulationswere performed in order to find optimal ramp-up ratios at different data rates.See figure 7.7 for the final ratios.

80 120 150 223 2500

0.2

0.4

0.6

0.8

1

Data Rate (kbit/s)

Ra

mp

−u

p R

atio

Figure 7.7: Ramp-up ratio for PLL based modulation with dither.

The bandwidth efficiency is increased by adding dithering. Comparing thespectrum in figure 7.8 and 7.5 it is shown that the signal in 7.8 has a higher degree


of in-band occupancy.

Figure 7.8: Frequency spectrum of the PLL- and dither-shaped QPSK signal.

7.5 Direct Multiplexing

The proposed architecture with direct multiplexing was simulated with both 4and 8 intermediate phase steps. In both cases the maximum data rate simulatedfor comparison was 250 kbit/s. The maximum data rate for noiseless transmissionis 275 kbit/s. The IQ-diagrams are depicted in figure 7.9 (a) and (b) where the IQ-diagram of the eight-intermediate-step-architecture almost has a perfect circularshape. Hence, displaying a high degree of constant envelope behavior. The phasetransitions are depicted figure 7.9 (b) and (d).

The two architectures were simulated individually to extract the optimal ramp-up ratios. The result from these simulations shows that the two architecturesdisplays optimal behavior at identical ramp-up ratios. The ramp-up ratios aredepicted in figure 7.10.

The direct multiplexing architectures achieve approximately the same in-bandoccupancy. The lower Eb/n0 ratio achieved by the direct multiplexing architecturescould be explained by a higher degree of in-band occupancy compared to theother simulated architectures, see figure 7.11. The main difference between thedirect multiplexing architectures aside from the difference in Eb/n0 ratios is theattenuation of out-of-band frequencies.

7.5 Direct Multiplexing 53


(c) IQ diagram. (d) Phase diagram.

Figure 7.9: IQ and phase diagram for direct multiplexing architecture, phasediagram for a data rate of 250 kbit/s. 4 intermediate steps are shown in (a) and(b) and 8 are shown in (c) and (d).

80 120 150 223 2500

0.2

0.4

0.6

0.8

1

Data Rate (kbit/s)

Ra

mp

−u

p R

atio

Figure 7.10: Ramp-up ratio for the direct multiplexing architectures.


(a) Spectrum using 4 intermediate steps.

(b) Spectrum using 8 intermediate steps.

Figure 7.11: Frequency spectrum for the direct multiplexing architectures.

Chapter 8

Conclusion

This chapter presents the conclusions made from the simulations and the overviewof architectures presented in chapter 3.

8.1 Evaluating the Results

This section discusses the results presented in chapter 7. A brief discussionabout additional hardware needed in PSK modulation for each architecture isalso presented using the FSK architectures in chapter 3 as a baseline. The givendifferences in Eb/n0 discussed in this section refer to the theoretical differencebetween QPSK and FSK described in 2.2.1. The numbers assume a BER of 10−3.

8.1.1 PLL Based Modulator

By using the PLL loop filter to shape the symbol transitions, the data rate couldbe increased from 90 kbit/s to 150 kbit/s. However, the increase in data ratecomes with the cost of a significantly deteriorated Eb/n0 ratio. At 150 kbit/s thePLL architecture need about 3.41 dB higher Eb/n0 than the theoretical Eb/N0 forcoherent FSK and 1.91 dB higher than non-coherent FSK.

Some of the FSK architectures1 covered in chapter 3 states compliance to theMICS mask at 150 kbit/s and higher data rates. Hence, a higher Eb/n0 ratio is notoffset by a superior data rate. This PSK architecture therefore do not seem to becompetitive both in regard to Eb/n0 ratio and data rate.

If power consumption was of less importance, loop filter shaping could proveto be a simple way to increase data rate from 80 kbit/s in MICS applicationsutilizing PSK modulation. Albeit to the limited data rate of 150 kbit/s.

1For example [10] and [12]

55

56 Conclusion

Additional Hardware

A PLL is obviously needed in the PLL architecture. Hence, the additional costin terms of power has to be considered. In chapter 3, transmitter architectureswithout PLL:s were discussed utilizing FSK modulation and distributed feedback.Compared to these FSK architectures, the PLL based PSK architecture needsadditional hardware like e.g. frequency divider and PFD. Further hardware isneeded in order to generate the four phases of the quadrature signal. See table8.1.

8.1.2 PLL Based Modulator with Dither

By adding dithering circuitry to the PLL based modulator discussed in the sectionabove, data rate and Eb/n0 ratio of this proposed architecture is improved. At adata rate of 150 kbit/s the Eb/n0 is 0.7 and 2.2 dB lower than that for coherent andnon-coherent FSK respectively. This is an improvement compared to the PLL-loop-filter architecture. The Eb/n0 ratio deteriorates sharply at data rates above150 kbit/s. At the data rate of 223 kbit/s the Eb/n0 ratio has increased to 4.67 dBhigher than the theoretical ratio for binary FSK.

This architecture do not seem competitive compared to current FSK architec-tures due to the poor Eb/n0 ratios at data rates above 200 kbit/s.

Additional Hardware

As with the PLL architecture (discussed in section 8.1.1), the PLL with ditherwould need a PLL and hardware to generate the four phases. In addition, it wouldalso need to dither between the phases during symbol transitions. This ditheringwill occur at high frequencies adding further to the global power consumption.See table 8.1 for an overview of additional hardware needed.

8.1.3 Direct Multiplexing

Two “Direct Multiplexing” architectures are proposed in this thesis and were sim-ulated using different number of intermediate phases during symbol transitions,one with four and one with eight intermediate phases. At a data rate of 150 kbit/sboth architectures require an Eb/n0 ratio 1 dB lower than that of coherent FSK and2.5 dB lower than non-coherent FSK. The advantage of using a higher number ofintermediate phases becomes apparent at data rates higher than 150 kbit/s. At223 kbit/s the architecture using 4 intermediate phases has an Eb/n0 ratio 0.6 dBhigher than coherent FSK while the architecture using 8 intermediate phases hasan Eb/n0 ratio 0.42 dB lower than coherent FSK.

The direct multiplexing architecture using 8 intermediate phases are, com-pared to the other simulated PSK architectures, the most competitive architectureat data rates over 200 kbit/s.

8.2 Final Conclusion 57

Additional Hardware

The direct multiplexing architecture does not utilize the filtering techniques de-scribed in the preceding architectures and could therefor be designed withoutthe use of a PLL. Taking advantage of the relaxed frequency deviation require-ments of the MICS standard a distributed feed-back architecture could possibly beused as described in 3.1.1. If no channel selectivity is needed, an edge-combinerbased architecture (see section 3.1.2) operating at low frequency could be usedto generate the operating frequency. In order to use these architectures in PSKapplications additional hardware is needed to generate and switch between thephases. Typically by the use of DLL:s and multiplexers. The additional hardwareneed are listed in table 8.1.

Architecture PLL Dither Generate Phases MultiplexerPoly-phase DLL 20-36 4 L 4 H 20-36 M

PLL X X XPLL + Dither X X X X

Direct Multiplexing X X

L = Low Speed; M = Medium Speed, H = High Speed

Table 8.1: Additional hardware needed in PSK modulation.

8.2 Final Conclusion

The result from this thesis suggest that the simplified PSK architectures presentedare not competitive compared to current FSK architectures at higher data rates.The benefits generally attributed to PSK, i.e. lower transmitted signal powers andhigher bandwidth efficiency, is lost due to the amount of filtering needed to fitthe PSK frequency spectra within the MICS mask. However, the presented PSKarchitectures could prove competitive at lower data rates below 230 kbit/s. WhatPSK architecture to use is dependent on the targeted data rate. The PLL basedarchitectures are a viable alternative at data rates up to about 120 kbit/s wheresthe multiplexing modulators are preferably used at data rates above 120 kbit/sto about 230 kbit/s. An overview of data rates and suitable architectures issummarized in figure 8.1.

Architectures utilizing FSK modulation would need some means of shapingat data rates above 230 kbit/s but are less exposed to a deteriorated Eb/n0 ratio,due to a more favorable shaped frequency spectra defined by the MICS mask.

58 Conclusion

UnfilteredQPSK

PLL

PLL + Dither

80k 90k 120k


150k 223k


FSK

Figure 8.1: Graph showing what data rates could be considered for which archi-tecture.

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a study on qpsk modulator architectures for ultra low

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