ECE 734 Project Proposal (10/2000)Huaibin Yang, ID 9017919045Emal: hyang@cae.wisc.edu

A Survey of DDFS Architecture and ImplementationBackgroundFast frequency switching is crucially important in modern wireless communication systems such as TDMA/CDMA digital cellular systems and spectrum-spread wireless LANs. For example, the TDMA system may require that the carrier frequency have to be switched during a signal slot, that is, the change must be accomplished within 100us. Linear phase shifting is also crucial in any system that uses phase shift keying modulation techniques. Such system includes IS-95, IS-94, GSM, DCS-1800, CDPD and several others. Direct Digital Frequency Synthesizer (DDFS) can achieve fast frequency switching in small frequency steps, over a wide band. Also it provides linear phase and frequency shifting with good spectral purity. So, DDFS is best suited to use in the above communication systems. A further requirement for DDFS is low power consumption budget, especially for portable wireless terminals.

MotivationI have discussed fundamental frequency synthesizer techniques, Phase Lock Loop (PLL) and DDFS in the ‘in-class presentation’, and focused on the basic DDFS architectures such as RAM-based and phase accumulated methods as well as some implementation examples of DDFS building blocks. A fully pipelined FA architecture for phase accumulator is presented. A simplified ROM look-up table model, aimed at reducing table size to meet power consumption budget in wireless transceivers, is introduced to give an overall conclusion that ROM size is one of the key considerations in DDFS implementation. Along this direction, I hope do more exploration on this special topic.

Project ObjectiveThis course project intends to be survey type. I will focus to discuss the low power DDFS architecture and implementation.In the first part of the project, basic DDFS concept, design and performance analysis will be presented based on some frequency synthesizer books ([1], [2]). Then I will review some “classic” papers ([3], [4]) in terms of a historical view to understand DDFS technology development and new ideas (almost all papers about DDFS cite [3] at the first place). Then with above background knowledge, the main part of the project comes to explore the most newly papers ([5], [6], [7], [8], [9], some will be added into this list during the progress of the project), which bring new architectures and implementations to reduce power consumption of DDFS in wireless applications. The book ([10]) addresses almost every topic about DDFS and collects the bunch of papers before 1996. It is a good reference if extending the discussion of DDFS further not only for low power implementation. Conclusion and some discussions will be given in the last part of project report.

PROJECT REPORT

ABSTRACT

Direct Digital Frequency Synthesizer (DDFS) can achieve fast frequency switching in small frequency steps, over a wide band. Also it provides linear phase and frequency shifting with good spectral purity. J.Tierney proposed the DDFS idea in 1971[3]. With development of VLSI technology and requirement of modern communication systems, since 1980’s, DDFSs have been widely used in wireless transceivers and many kinds of frequency synthesizer systems especially which impose high demands on frequency synthesizer’ agility.

A standard DDFS architecture consists of accumulator, ROM lookup table, DAC and some reconstruction filters. [1] gives the analysis of spurious effects due to phase truncation of accumulator and finite word length effects of ROM lookup table. Among all building blocks of DDFS, ROM represents both power and performance bottlenecks [11]. Reducing ROM size and power dissipation level are main concerns in this survey.

Early techniques to reduce ROM size are Sunderland’s architecture [12], which leads to 50% reduction of ROM size. Nicolas’s architecture [13] is a further optimization and enhancement of Sunderland’s. In the recent decade, many efforts have been done to change their architectures to get smaller ROM, and even ROM-less. Bellaouar ([5], [7]) proposed a new architecture of only 16-point small lookup-table size, used in wireless communication. Yamagishi [8] observed that reducing the bit number of ROM output is more effective than reducing ROM storage size in decreasing the power dissipation level, so his implementation aims at smaller number of ROM output bit. Hegazi [9] found that traditional DDFS architecture has different number of sine wave samples when DDFS outputs different frequencies. He introduced a method of generating the fixed number of sine wave samples for different output frequencies. Based on this point, his implementation is ROM-less. So far, all DDFS’s architectures are ROM-based. Mortezapour [6] gave the most dramatic change to the traditional DDFS architecture. That is, replacing the ROM with a Non-linear DAC. The phase accumulator’s outputs will be directly as the inputs of a non-linear DAC for generating sine wave. So, the design of non-linear DAC becomes the key consideration in his paper.

The remaining part of this survey is organized as the following three sections. Section I introduces basic DDFS concepts; Section II surveys ROM compression techniques; Section III illustrates two ROM-less designs.

SECTION I: DDFS Introduction

Basic concept

A basic diagram for the standard DDFS is shown in Figure 1. Almost all DDFS are composed of these same fundamental building blocks, although with some enhancements or modifications. J.Tierney presented the idea at [3] in 1971.

It uses an M-bit accumulator and a sine function ROM lookup table. This block is clocked with frequency Fclk. For each of clock period, the M-bit input word is added to the accumulator. The output of the accumulator addresses the ROM lookup table to generate a K-bit digitized sine value. Then this value is converted to an actual analog voltage by D/A converter. Since the DDFS is essentially a sampled system, the D/A output should normally be passed through a reconstruction filter, which removes unwanted alias frequencies. Finally, the D/A output is passed through an ideal hard limiter in order to remove any residual AM that may be present.

The minimum frequency resolution of the DDFS is

.

The output frequency is given as

where FIW is frequency input word.

Design considerations

Representation of the Ideal DDFS Output Spectrum

,

where h(t) represents the output sample-and-hold, h(t) = 1 for and 0 otherwise. Tc = fclk –1 .

1. Phase Truncation Related Spurious Effects

If M of FIW is large, it is impractical that the bit width of the accumulator feedback input is M. Usually, we use W<M bits in the basic architecture to address the sine lookup table. In this phase truncation case,

.

[1] gives the DDFS output:

,

where e(n) represents the phase error at each clock instance due to truncation, and provides the equation for the magnitude of the largest spur in the spectrum:

whereB = number of accumulator bits truncatedFr = integer representation for FIW

= the greatest common divisor between Fr and 2 B This equation represents an important finding that the magnitude only depends on Fr through the greatest common divisor factor . Also [1] shows the algorithm for determining the discrete output spectrum of the DDFS in the presence of phase truncation. The conclusion is that if values of Fr have the same value of , the spurious output amplitudes and numbers are unchanged. Only the position of each spur in the output spectrum is altered.

2. Lookup Table Finite Word Length Effects on Spectral PurityFinite quantization in the sine lookup table sample values leads to a DDFS output spectrum impairments. Here [1] gives an result signal-to-noise ratio (CNR) at the DDFS output:

For example in D=10 bits, Fclk = 40 MHz, CNR = 138dBc/Hz. Also [1] analysis the spurious level in the worst case. In this example, it is about –60 dBc.

SECTION II: ROM Size Compression

For DDFS, transforming the phase accumulator phase value to sin() is particularly crucial if table storage size is to be kept reasonable because, ROM represents both power and performance bottlenecks[11]. Each additional bit used in the lookup table process

potentially represents a doubling of the required table storage space. ROM compression methods are used to minimize the ROM size.

1. Sine waveform symmetryDue to the symmetry of the function /2 and , with proper manipulation of the phase and amplitude, lookup table samples can be stored for phase values spanning the 0 to /2. That is, the accumulator value is reflected into the first quadrant by computing = mod /2.

2. Sunderland architecture (Using trigonometric identity)[12]

Further technique used to compress ROM size is presented in [12]. is decomposed into a sum of three angles

= + β +γ. Using the basic trigonometric identity:

Sin( + β +γ) ≈ sin(( + β) + cos(α)sin(γ).So, one large size ROM can be split two smaller ROMs. The upper ROM, called Coarse ROM, contains the quantity of sin(( + β). The lower ROM contains the quantity of cos(α)sin(γ) and is called Fine ROM because its size can be considerably smaller than the upper one due to sin(γ) <<1. This architecture is called Sunderland architecture conventionally.

3. Nicholas architecture (Sine-phase difference, Using Tylor series expansion for sin() )[13]

According to the first-order Taylor series expansion:f(x) = sin( x /2) – x /2,

We store f(x) which has the smaller dynamic range resulting in further reduced table size.

4. Paper [5] proposed a new architecture for small lookup-table size.

In this architecture only 16 points are stored. The final sine and cosine waveform values are computed through the linear relationship between the sample points. It gives experimental results about a DDFS with 60-dBc spectral purity, 29-Hz frequency resolution, and 9-bit output data for sine function generation. The DDFS is implemented in 0.8-um CMOS. Experimental results verify that the average power dissipation of the DDFS logic is only 9.5mW(at 33 MHz, 3.3V).

The paper’s basic idea and implementation is illustrated as follows:

Similar to the architectures of the above in [8] and [10], this one uses Taylor-series-based mapping technology as well, but linear interpolation is used between consecutive points stored in the ROM. In every interval [ i

, i+1 ]

sin = sin i + ( - i

) + sin

[ i , i+1

]. i and i+1 are two successive stored phases. The ( - i) term represents

the LSB’s of the phase , while i represents the MSB address of the ROM. The

interpolation coefficient for sin is also stored in ROM. Since it is multiplied by a small number ( - i), only few MSB’s of the coefficients need to strore.

Its architecture is shown as the following figure:

An N-bit accumulator is used for the phase control. The choice of N depends on the required frequency resolution. The m+n+3 MSB’s of the output of the accumulator are used of the subsequent blocks as the phase . The most significant three bits of the phase accumulator output are utilized to control the generation of the full sine wave, as is explained below. M bits( MSB’s of m+n remaining bits of the phase) are used to address the ROM for sine and cosine and the interpolation coefficients. The lower significant n bits (LSB’s of m+n bits of the phase) represent ( - i) in the interpolation formula.

The third MSB is used to decrease the address of the ROM and permit switching between sine/cosine waves for the first quarter of the sine wave. It is then XOR’ed with m+n bits (LSB’s) of the phase word. The second MSB is XOR’ed with the third MSB to select (through MUX 1 and 2) between samples stored in the ROM. The first MSB is used to generate the last half of the wave and as a sign bit.

As the summary, the comparison of relative ROM Sizes using previous compression techniques are compared, (quoted from paper [5])

Compression Technique ROM size in normalized bitsSine/Cosine Symmetry 39.38Sunderland’s Technique 10.46Nicholas’s Technique 2.46Bellaouar’s Technique 1

5. Reducing output bit number of ROM [8].

Yamagishi [8] proposed a method to further reduce the ROM size. His idea is based on the statement that reducing the number of bits output by the ROM is more effective in decreasing the power level than is reducing the number of words input of the ROM. He gives the power dissipation characteristics of the ROM in the following graph.

For example, when the storage of ROM is reduced to 1024 words from 4096 words, that is, the number of input bits is reduced from 12 to 10, the reduction of supply current is from 3 mA to 2.8 mA, only about 7%. However, the number of output bits reduced from 8 to 6, the power reduction is about 30%. This is because most current from the ROM is dissipated in sense amplifiers.

To achieve few output bit number, they devised a double-trigonometric-approximation architecture for the sine-wave lookup table. The graph below demonstrates the general idea of this architecture.

This architecture generates the familiar quarter cycle sine waveform using two triangle waveforms A and B, and approximation error C. It is no need to pay attention to the generation of A and B using either ROM or complex processing, because data for waveform A is equal to a part of the input phase data and data for waveform B is also equal to a part of the input phase data that inverted. This data can be changed from input data by few XOR gates depending on bit-width. Only approximation error data C must be stored in ROM. However, the ROM required capacity is small, since data A and B are removed from the sine waveform.

This architecture is similar with the Nicholas’s architecture, but aiming at reducing both input and output bit number. We can see this through the following implementation architecture that is given in this paper.

With this architecture, ROM output data is decreased by 3 bits. That is, this architecture compresses the ROM output bit-width from 9bits (the conventional ROM compression technique using quarter wave symmetry of a sine wave) to 6 bits, which results in a more than 30% reduction in ROM power dissipation.

SECTION III: ROM-less Architecture and Implementation

1. An ROM-less DDFS architecture with constant Over Sampling Rate

In conventional DDFS architecture, all ROM addresses are visited only for the minimum output frequency, on the other hand, only two addresses per cycle are used to generate the maximum frequency. Based on this observation, paper [9] proposed an architecture that a fixed number of sine wave samples is generated during each output cycle with a time spacing depending on the frequency being synthesized. The following is the block diagraph for the new architecture.

Let’s define over-sampling ratio (OSR):

Where W is input frequency word and N is the number of bits in the accumulator. In this architecture another accumulator (counter) is used to synthesize the sampling

interval using its over flow signal as output. Only the overflow signal is used as an indicator to the sampling interval.

The sampling frequency is given as

The number of samples per cycle is chose to be 2 s. The desired output frequency is therefore given as:

Note that in this architecture, Nyquist rate is not of concern since the accumulator’s overflow signal is not used as an output signal. It is used to increment the counter whose output is the number of the sine wave sample to be generated. A very small ROM block can be used to map the sine amplitude, e.g. an OSR of 4, the small ROM is only 8 addresses.

In the above example, since only 8 ROM samples are used, there is no need to use a ROM to map the sine wave sample’s amplitudes. A tailored DAC can give sine waves directly. It is equivalent to a three-bit DAC that has eight samples switching pool.

This architecture mainly improves the frequency switching speed and reduces die area because of ROM-less and simplified DAC. The power dissipation with an additional accumulator is the same as for the conventional architecture because accumulator power dissipation is about 50% the total power of DDFS.

2. ROM-less DDFS Architecture with non-linear DAC

The paper [6] proposes a new architecture. It proposed a design technique that uses nonlinear digital-to-analog converter (DAC) to replace look-up table. Significant saving in power dissipation results from this ROM-less implementation. The experimental results for a 3.3V supply are both 4 and 94 mW at a clock rate of 25MHz and 230MHz, respectively.

Here illustrates its new idea. The new architecture with nonlinear DAC shows as follows:

The function of the nonlinear DAC is to convert the digital phase information from the phase accumulator directly into an analog sine output voltage. If this proposed architecture requires the same number of bits of amplitude resolution as the conventional ROM based DDFS does, the performance of this architecture will be theoretically identical to the conventional one. The main advantage of paper [6]’s architecture is that it does not require a ROM look-up table. Therefore, the power dissipation will be less than that of a conventional DDFS if the non-linear DAC consumes about the same power as a linear DAC.

First, let’s focus on its implementation of non-linear DAC

where DAC output vo is a function of the complementor output st(n) and the MSB of the phase accumulator output. Assume that the peak value of the output sine wave is equal to 2 i –1, where i defines the number of bits of amplitude resolution of the sine wave.

1, the integer j represents the number of MSB bits output from the phase accumulator that is used as input bits to the nonlinear DAC.

Equation (2) gives a practical realization using iteration method. If DAC has 2 j-2 cells, for the kth DAC cell where k= 0, ……,2 j-2 –1, the output is ok.

Based on (1) and (2) the output value of the kth DAC cell can be determined as the following iteration equation:

The omax = 2 i –1 k/2 j-1 when k=0;

The value omax will directly affect the size of the DAC cells since the size of each DAC cell will be unified to have the same size and proportional to omax number of unit resistors

or current sources to simplify the layout of the entire nonlinear DAC. Some important observations from the above equation:

1. omax doubles when i is increased by 1 bit and approximately halves when j is increased by 1 bit.

2. for a fixed amplitude resolution (e.g., for fixed I), the number of DAC cells doubles when j is increased by 1.

As a result of these two observations, the overall area of the DDFS will only increase slightly for increasing the phase information to the non-linear DAC, since increasing j haves the omax in spite of doubling the number of omax.

Because in ROM-based DDFS architecture increasing the value of j by 1 bit means increasing the number of input address bits of the ROM by 1 bit and hence, doubling the ROM size. Therefore, this ROM-less DDFS has advantages over the ROM-based on in terms of power dissipation and die area.

The implementation of ROM-Less DDFS Using Nonlinear Resistor String DAC

1. Concept diagram

The input signal st(n) and the MSB of the phase accumulator are first decoded so that only one of the switchs will turn on and, hence there is only one low impedance path between the resistor string and the input of the buffer.

The resistance value in each DAC cell is equal to okR, and the total resistance of the entire resistor string s equal to 2 i+1 R, where R represents the unit resistance value. To simplify the layout of the entire nonlinear DAC, okR is unified to have the same size as omaxR.

2. Low-ohmic resistor ladder to reduce harmonic distortion.Because high amplitude resolution requirement could result in a long resistor string, nodes at different locations along the resistor string will have different RC time constants. This effect can cause harmonic distortion at the output.Resistor Ladder

Each resister in the low-ohmic resistor ladder is in parallel with 2 i+1-m resistors in the original resistor string. Therefore, the maximum resistance of the resistor string, which corresponds to the node at the middle of the resistor string, will drop from 2 i-1 R to 2 m-2

(r||2 i+1-m R)3. Quadrature output implementation

In communication systems, DDFS with quadrature (sine and cosine) outputs is desired. In conventional DDFS two linear DAC’s are needed and an extra digital multiplexer is required. In this paper, some design efforts are added to non-linear DAC cells to simplify the layout and to further reduce the area requirement and the power dissipation.

Wrapping around resistor string show as the following figure. DAC cells are selected by the row and column decoders, which are controlled by the output bits of the complementor. Each DAC cell has four resistors.

The terminal nodes of the resisters are connected to four global wires through four MOSFET’s as shown in this figure.

When a DAC cell is selected, four voltages representing four different sine voltages with 90o phase difference can be accessed simultaneously on the four global wires. A quadrant decoder, using the three MSB’s of the phase accumulator output, selects two global wires and connects them to two output buffers.

In this scheme, the two DAC’s for sine and cosine outputs can share not only the resistor string but also the row and the column decoders.

The paper gives an experimental result based on this design principle. The DDFS with a clock frequency of 25 MHz and voltage supply of 3.3V only consumes less than 4 mW of power dissipation while a power dissipation of 30-40mW is usually required for the same range of clock frequency.

CONCLUSION

Several ROM compression techniques and ROM-less designs have been described. Sunderland’s, Nicolas’s and Bellaouar’s ways for calculating ROM values are based on numerical optimization. In an implementation of Bellaouar’s architecture, only 16-point ROM size is needed. A DDFS with such a ROM consumes about 9.5mW when at 3.3V supply and 33MHz clock frequency. Yamagishi devised a double-trigonometric-approximation architecture to get few ROM output bit. Because most of current from the ROM is dissipated in sense amplifiers, the few output bit can reduce power dissipation dramatically. The author claims 30% further power dissipation reduction. Hegazi adds one more accumulator to traditional DDFS architecture to get constant number of sine wave samples for different output frequencies. Because every output frequency has equal number of sine wave samples, a very small ROM block can be used, e.g. 8 address.

Furthermore, 3-bit non-linear DAC can replace this small ROM. But due to additional accumulator, power dissipation remains almost same as traditional ones. The main benefits of this architecture are fast switch time and reduced die area. Mortezapour introduces A ROM-less DDFS for low-power implementation. The key is that only if the non-linear DAC consumes about the same power as a linear DAC we can get performance improvement due to ROM-less style. One such non-linear DAC is build from resistor string and uses low-ohmic resister ladder to reduce output latency. A reported DDFS with 3.3V supply and 25MHz clock consumes about 4mW power. The above surveyed DDFS design techniques aim at reducing power consumption, small or non-ROM, therefore can be used in portable wireless communication systems.

ACKNOWLEDGEMENT

Thanks Professor Yu Hen Hu for his encouragement and invaluable comments.

Reference:[1] James A. Crawford, “Frequency Synthesizer Design Handbook” 1994[2] Ulrich L. Rohde, “ Microwave and Wireless Synthesizers Theory and Design”1997[3] A Digital Frequency SynthesizerJ.Tierney, C.M.Radre, and B.GoldIEEE Transactions on Audio and Electroacoustics, March 1971[4] CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum CommunicationsD.A.Sunderland, R. A. Strauch, S.S. Wharfield, H.T. Peterson and C.R. ColeIEEE Journal of Solid-State Circuits, August 1984[5] Low-power direct digital frequency synthesis for wireless communications Bellaouar, A.; O'brecht, M.S.; Fahim, A.M.; Elmasry, M.I. Solid-State Circuits, IEEE Journal of, Volume: 35 Issue: 3 , March 2000 Page(s): 385 -390URL: http://ieeexplore.ieee.org/iel5/4/17940/00826821.pdf[6] Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter Mortezapour, S.; Lee, E.K.F. Solid-State Circuits, IEEE Journal of, Volume: 34 Issue: 10 , Oct. 1999 Page(s): 1350 –1359URL: http://ieeexplore.ieee.org /iel5/4/17209/00792601.pdf[7] A low-power direct digital frequency synthesizer architecture for wireless communications Bellaouar, A.; Obrecht, M.; Fahim, A.; Elmasry, M.I. Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999 Page(s): 593 -596URL: http://ieeexplore.ieee.org/iel5/6310/16877/00777351.pdf[8] A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication Yamagishi, A.; Ishikawa, M.; Tsukahara, T.; Date, S.

Solid-State Circuits, IEEE Journal of, Volume: 33 Issue: 2, Feb. 1998 Page(s): 210 –217URL: http://ieeexplore.ieee.org/iel3/4/14352/00658622.pdf[9] New direct digital frequency synthesizer architecture for mobile transceivers Hegazi, E.M.; Ragaie, H.F.; Haddara, H.; Ghali, H. Circuits and Systems, 1998. ISCAS' 98. Proceedings of the 1998 IEEE International Symposium on, Volume: 3, 1998 Page(s): 647 -650 vol.3URL: http://ieeexplore.ieee.org/iel4/5627/15080/00704095.pdf[10] Derect Digital Frequency Synthesizers, A Selected Reprint VolumeIEEE Ultrasonics, Ferroelectrics and Frequency Control Society.[11] Digital Techniques in Frequency SynthesisB.GoldbergNew York: McGraw-Hill, 1996[12] CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communicationsD.Sunderland, R.Strauch, S.Wharfield, H.Peterson, and C.ColeIEEE J. Solid-state Circuits, vol. SC-19, pp 497-505, Aug. 1984.[13] The optimization of direct digital frequency synthesizer performance in the presence of finite word length effectsH.Nicholas, H.Samueli, and B.Kim42nd Annu. Frequency Control Symp., 1988, pp.357-363