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Digital Frequency Detector based on Multiphase Ring Oscillator

Choong-Yul Cha, Minjae Lee1, Jaesup Lee, and Taewook Kim

Samsung Advanced Institute of Technology, University of California, Los Angeles1

Mt. 14-1 Nongseo-dong Giheung-gu Yongin-Si Gyeonggi-do, Korea, 446-721

Tel: +82-31-280-9648, E-mail: choongyul.cha@samsung.com

AbstractA new high resolution digital frequency detector architecture based

on multiphase ring oscillator is proposed, and it uses the time resolution

of fast-operating deep sub-micron MOS transistor. The proposed DFDis implemented with 65nm CMOS technology. The measuredfrequency resolution is amount to 75dBc with 10.2MHz input signal.Fabricated digital frequency detector draws about 4mA in 1.2V supplyvoltage.

IntroductionAs the operation speed of deep sub-micron MOS transistor becomes

higher than hundred GHz, the analog-incentive mixed-signal circuitsare being digitalized by using the tens pico-second time-resolution of

fast-operating MOS transistor. And several achievements have beenreported already in PLL and ADC design area [1-2].

This fine time-resolution of deep sub-micron MOS transistors can

also be applied to the design of high resolution digital frequencydetector (DFD) converting the frequency of input signal to a highresolution digital value. The previously reported frequency-to-digitalconverter (FDC) detects the frequency of input signal with the edgediscrimination or phase differentiation, and the edge or phaseinformation of input signal is detected with D flip-flop or digitalcounter. In the previous FDC, because the phase detection is onlycarried out per unit period, the sampling frequency must be muchhigher than the frequency of input signal for the fine resolution offrequency detection [3-4]. Thus, the application of previous FDC islimited to the low frequency input signal. In this paper, we propose anew high resolution DFD architecture based on multiphase ring

oscillator, and which use the time resolution of sub-micron MOStransistor and removes the necessity of the higher sampling frequencyfor high frequency resolution.

Proposed Digital Frequency Detector Architecture

Fig.1 Concept diagram of the proposed DFD based on multiphase ring oscillator

Fig.1 shows the concept diagram of the proposed DFD based onmultiphase ring oscillator. In Fig.1, the digital phase sensoraccumulates the phase information of the free-running ring oscillatorand the phase information is latched at the rising edge of REF. Thelatched phase information is converted to the frequency informationwith differentiator. The differentiator output dREF=f(RING)/f(REF),where, f(RING) and f(REF) are the frequency of ring oscillator andREF, respectively. In here, the frequency resolution of dREF is

increased with the increase of the oscillation frequency of ringoscillator, and which of ring oscillator is also increased with thescaling-down of CMOS process.

However, dREFcannot be directly used as an absolute value sincethe oscillation frequency of free-running ring oscillator is an un-knownvalue. As shown in Fig.1, by using a digital divider and two FDCsoperated with REF and SIG, the frequency relation between SIG andREF can be detected regardless the un-known oscillation frequency offree-running ring oscillator. In Fig.1, since dSIG=f(RING)/f(SIG) anddREF=f(RING)/f(REF), Fout=dREF/dSIG=f(SIG)/f(REF), where

f(SIG) is the frequency of SIG, andFout is the relative digital frequencyof SIG to the frequency of REF which is already known.

Fig.2 Phase quantizer of DFD

Fig.2 shows the phase quantizer of DFD which is composed ofmultiphase ring oscillator, counter and latches. The counter and latchesare equivalent to the digital phase sensor in Fig.1. The digital countercounts the unit period of ring oscillator and the counting value issampled at the rising edge of REF and SIG. As shown in Fig.2, latchesattached in every delay cell of ring oscillator sample the state of ringoscillator at the rising edge of REF and SIG. With the state ofoscillators delay cell, the fractional phase of ring oscillator can bedetected. And, the fractional phase detection improves the frequencyresolution of DFD.

Fig.3 Digital frequency generator of DFDFig.3 shows the digital frequency generator of DFD which calculates

978-1-4244-1805-3/08/$25.00 2008 IEEE 2008 Symposium on VLSI Circuits Digest of Technical Papers 84

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the relative digital frequency of SIG to the frequency of REF. In thebeginning, digital frequency generator detects the fractional phase ofREF and SIG using the state of ring oscillators delay cells. And then,the total phase of SIG and REF is calculated by summing the detectedfractional phase and the integer phase from the digital counter. Digitalfrequencies dREFand dSIG are calculated with differentiator. Finally,the digital frequency relation Fout between f(REF) and f(SIG) iscalculated with the digital divider.

Circuit Implementation and Experimental Results

Fig.4 (a) Multiphase ring oscillator with latches and (b) time interpolation

Fig.5 (a) delay element of ring oscillator and (b) comparator (latch)

Fig.4 (a) shows the block diagram of multiphase ring oscillator withlatches. Each node of delay cells is connected to latch which detects thestates of delay cell at the rising edge of REF signal. In addition,interpolation latches can sense the signal changes on inputs (Vx) andoutputs (Vy) of each delay cell as shown in Fig. 4(a) and (b). Theseinterpolation latches increase the time resolution of DFD as much astwice. The delay cell of ring oscillator is realized by differential type sothat it reduces noise interference. In Fig.4, only REF signal part isshown and the latches for SIG signal part are omitted. Fig. 5(a) and (b)

show the schematics of delay element of the ring oscillator andcomparator (latch).

The proposed DFD architecture is implemented with 65nm CMOStechnology. For the measurement, SIG signal is changed through

9.0MHz ~ 11MHz while 10MHz REF signal is given. Then, digitaloutput Fout is measured. With 1.2V supply voltage, the currentconsumption is about 4mA, and the oscillation frequency of ringoscillator with 32 delay cells is about 820MHz. Fig. 6(a) shows FFTspectrum of measured digital frequency outputs when the frequency ofSIG is 10.2MHz. This measured spectrum shows about 75dBc ofdigital frequency resolution. In simulation, the spectrum shows 1storder noise shaping, but the spectrum of measured results does not

show clearly the 1st order noise shaping due to unknown noise coupling.Fig. 6(b) is a plot of digital frequency output vs. SIG frequency. Within

SIG frequency from 9.4 to 10.6MHz, the deviation of digital output toideal value is less than +/-0.3%. However, the deviation of digitaloutput is abruptly increased on other SIG frequency range such ashigher than 10.7MHz or less than 9.4MHz. This abrupt increase ofdeviation is due to the synchronization problem of two clocks (REFand SIG). Fig. 7 is chip photo diagram of implemented DFD and coresize of DFD is 0.07mm

2 including analog and digital circuits together.

Fig.6 Measured (a) FFT spectrum @ f(SIG)=10.2MHz and (b) Fout and

deviation(%)

Fig.7 DFD chip (a) photo graph and (b) layout

In this paper, the new architecture of high resolution DFD withmultiphase ring oscillator is proposed and fabricated. As a result, thefunctionality of DFD is verified with measurement results and proposed DFD has achieved to 75dBc of frequency resolution. Thisnew architecture of DFD is expected to be used in many applicationssuch as PLL, ADC, etc.

References[1]B. Staszewski, et al., All-digital phase-domain TX frequency synthesizer for

Bluetooth radios in 0.13um CMOS,Proc. IEEE Solid-State Circuits Conf.,

pp.272-273, Feb. 2004.

[2]M. Z. Straayer and M. H. Perrot, A 10-bit 20MHz 38mW 950MHz CT

ADC with a 5-bit noise shaping VCO-based Quantizer and DEM circuit in013u CMOS,Proc. Symposium on VLSI Circuits, pp.246-247, June 2007.

[3]M. Hovin, et al., Delta-Sigma Modulators Using Frequency- Modulated

Intermediate Values, IEEE Journal of Solid-Stage Circuit, Vol.32, No.1,

pp.13-22, Jan. 1997.[4]M. Hovin, et al., A Narrow-Band Delta-Sigma Frequency-to-Digital

Converter, IEEE Proc. International Symposium on Circuits and Systems,

pp.77-80, June 1997.

978-1-4244-1805-3/08/$25.00 2008 IEEE 2008 Symposium on VLSI Circuits Digest of Technical Papers 8