aaaatm shared memory atm switch

8/7/2019 aaaatm SHARED MEMORY ATM SWITCH

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SHARED MEMORY ATM SWITCH

ARCHITECTURE

JIVASINGH



ATM Switch Architectures

� An ATM Switch is used to transfer cells from itsincoming links to out going links. This is know asswitching function.

� These ATM switches can be grouped into threeclasses, namely ,

� Space Division Switches

� Shared memory switches

� Shared medium switches



� A generic model of ATM Switch consists N input and Noutput ports.

� Each input port have a finite capacity buffer where cellswait until they are transferred to their destinationoutput ports.

�

An ATM switch is referred to as an output bufferingswitch if only if its output ports are equipped withbuffers.

� The input ports are connected to their out put ports via

the switch fabric. It is equipped with a CPU, which isused to carry out signalling and managementfunctions.



Shared memory switch

� Shared memory is used to store all the cellscoming in from the input ports.

� It can read and write at the same time.

� Shared memory is organized into linked lists oneper output port.

� At the beginning of the slot all the input portsthat have a cell, write into the shared memory.

At the same time all the output ports with a cellto transmit read the cell from the top of theirlinked list and transmit it out .



� If N is the no of input/output ports then in

one slot upto N cells can be written and

transmitted.If the speed of transmission is V

then the required bandwidth is 2NV.

� An output port gets hot when a lot of

incoming traffic goes to a particular port. As aresult queue of the port takes lot of the

shared memory leaving little space for other.



Cell loss

� Cell loss occurs when a cell arrives at a time

when the shared memory is full.i.e it contains

B cells.

� Cell loss occurs when a cell with destination

port i arrives at a time when the total no of

cells queued for this port is Bi i.e.queue is full.



Hitac i s ar ry s itc



Hitachi shared memory switch

� Proposed by Hitachi.

� First, cells are converted from serial to parallel

and header conversion takes place.� Cells from all the input ports are multiplexed

and written into shared memory,

�

For each linked list there is a pair of addressregisters(one to write WA one to read RA).



� The WA reg for the linked list contains theaddress of last cell of the list, which is always

empty . The incoming cell is written in thataddress . At the same time WA is updatedfrom IABF, which keeps a pool of empty bufferlocations.

� At each slot a packet from each list isidentified through the content of RA regretreived, demultiplexed and transmitted. The

empty buffer is returned to pool and RA isupdated with next cell address of the linkedlist.



Bit slicing method

� To reduce bandwidth bit slicing method isused,

� Here a cell in the linked list is stored in Kfragments over K shared memories . If wehave N links and speed of transmission is V

then required bandwidth is 2NV/K.

.



� Shared memory switch architecture has also been used

in non blocking switch with output buffering.

� If there is a dedicated buffer for each out port freespace in one port cant be used for other.

� This may result in the poor utilization of the bufferspace.

� This can be solved by using shared memory switch to

serve a number of ports.



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aaaatm shared memory atm switch

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