aalborg universitet virtual impedance based fault current...
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Aalborg Universitet
Virtual Impedance Based Fault Current Limiters for Inverter Dominated AC Microgrids
Lu, Xiaonan; Wang, Jianhui; Guerrero, Josep M.; Zhao, Dongbo
Published in:I E E E Transactions on Smart Grid
DOI (link to publication from Publisher):10.1109/TSG.2016.2594811
Publication date:2018
Link to publication from Aalborg University
Citation for published version (APA):Lu, X., Wang, J., Guerrero, J. M., & Zhao, D. (2018). Virtual Impedance Based Fault Current Limiters for InverterDominated AC Microgrids. I E E E Transactions on Smart Grid, PP(99). DOI: 10.1109/TSG.2016.2594811
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Abstract—In this paper, a virtual impedance based fault
current limiter (VI-FCL) is proposed for islanded microgrids comprised of multiple inverter interfaced distributed generators (DGs). Considering the increased fault current capability induced by high penetration of renewable energy sources (RESs), FCLs are employed to suppress the fault current and the subsequent oscillation and even instability in the modern distribution network with microgrids. In this study, rather than involving extra hardware equipment, the functionality of FCL is achieved in the control diagram of DG inverters by employing additional virtual impedance control loops. The proposed VI-FCL features flexible and low-cost implementation and can effectively suppress the fault current and the oscillation in the following fault restoration process in AC microgrids. The systematic model of the inverter dominated AC microgrid is derived, and the stability analysis in consideration of VI-FCLs is thereby studied. MATLAB/Simulink model comprised of three inverter-interfaced DGs is implemented to verify the feasibility of the proposed method.
Index Terms—AC microgrid, distributed generation, fault current limiter, interface inverter, virtual impedance
I. INTRODUCTION HE increasing penetration of renewable energy sources (RESs) has significantly challenged the modern
distribution systems in terms of bidirectional power flow in active distribution network [1], stochastic and intermittent power generation [2], different fault current capability [3], etc. In order to effectively control and manage the distributed generators (DGs), the concept of microgrid was proposed years ago to aggregate distributed sources and loads [4]. By employing the proper design and control algorithm, a microgrid can be used to enhance the reliability of distributed generation networks and reduce the operation cost. Meanwhile, by integrating microgrid controller with distribution management system (DMS), the functionality of microgrid can be further extended.
In order to improve the controllability of RESs and ensure the required power quality, power electronic inverters are widely employed as the interfaces [5]. Considering the distributed configuration of DGs, the interface inverters are usually connected in parallel [6]. A general configuration of AC microgrids is depicted in Fig. 1. It should be noted that the
This work is sponsored by the U.S. Department of Energy (DOE) Office of Electricity Delivery and Energy Reliability.
X. Lu and J. Wang are with the Energy Systems Division, Argonne National Laboratory, Lemont, IL, USA (email: [email protected], [email protected]).
J. M. Guerrero is with the Department of Energy Technology, Aalborg University, Aalborg, Denmark (email: [email protected]).
D. Zhao is with Eaton Corporation, Eden Prairie, MN, USA (email: [email protected]).
proper power sharing among different interface inverters should be achieved to avoid the unnecessary power circulation and the additional power loss. Different control strategies are proposed to realize the proper active and reactive power sharing, e.g. master-slave control [7], circular-chain-control (3C) [8], average current control [9], etc. It should be noticed that the above power sharing methods and their variants are realized based on dedicated high bandwidth communication network, which is less applicable for microgrids considering its distributed nature. Droop control and its modified versions are widely employed in microgrids [10]–[13]. Since it relies on only local information, a decentralized control diagram can be reached. Hence, it is more suitable for power sharing in microgrids compared to the communication-based methods. In order to fulfill the multiple requirements in microgrid operation and implement a systematic control algorithm, a hierarchical control diagram is proposed in [14], including the control objectives of local power sharing, voltage frequency and amplitude restoration, and active and reactive power control when interacting with external utility grid. The lower control layer of the hierarchical control diagram is reached based on decentralized control method, and the higher control layers are implemented based on low bandwidth communication links.
… …
AC Bus
Solar Array
Wind Turbine
Plug-in Vehicle
AC Loads
AC Loads
Energy Storage
Energy Storage
AC Utility Grid
Fig. 1. General configuration of AC microgrids.
Fault protection schemes should be designed properly to ensure the safe and reliable operation of microgrids. In consideration of DG participation, the protection strategies of microgrids are more complicated than conventional passive distribution systems. The DGs may lead to missing operation or sympathetic tripping of the protective devices (PDs) during fault conditions. Meanwhile, since the fault current inside a microgrid is synthesized by the upstream utility grid and DG branches, the related relay settings for conventional distribution systems should be modified accordingly [3]. Especially for inverter dominated microgrids, the inertia of inverter-interfaced DGs is lower compared to the rotation-based DGs, e.g. small hydro, diesel generator, etc., and the
Virtual Impedance Based Fault Current Limiters for Inverter Dominated AC Microgrids
Xiaonan Lu, Member, IEEE, Jianhui Wang, Senior Member, IEEE, Josep M. Guerrero, Fellow, IEEE, and Dongbo Zhao, Senior Member, IEEE
T
fault current limits are reduced due to the inverter power rating.
Various strategies are proposed to improve the protection schemes for inverter dominated microgrids. In [15], the amplitude of the inverter output current is calculated to detect the fault, and it is constrained to the maximum value during fault condition. For fault restoration, the post- and pre-fault values of the output current are compared to identify if significant change is entailed in the microgrid. In [16], the voltage magnitude regulation scheme and phase lock loop (PLL) are modified to enhance the performance during faults, and a phase angle restoration loop is employed to improve the fault ride through capability of the inverter interfaces and improve the process of post-fault recovery. In [17], the fault responses of AC microgrids with single inverter and multiple inverters are discussed, and the positive sequence equivalent P&Q model and current source model are derived for analyzing the operation of the interface inverter during faults. In [18], a fault current alleviation method is accomplished by measuring the remote voltage signal of the point of common coupling (PCC). By comparing the local output voltage and PCC voltage, the difference between the amplitudes and the phase angles are minimized to reduce the fault current. In [19], the protection strategy is implemented by using digital relays with communication capability. The failures of hardware devices and communication links are taken into account in the hierarchy of protection scheme. In [3], a multi-layer protection diagram is proposed, including load-way level, loop level, loop-feeder level and microgrid level, which is suitable for different microgrid configurations.
In order to mitigate the influence of fault current in microgrids, fault current limiters (FCLs) are studied and developed. The FCLs behave as rather low impedances in microgrids in the normal operation, while during faults, it becomes a large impedance and limit the amount of fault current. Hence, the uninterrupted operation of electrical systems can be obtained. Two types of technologies for FCLs currently exist, i.e., high temperature superconducting (HTS)-based FCL and solid-state circuit (SSC)-based FCL [20]. For HTS-based FCL, the characteristic of superconductor is utilized to change the impedance. For SSC-based FCL, it is essentially an additional power electronic converter series-connected in the power cable. The discussion of FCLs is found in existing literature. In [21], the functionality of dynamic voltage restorer (DVR) is extended to implement a SSC-based FCL and alleviate the impact of downstream fault current. In [22] and [23], additional inverters are series-connected to the feeder impedance to form a SSC-based FCL and emulate resistive or inductive impedance during faults. In [24], a unidirectional FCL is developed and placed between downstream microgrid and upstream utility grid to cope with the downstream faults. In [25] and [26], the optimal positioning of HTS-based FCLs is discussed. Especially in [26], the location of FCLs in hybrid AC and DC microgrids is studied to ensure the effective suppression of fault current. In [27], HTS-based FCL is employed to protect the key energy storage units in the system. In [28], a constrained nonlinear
programming problem is formulated to optimally select the relay settings and size FCLs.
Virtual impedance as a cost-effective and flexible approach has been employed in the control diagram of microgrids in the past years. It can be used to match the output impedance of each interface inverter and decouple the active and reactive power sharing in droop-controlled microgrids [29], [30]. Meanwhile, a virtual impedance can be also used to dampen the resonance peaks in LCL-filtered inverters to increase the stability margin [31], or emulate required damping impedance at different harmonic frequencies so that the certain harmonic components can be eliminated [32].
In this paper, a virtual impedance based FCL (VI-FCL) is proposed to suppress the fault current in islanded AC microgrids. Since three-phase faults have the highest impact on system operation, the proposed method is mainly designed for alleviating the influence of symmetrical three-phase faults. For asymmetrical faults, similar approaches can be developed by implementing VI-FCLs in positive and negative sequences, respectively. Compared to the existing methods of implementing FCLs, the VI-FCL features lower capital and maintenance costs. No extra superconducting devices or inverters are required to work as FCLs. The existing current controller in the primary control level of a DG unit does not work for limiting the fault current considering controller saturation, huge amount of fault current and low voltage at the fault location. By involving additional virtual impedance loops in the DG interface inverters, large output impedances can be implemented during faults to emulate the physical inductance and resistance in the real FCLs. Meanwhile, in normal operation, the VI-FCLs keep zero to avoid unnecessary voltage drops. Furthermore, it should be noted that by using the proposed VI-FCL, the fault ride through capability of DG unit can be enhanced. Hence, they do not need to be cut off although the fault occurs. Compared to the conventional current/voltage based protection schemes, the proposed method does not interrupt the DG operation, so the complicated resynchronization algorithm for DG reconnection can be avoided. The principle and implementation of the proposed VI-FCL is introduced in this study. Meanwhile, a systematic model of inverter dominated AC microgrids during faults is derived, and the stability analysis of the overall system is thereby analyzed. A MATLAB/Simulink model comprised of three interface inverters is implemented to verify the effectiveness of the proposed VI-FCL. Meanwhile, real-time hardware-in-the-loop (HIL) test based on OPAL-RT platform is also conducted to further verify the feasibility of the proposed method.
The following paper is organized as follows. Section II introduces the principle and implementation of VI-FCL. Section III analyzes the model of AC microgrids during faults and conduct the stability analysis of the overall control diagram with VI-FCLs. Section IV shows the simulation results for different cases. Finally, Section V summarizes the paper and draws the conclusion.
II. PRINCIPLE AND IMPLEMENTATION OF VI-FCLS
A. Principle of VI-FCL The simplified configuration of AC microgrids dominated
by multiple interface inverters is shown in Fig. 2. Each inverter interfaced DG unit is modeled by using a voltage source and two virtual impedances. The reference value of the voltage source is calculated by droop control method [14]. In particular, the reference values of the voltage frequency and amplitude are generated as follows:
*i oif f mP= − (1)
*i oiE E nQ= − (2)
where fi and Ei are the voltage frequency and amplitude, f* and E* are their reference values, m and n are the droop coefficients, and Poi and Qoi are the output active and reactive power, i = 1, 2, …, n.
Note that the frequency and amplitude deviation of the local output voltage should be limited within the acceptable range, namely
*i maxf f f− ≤ Δ (3)
*i maxE E E− ≤ Δ (4)
where Δfmax and ΔEmax are the maximum acceptable deviation of the frequency and amplitude.
#1
#n
... ......
Line Impedance #1
Line Impedance #n
VI-FCL #n
PCCVI-FCL #1
Zv1
Zvn
Line Impedance #2
VI-FCL #2
Zv2 #2
...
VI-FCL:
Activated during Faults
Terminal #1
Load
Zfcl1
Zfcln
Zfcl2
Simplified Impedance Model
DG #1
ft span
thfcli ( )/
fcli thmax
0
[1 ] t t t
I IZ
Z e I I− −
<= − ≥
Fig. 2. Configuration of AC microgrids dominated by multiple interface inverters.
The two virtual impedances in the equivalent model of the inverter interfaced DG unit are represented by Zvi and Zfcli, respectively. Here, Zvi is used to decouple the active and reactive power sharing and ensure the droop relationship shown in (1) and (2) [29], [30], and Zfcli is involved to represent the VI-FCL, which is activated only during faults and keeps zero in normal operation. The amplitude of Zfcli is calculated as:
ft span
thfcli ( )/
fcli thmax
0
[1 ] t t t
I IZ
Z e I I− −
<= − ≥
(5)
where |Zfcli|max is the maximum amplitude of the virtual impedance that is determined by considering the acceptable fault current level, tft is the time when the measured peak current exceeds the threshold, tspan is the transient time for the amplitude of the virtual impedance changing from 0 to the maximum value, I is the peak value of the current, and Ith is the current threshold of triggering the FCLs.
Based on the above definition, the overall control diagram is shown in Fig. 3, and the flow chart of the working principle of VI-FCL is shown in Fig. 4. In the control diagram in Fig. 3, proportional-resonant (PR) controllers are used in the inner voltage and current control loops [30], which can be shown as:
rvv pv 2 2
k sG ks ω
⋅= ++
(6)
rcc pc 2 2
k sG ks ω
⋅= ++
(7)
where Gv and Gc are the transfer functions of the inner voltage and current controllers, kpv and krv are the coefficients of the proportional and resonant terms in Gv, kpc and krc are the coefficients of the proportional and resonant terms in Gc, ω is the angular frequency, s is the Laplace operator.
Meanwhile, it should be noted that secondary control is employed to eliminate the deviations of frequency and amplitude in normal operation. By using secondary frequency and voltage amplitude control, two compensation terms related to the phase angle Φ and voltage amplitude E, i.e., δΦ and δE, are generated and added to the voltage reference. The fault is detected when the peak value of output current reaches its threshold, and the secondary control is deactivated while the VI-FCL is activated. Then, the amplitude of Zfcl reaches its maximum value to alleviate the amount of fault current. When the peak value of output current falls below its threshold, the VI-FCL is deactivated to avoid unnecessary voltage drop, and the secondary control is reactivated to restore the voltage frequency and amplitude. Here, deactivating secondary control refers to resetting the proportional-integral (PI) controllers in the secondary control level and stop adding the compensation terms, i.e., δΦ and δE, into the voltage reference.
It can be seen that the VI-FCL, i.e., Zfcli, is only activated during fault conditions. However, as aforementioned, when the fault occurs, secondary control should be deactivated. The reason for deactivating secondary control during faults is that the voltage is forced to drop down due to the existence of fault impedance and this voltage drop is inevitable. Since secondary control is used to restore the voltage, it conflicts with voltage drop induced by the faults. Hence, it should be deactivated to avoid the instable operation of the control diagram.
Power Calculation
vo
io
Low-Pass Filter
Po
Qo
-
-
f*
+
+E*
1/sΦ
E
Voltage Ref.
Generator
voref +
io abc iαβZfcl
vfcl
-
PI+f*
-f
δΦ1/s
PWM Generatorn
m
+
++
io abc iαβZv
vv
-
DG#1
Terminal #1
PCC
Terminal #n
...... ...
Load
Terminal #2Line
Impedance #2
LineImpedance #1
LineImpedance #n
PI+E*
-E
δE
δE
δΦ
vo+-
io
αβ
αβ
-vo
PRiLref +
-iL
PR
Voltage Controller
Current Controller
iL
Fig. 3. Overall control diagram including the additional control loop of VI-FCL.
I ≥ IthNormal
OperationNo
Yes
Yes
No
|Zfcli| = |Zfcli|max[1 – e-(t - tth)/tspan]
|Zfcli| = 0
Deactivate Secondary Control
Activate Secondary Control
I < Ith
Fig. 4. Flow chart of the working principle of VI-FCL.
B. Design and Implementation of VI-FCL In order to properly design the VI-FCL, as shown in Fig. 5,
the representative system is employed, where the Żl, Żv, Żfcl and Żg represent the vectors of line impedance, virtual impedance Zv, VI-FCL Zfcl and the ground impedance at the fault location, respectively, and Żfcl is only activated during faults. The impedances Żl, Żv and Żfcl can be written as:
l l l
v v v
fcl fcl fcl
Z Z
Z Z
Z Z
θ
θ
θ
= ∠ = ∠
= ∠
(8)
where θl, θv and θfcl are the phase angles of the corresponding impedances.
In order to simplify the analysis and avoid the potential instability issue, Żfcl is selected to be in phase with Żv. Therefore, it is achieved that:
fcl v
fcl vZ k Z
θ θ= =
(9)
where k represents the ratio between |Żfcl| and |Żv|. As shown in [29]-[30], the virtual impedance Zv is used to
ensure that the active and reactive power sharing follows the
droop control expression shown in (1) and (2) in normal condition. In order to meet this requirement, Zv should be significantly inductive. To quantitatively identify the required |Żv| and θv, the phasor diagram of the impedances as shown in Fig. 6 are employed. It is defined that:
eq l vZ Z Z= + (10) Hence, in order to guarantee that the equivalent line
impedance Żeq in normal condition is significantly inductive, the phase angle of Żeq, i.e., θeq, should be almost 90°. Namely,
eq eqm90 θ θ− ≤ (11) where θeqm is the maximum acceptable phase difference, which is selected as 2° here.
By using the cosine law in the triangle ΔOBC, it is derived that:
2 2
eq v l v l v l2 cos(90 )Z Z Z Z Z θ θ= + − − + (12)
Meanwhile, by using the sine law in the same triangle, it yields that:
vv l
eq
arcsin[ sin( )]Z
Zα θ θ= −
(13)
where α = ∠COB. Hence, it can be derived that:
eq lθ α θ= + (14) For a given system, |Żl| and θl are commonly vary within a
certain range that is determined by the practical condition of the DG branch. The selection of |Żv| and θv should make sure that for arbitrary |Żl| and θl within their ranges, the equivalent line impedance Żeq should be significantly inductive, i.e., the criteria established by combining (11) – (14) should be satisfied. In the given system, assuming that |Żl| varies within the range of 0.5 ~ 1 Ω and θl varies within the range of 80° ~ 87.5°, by using MATLAB m-script to search the suitable |Żv| and θv, it can be reached that:
v
v
1.40
89
Z
θ
= Ω
=
(15)
Note that some more choices of |Żv| that is larger than 1.40 Ω can be selected to meet the criteria established by (11) – (14). Since larger |Żv| reduces the output voltage in normal condition, the smallest |Żv| that fulfills the criteria is selected
here in (15). After designing |Żv| and θv, as mentioned in (9), it is
achieved that: fcl v 89θ θ= = (16)
Therefore, the next step for the design procedure is to select the suitable k so that the vector Żfcl can be determined.
As shown in the representative system in Fig. 5, in case of a fault occurring at the DG branch, a parameter λ is employed to indicate the fault location. It is defined as:
la
la lb
ZZ Z
λ =+
(17)
where Żla is the part of the line impedance near the DG unit, while Żlb is the part of the line impedance near the PCC, and Żla + Żlb = Żl. The smaller λ indicates that the fault is near the DG terminal, while the larger λ indicates the fault is near the PCC.
The variable k should be determined by limiting the maximum |Io| lower than |Io|max. As shown in Fig. 5, when the fault occurs, the voltage at the fault location can be regarded as almost zero. Hence, it can be calculated that:
refo o max
l1 l v v v v
VI IZ Z k Zθ θ θ
= ≤∠ + ∠ + ∠
(18)
Assuming that the phase angle of Vref is zero and |Vref| = 110 V, (18) should be satisfied with arbitrary line impedances and fault locations. In other words, for the given system, (18) should be fulfilled with arbitrary |Żl| within the range of 0.5 ~ 1 Ω, arbitrary θl within the range of 80° ~ 87.5°, and arbitrary λ within the range of 0 ~ 1.
Similar to the design procedure of |Żv| and θv, the suitable value of the variable k can be searched by using MATLAB m-script. Here, it is obtained that k equals 4.
Note that larger k can be also selected to meet the requirement in (18). In order to avoid the unnecessary voltage deviation during faults, the minimum k that satisfies (18) is selected here.
Hence, by summarizing the above results, it yields: fcl fcl fcl v v 4 1.4 89 5.6 89Z Z k Zθ θ= ∠ = ∠ = × ∠ = ∠ (19)
It should be noticed that for multiple inverters in an AC microgrid, the VI-FCL for each interface inverter should be designed individually based on the practical line impedance Żl and the virtual impedance Żv.
ŻlaŻfclŻv+
-
+
-
+
-
Vref Vo Vpcc
İo
Żlb
Żg
Vfault ≈ 0
Fig. 5. Representative system for the design of VI-FCL.
O
A
B
C
Żl
Żv
Żeq
α
θlθv
Fig. 6. Phasor diagram of the impedances Żl and Żv.
III. MODELING AND ANALYSIS OF AC MICROGRIDS WITH VI-FCLS
A. Modeling of AC Microgrids with VI-FCLs during Faults In order to analyze the effectiveness of VI-FCLs, the model
of AC microgrids during faults is analyzed as follows. Take an AC microgrid with three DGs as an example. The impedance model of AC microgrids during faults is shown in Fig. 7, where Zload is the load impedance and Zg is the ground impedance of the fault. It is assumed that the fault occurs at the branch of DG #1.
For each DG interface inverter, the configuration of the main power circuit and the corresponding control diagram are shown in Fig. 8 (a) and (b). It can be derived based on the control diagram in Fig. 8 (b) that:
vi ci d capioi refi
ci d indi vi ci d capi
vi ci d capi vi fcli ci d indi capioi
ci d indi vi ci d capi
(1 )( ) ( )
(1 )
G G G Gv v
G G G G G G GG G G G Z Z G G G G
iG G G G G G G
= ⋅+ + +
+ + +− ⋅
+ + +
(20)
where Gvi and Gci are the inner voltage and current controllers, respectively, Gd represents the PWM generation unit, Gcapi is the transfer function of the inverter filter capacitor, Gindi is the transfer function of the inverter filter inductor, voi and ioi are the output voltage and current of inverter #i, and vrefi is the reference value of voi (i = 1, 2, 3).
Zl1a Zl1b
Zg
Zv1
+
-
Zl2 Zv2
+
-
DG #1
Zl3Zv3
+
-
Zload
PCC
+
-vo3
+
-vo1
io1
io3
io2+
-vo2
Zfcl1
Zfcl3
Zfcl2
DG #3
DG #2
Fig. 7. Impedance model of the AC microgrid with VI-FCLs during faults.
vo
+
-
ioL
Cvinv
+
-
iL
(a)
Gv Gc
Zv + Zfcl
Gd 1/Gind Gcapvoref +
-
vo
io
-iLref
vo
+
-iL
vinv +-
iL+-
vo
(b)
Fig. 8. Detailed configuration of each DG interface inverter. (a) Main power circuit configuration. (b) Control diagram of each DG interface inverter.
It should be noted that first-order approximation, as shown in the transfer function Gd, is used here to represent the procedure of PWM generation [33]. Meanwhile, Gvi and Gci are the common PR voltage and current controllers, respectively. The transfer functions of Gvi, Gci, Gd, Gcapi and Gindi are shown below:
rvi rcivi pvi ci pci2 2 2 2
d capi indi id i
,
1 1, ,1
k s k sG k G ks s
G G G sLT s sC
ω ω⋅ ⋅= + = +
+ +
= = =+ ⋅
(21)
where kpv and krv are the proportional and resonant coefficients of the voltage PR controller, kpci and krci are the proportional and resonant coefficients of the current PR controller, Td is the delay induced by PWM generation and duty cycle updating, Ci is the inverter filter capacitance, and Li is the inverter filter inductance.
For simplification, (20) can be rewritten as: oi refi refi oi oi (i=1, 2, 3)v G v Z i= ⋅ − ⋅ (22)
where vi ci d capi
refici d indi vi ci d capi
vi ci d capi vi fcli ci d indi capioi
ci d indi vi ci d capi
(1 )( ) ( )
(1 )
G G G GG
G G G G G G GG G G G Z Z G G G G
ZG G G G G G G
=+ + +
+ + +=
+ + +
The system model can be derived by using superposition theorem based on the impedance network in Fig. 7, namely each output current or voltage can be calculated by considering the sum of that variable in each case with single source. Take the output current of DG #1 as an example. It is obtained that:
o1o11
load l2 l3 l1 g l1[ / / / / (1 ) ] / /vi
Z Z Z Z Z Zλ λ=
+ − + (23)
o2o12
l1 g l1 load l3 l2
gload l3
l1 g l1 load l3 l1 g
[( ) / / (1 ) ] / / / // /
( ) / / (1 ) / /
viZ Z Z Z Z Z
ZZ ZZ Z Z Z Z Z Z
λ λ
λ λ λ
= −+ − +
⋅ ⋅+ − + +
(24)
o3o13
l1 g l1 load l2 l3
gload l2
l1 g l1 load l2 l1 g
[( ) / / (1 ) ] / / / // /
( ) / / (1 ) / /
viZ Z Z Z Z Z
ZZ ZZ Z Z Z Z Z Z
λ λ
λ λ λ
= −+ − +
⋅ ⋅+ − + +
(25)
where io11, io12 and io13 are the output current of DG #1 in each decomposition system, and vo1, vo2 and vo3 are the corresponding output voltage of each DG unit.
Hence, it yields: o1 o11 o12 o13
11 o1 12 o2 13 o3
i i i iY v Y v Y v
= + += ⋅ + ⋅ + ⋅
(26)
where Y11, Y12 and Y13 are the coefficients in (23) – (25). By using the same procedure, the output current of each DG
branch can be reached, which can be summarized as: o1 o1
o2 o2
o3 o3
i vi Y vi v
= ⋅
(27)
where Y is the coefficient matrix with elements Yij (i, j = 1, 2, 3).
Combining (22) (i = 1, 2, 3) and (27), it is achieved that: o1 ref1
1o2 o ref ref2
o3 ref3
(1 )v vv Z Y G vv v
− = + ⋅
(28)
where o1 ref1
o refo2 ref2
o3 ref3
, Z G
Z Z G GZ G
= =
Hence, the stability of the system with VI-FCLs can be studied by analyzing the dominant poles of the transfer functions voi/vrefi (i = 1, 2, 3) in (28). B. Stability Analysis of VI-FCLs
For the given system in Table I [34], by defining that Zv = Rv + s·Lv, Zfcl = Rfcl + s·Lfcl, Zload = Rload + s·Lload, Zg = Rg + s·Lg, and using bilinear transformation of s = 2/Td·(1 – z-1)/(1 + z-1), where Td is the unit delay induced by PWM generation, the stability analysis during faults is conducted by assessing the locations of dominant poles in z domain [35]–[40]. It should be noticed that the transient rising time tspan of VI-FCL in (5) is much smaller than the fault duration. Hence, only the steady state value of Zfcl during fault needs to be considered here.
When increasing the virtual inductance Lfcl from 50 nH to 80 mH and having Rfcl as 97.6 mΩ, it can be seen in Fig. 9 (a) that the dominant pole of system moves towards the unstable region. When the dominant pole locates near the stability boundary (the unit circles in Fig. 9 (a)), e.g., pL1 = -0.92 + j0, the system stability is challenged to be at risk. It should be noted that the poles locating on the right side of the figure are not the dominant poles since they are cancelled by the zeros. Similar situations exist for the z domain stability analysis in Fig. 9 (b) and (c). When increasing the virtual resistance Rfcl from 5 mΩ to 1 Ω and keeping Lfcl as 14.8 mH, it can be seen that three dominant poles move towards the stability boundary. As shown in Fig. 9 (b), the dominant poles are finally shown as pR1 = -0.69 + j0 and pR2,3 = -0.60 ± j0.50. It should be noticed that the impact of pR1 and pR2,3 are less significant compared to the case with increasing virtual inductance Lfcl since their magnitudes are smaller than the dominant pole pL1 in Fig. 9 (a). Meanwhile, as aforementioned, a parameter λ is involved to indicate the fault location. When changing λ and keeping Lfcl = 14.8 mH and Rfcl = 97.6 mΩ, all the dominant poles statically locate in the stable region without a trend to orient the unstable boundary. Hence, the proposed VI-FCL method is valid for different fault locations.
TABLE I SYSTEM PARAMETERS
Symbol Parameter Value f* Rated voltage frequency 60 Hz E* Rated RMS voltage 110 V Ll1 Line inductance #1 2.5 mH Rl1 Line resistance #1 0.08 Ω Ll2 Line inductance #2 1.8 mH Rl2 Line resistance #2 0.03 Ω Ll3 Line inductance #3 1.8 mH Rl3 Line resistance #3 0.03 Ω
Lload Load inductor 20 mH Rload Load resistor 0.4 Ω Lg Grounding inductance 0.03 mH Rg Grounding resistance 0.6 mΩ L Filter inductance of the inverter 1 mH C Filter capacitance of the inverter 47 μF kpv Proportional coefficient of the
voltage PR controller 0.6 -
krv Resonant coefficient of the voltage PR controller
2 -
kpc Proportional coefficient of the current PR controller
1 -
krc Resonant coefficient of the current PR controller
2 -
M Droop coefficient for voltage frequency
0.0006 rad/(W·s)
n Droop coefficient for voltage amplitude
0.02 V/Var
kpfs Proportional term of secondary frequency control
3×10-4 -
kifs Integral term of secondary frequency control
1.4 -
kpes Proportional term of secondary voltage amplitude control
2×10-3 -
kies Integral term of secondary voltage amplitude control
4 -
fs Switching frequency 10 kHz Td PWM delay 100 μs
Real Part
Imag
Par
t
-0.92 + j0
Unstable Region
(a)
Real Part
Imag
Par
t
Unstable Region
-0.69 + j0
-0.60 + j0.50
-0.60 - j0.50
(b)
Real PartIm
ag P
art
Unstable Region
-0.40 + j0
(c)
Fig. 9. Locations of the dominant poles in z domain. (a) 50 nH ≤ Lfcl ≤ 80 mH, Rfcl = 97.6 mΩ. (b) 5 mΩ ≤ Rfcl ≤ 1 Ω, Lfcl = 14.8 mH. (c) 0.05 ≤ λ ≤ 0.95, Lfcl = 14.8 mH and Rfcl = 97.6 mΩ.
IV. SIMULATION VALIDATIONS In order to verify the proposed control diagram with VI-
FCLs, a MATLAB/Simulink model comprised of three DGs is implemented. The system configuration is shown in Fig. 10 and the fault locations in different test cases are highlighted by using the circled numbers. Meanwhile, real-time HIL test is also conducted based on OPAL-RT platform. The system parameters are the same as those shown and Table I. It should be noted that the proposed method can be also used in practical applications. For practical implementation, the VI-FCL should be designed based on the real condition of power cable, acceptable fault current level, desired transient time for fault clearance, etc. Due to the present hardware limitations, only offline and real-time simulations are shown below for case studies. Case I: Different Values of VI-FCLs
Different values of VI-FCLs are tested to study their impacts on fault current limiting and transient oscillation mitigation. As shown in Fig. 10, taking the fault at the PCC as an example, it occurs at t = 36 s and lasts for 0.2 s. The comparative study of different VI-FCLs is investigated in this test case. In the illustrative system, as shown in Table I, the length of the power cable for DG #2 and #3 is the same, while the length of the cable for DG #1 is longer. The waveforms of the RMS current for DG #1 and #2 and the system frequency are selected as examples.
PCCDG#1
DG#2
Zload
②③
④⑤
⑦Terminal #1
DG#3
Terminal #3
Terminal #2
①
Line #3
Line #1 Line #2
⑥ ⑧
Fig. 10. System configuration and fault locations for different test cases.
Four parameters are defined to evaluate the effect of fault current limiting, i.e., ΔIm, Δfm, Δtsi and Δtsf. Here, ΔIm and Δfm represent the maximum deviation of the RMS current and frequency compared to their normal values, and Δtsi and Δtsf represent the response time during which the current and frequency return to their normal values.
It can be seen from Fig. 11 that the VI-FCLs are activated during faults. Different curves in Fig. 11 represent the results with different VI-FCLs. In particular, as shown in the results and legends in Fig. 11 (a), when the amplitude of the VI-FCL, namely |Zfcl|, is selected as 0, 1.5 Ω and 9.2 Ω, respectively, ΔIm is measured as 5.36 A, 4.01 A and 1.16 A. Meanwhile, for the waveforms of frequency shown in Fig. 11 (b), when |Zfcl| is selected as 0, 1.5 Ω and 9.2 Ω, Δfm is shown as 0.33 Hz, 0.25 Hz and 0.21 Hz. Therefore, it is demonstrated that the VI-FCLs can be used to alleviate the fault current and mitigate the transient oscillations. Meanwhile, with larger |Zfcl|, the transient over-shoot fault current is smaller.
Since the fault current is limited, the system can restore to the normal status in shorter adjustment time. As shown in the current waveform, when |Zfcl| changes, Δtsi is reduced, as shown as 10.4 s, 9 s and 6.1 s, respectively. In the meantime, as shown in the frequency waveform, Δtsf is reduced as shown as 6.5 s, 5 s and 1.4 s.
As indicated in (5), a transient time tspan is involved to flexibly adjust the rising time of |Zfcl|. Here, tspan is selected as 5 ms, as shown in Fig. 11 (c). Case II: Fault Occurs at the DG Branch
As shown in Fig. 10, in this test case, the fault occurring at the branch of DG #1 is selected as an example. Both the faults near the DG unit and PCC are taken into account. As the same as Case I, the fault occurs at t = 36 s and lasts for 0.2 s. It should be noticed that the impact of the fault changes with different fault locations.
For the case with the fault near the DG unit, i.e., λ = 0.15, the waveforms of the RMS current of DG #1 and #2 are shown in Fig. 12 (a) and (b), respectively. It can be seen that although the fault occurs at the branch of DG #1, each DG unit contributes to the fault current. Meanwhile, the DG unit near the fault location delivers larger fault current. When activating the VI-FCL in each DG unit, the fault current and the transient oscillation can be significantly mitigated. In particular, for the RMS current of DG #1, ΔIm is reduced from 43.2 A to 15.4 A and Δtsi is reduced from 17.7 s to 4.6 s. For the RMS current of DG #2, ΔIm is reduced from 7.1 A to 1.65 A and Δtsi is reduced from 12.6 s to 3.8 s. The improvement of transient performance can be also clearly seen in the waveforms of the system frequency. As shown in Fig. 12 (c), large oscillations can be found in the frequency waveform when the VI-FCLs
are not employed. When activating the VI-FCLs, large oscillations are removed. Meanwhile, Δfm is reduced from 1 Hz to 0.29 Hz and Δtsf is reduced from 13.6 s to 0.9 s.
For the case with the fault near the PCC, i.e., λ = 0.85, the waveforms of RMS current of DG #1 and #2 are shown in Fig. 13 (a) and (b), respectively. It can be seen that for the RMS current of DG #1, ΔIm is reduced from 7.95 A to 2.96 A and Δtsi is reduced from 11.0 s to 3.4 s. For the RMS current of DG #2, ΔIm is reduced from 5.82 A to 3.02 A and Δtsi is reduced from 5.2 s to 3.6 s. For the frequency waveform, as shown in Fig. 13 (c), Δfm is reduced from 0.38 Hz to 0.22 Hz and Δtsf is reduced from 6.4 s to 1.2 s.
Meanwhile, compared to the results of the case with the fault near the DG unit shown in Fig. 12 (a) – (c), it can be found that the proposed VI-FCLs can be used to suppress the fault current and transient oscillations in various cases with different fault locations. Case III: Fault Occurs at the PCC
As shown in Fig. 10, the fault occurs at the PCC is studied. The effectiveness of VI-FCL during fault and in the post-fault procedure is discussed in detail in this test case. As same as Case I and II, the fault occurs at t = 36 s and lasts for 0.2 s. As shown in Fig. 14 (a), for DG branch #1, ΔIm changes from 5.36 A to 1.16 A if activating the VI-FCLs, and Δtsi is reduced from 10.4 s to 6.1 s. Meanwhile, for DG branch #2, as shown in Fig. 14 (b), ΔIm changes from 11.7 A to 4 A, and Δtsi reduces from 5.3 s to 4 s with VI-FCLs. It should be noted that the differences in the current and frequency waveforms for DG branch #1 and #2 are caused by different lengths of the power cables. For the frequency waveforms, as shown in Fig. 14 (c), large oscillations can be found without VI-FCLs. If activating the VI-FCLs, Δfm is reduced from 0.33 Hz to 0.21 Hz, and the transient time Δtsf is reduced from 6.5 s to 1.4 s. Case IV: Multiple Fault Locations
As shown in Fig. 10, the system responses when multiple faults occur at different locations are shown in this case study. It is set that the faults occur at DG branch #1 and DG branch #2 simultaneously at t = 36 s and lasts for 0.2 s. In order to diversify the fault locations, the fault at DG branch #1 occurs near the DG unit, while the fault at DG branch #2 occurs near the PCC. As shown in Fig. 15 (a), for DG branch #1, ΔIm changes from 30.9 A to 9.3 A with VI-FCLs activated, and Δtsi is reduced from 15.6 s to 4.7 s. Meanwhile, for DG branch #2, as shown in Fig. 15 (b), ΔIm is reduced from 25.3 A to 7.1 A, and Δtsi reduces from 10.6 s to 3.8 s with VI-FCLs. For the system frequency, as shown in Fig. 15 (c), when activating the VI-FCLs, Δfm is reduced from 0.94 Hz to 0.53 Hz, and the transient time Δtsf is reduced from 13.8 s to 3.6 s. Case V: Continuously Variable Load
The feasibility of the proposed method with continuously variable load is tested in this case study. In particular, the conventional impedance load is replaced by the variable load. The load current continuously changes during the whole simulation procedure, as shown in the current profile of the common load in normal condition in Fig. 16 (a). Meanwhile, as shown in Fig. 10, it is set that the fault at the DG branch #1 near the DG unit occurs at t = 36 s and lasts for 0.2 s. As
shown in Fig. 16 (b) – (d), when the fault occurs, compared to the value in normal condition, the maximum deviation of Irms1 is 52.5 A without VI-FCL, which is reduced to 16.4 A when the VI-FCL is activated. For DG branch #2, also compared to the value in normal condition, the maximum deviation of Irms2 is reduced from 15.6 A to 4.6 A with VI-FCL activated during the fault. At the same time, the maximum deviation of system frequency is reduced from 2.7 Hz to 2.0 Hz. It should be noted that since the load is continuously changed, the transient response time, i.e., Δtsi and Δtsf, is not calculated. It can be also seen from Fig. 16 (d) that when VI-FCL is employed, the post-fault procedure is significantly improved with much lower oscillations. Case VI: Rotating Machine Load
It should be pointed out that the proposed VI-FCL works with not only impedance load but also the other types of load. In this case study, a rotating machine load is employed as an example to test the feasibility of the proposed method in suppressing the amount of fault current. In particular, a three-phase asynchronous machine is used as the common load. The rated voltage and frequency are 110 V (rms) and 60 Hz, respectively. As shown in Fig. 10, it is set that the fault occurs at DG branch #1 near the DG unit at t = 36 s and lasts for 0.2 s.
It can be seen from Fig. 17 (a) that the maximum deviation of the torque ΔTm is reduced from 15.6 Nm to 4.6 Nm when activating VI-FCL. Meanwhile, the transient time ΔtsT w/o VI-FCL is similar, which is approximately 0.6 s. For the rotor speed, as shown in Fig. 17 (b), its maximum deviation Δωm is reduced from 9.6 rad/s to 2.6 rad/s when activating VI-FCL, and the transient time Δtsω is reduced from 3.6 s to 1.7 s. Hence, it can be seen that the proposed method works for rotating machine load. Case VII: Comparison with Conventional Current/Voltage Based Protection Schemes
Conventional protection schemes can be generally implemented by detecting the abnormal current or voltage. In order to identify the merits of the proposed VI-FCL based method, traditional current/voltage based protection schemes are implemented in this case study for comparison.
As shown in Fig. 10, it is set that the fault occurs at DG branch #1 near the DG unit at t = 36 s and lasts for 0.2 s. The responses with the conventional protection scheme based on current detection is shown in Fig. 18 (a) – (c). It can be seen that when Irms1 reaches its over-current threshold, the protective relay is activated to cut off the fault. Hence, Irms1 reduces to zero. Since the fault at DG branch #1 is isolated, the system returns to normal operation. Considering that DG branch #1 is cut off, the load is fed by DG branch #2 and #3. Therefore, Irms2 increases to 7.3 A. For the system frequency, it drops down to 59.84 Hz during the transient process and it gradually returns the rated value 60 Hz after the fault is isolated.
By setting the same fault condition, the responses with the conventional protection scheme based on voltage detection is shown in Fig. 19 (a) – (c). It can be seen that when Vrms1 reduces to its low-voltage threshold, the protective relay is
activated to cut off the fault and the interface inverter for DG #1 stops working. Hence, Vrms1 reduces to zero. Meanwhile, since the fault is isolated, the system returns to normal operation. In particular, Vrms2 reaches 149.5 V after the transient deviation induced by the fault, and the frequency is gradually returned from 59.84 Hz to the rated value 60 Hz.
It should be noted that although the conventional current/voltage based protection schemes can effectively isolate the fault and make the system return to normal operation. It must be noticed that the DG branch with fault is cut off. Even though it can be reconnected when the fault is cleared, unavoidable resynchronization algorithm should be implemented during reconnection. This resynchronization may involve some additional stability and power quality issues. The proposed VI-FCL based fault ride through method is implemented without interrupting the connectivity of DG units. Hence, no complicated resynchronization is needed. Case VIII: Real-Time Hardware-in-the-Loop Simulation Test
In order to further verify the feasibility of the proposed VI-FCL, real-time HIL test is conducted. In particular, a real-time simulation environment is implemented based on OPAL-RT platform, which can be regarded as a semi-hardware platform where the AC microgrids with DG interface inverters and line impedances are modeled in the real-time environment in OPAL-RT while real hardware controllers are used to test the proposed method. Meanwhile, the whole test procedure is done in real-time. The system configuration of the real-time HIL test platform is shown in Fig. 20.
Compared to the conventional off-line simulation test based on MATLAB/Simulink, the real-time HIL demonstration based on OPAL-RT features the enhanced test capability. Hence, the longer time test case can be verified. As shown in Fig. 10, during the whole test procedure, at t = 40 s, 80 s and 120 s, the fault occurs at different locations, and each fault lasts for 0.2 s. At t = 40 s, the fault near PCC occurs at DG branch #1, and at t = 80 s, the fault near DG unit occurs at DG branch #2. Finally, at t = 120 s, multiple faults occur simultaneously at DG branch #1 near PCC and DG branch #2 near DG unit. It can be seen from Fig. 21 (a) – (c) that with the proposed VI-FCLs, the fault current at different fault locations can be effectively suppressed. Meanwhile, the oscillation in the post-fault procedure can be significantly improved.
Time (s)
I rm
s1 (A
)
Δtsi = 10.4 s
Δtsi = 9 s
Δtsi = 6.1 sΔIm = 1.16 A
ΔIm = 4.01 A
ΔIm = 5.36 A
|Zfcl| = 1.5 Ω|Zfcl| = 0
|Zfcl| = 9.2 Ω
(a)
Time (s)
Freq
(Hz)
Δtsf = 6.5 s
Δtsf = 5 sΔtsf = 1.4 s
Δfm = 0.33 Hz
Δfm = 0.25 Hz
Δfm = 0.21 Hz
|Zfcl| = 1.5 Ω|Zfcl| = 0
|Zfcl| = 9.2 Ω
(b)
|Zv|
(Ω )
Time (s)
tspan = 5 ms
|Zfcl| = 1.5 Ω|Zfcl| = 0
|Zfcl| = 9.2 Ω
(c)
Fig. 11. Fault responses with different VI-FCLs. (a) RMS current waveform with different VI-FCLs. (b) Frequency waveform with different VI-FCLs. (c) Amplitude of virtual impedance.
I rm
s1 (A
)
Δtsi = 4.6 s
Δtsi = 17.7 s
ΔIm = 15.4 A
ΔIm = 43.2 A
Time (s)
Without VI-FCLWith VI-FCL
(a)
I rm
s2 (A
)
Time (s)
Δtsi = 12.6 s
Δtsi = 3.8 s
ΔIm = 7.1 A
ΔIm = 1.65 A
Without VI-FCLWith VI-FCL
(b)
Freq
(Hz)
Time (s)
Δtsf = 13.6 s
Δfm = 1 Hz
Δtsf = 0.9 s
Δfm = 0.29 Hz
Without VI-FCLWith VI-FCL
(c)
Fig. 12. Reponses with the fault occurring at the DG branch (near DG unit). (a) RMS current waveform of DG #1. (b) RMS current waveform of DG #2. (c) Frequency waveform.
Time (s)
I rm
s1 (A
)
Δtsi = 11.0 s
ΔIm = 2.96 A
ΔIm = 7.95 A
Δtsi = 3.4 s
Without VI-FCLWith VI-FCL
(a)
I rm
s2 (A
)
Time (s)
Δtsi = 5.2 s
Δtsi = 3.6 sΔIm = 5.82 A
ΔIm = 3.02 A
Without VI-FCLWith VI-FCL
(b)
Freq
(Hz)
Time (s)
Δtsf = 1.2 s
Δtsf = 6.4 s
Δfm = 0.38 Hz
Δfm = 0.22 Hz
Without VI-FCLWith VI-FCL
(c)
Fig. 13. Reponses with the fault occurring at the DG branch (near PCC). (a) RMS current waveform of DG branch #1. (b) RMS current waveform of DG branch #2. (c) Frequency waveform.
Time (s)
I rm
s1 (A
)
ΔIm = 1.16 A
Δtsi = 6.1 s
Δtsi = 10.4 s
ΔIm = 5.36 A Without VI-FCLWith VI-FCL
(a)
I rm
s2 (A
)
Time (s)
Δtsi = 4 s
Δtsi = 5.3 s
ΔIm = 11.7 A
ΔIm = 4 A
Without VI-FCLWith VI-FCL
(b)
Freq
(Hz)
Time (s)
Δtsf = 1.4 s
Δtsf = 6.5 s
Δfm = 0.33 Hz
Δfm = 0.21 Hz
Without VI-FCLWith VI-FCL
(c)
Fig. 14. Reponses with the fault occurring at the PCC. (a) RMS current waveform of DG branch #1. (b) RMS current waveform of DG branch #2. (c) Frequency waveform.
Time (s)
I rm
s1 (A
)
ΔIm = 9.3 A
ΔIm = 30.9 A
Δtsi = 4.7 sΔtsi = 15.6 s
Without VI-FCLWith VI-FCL
(a)
Time (s)
I rm
s2 (A
)
ΔIm = 7.1 A
ΔIm = 25.3 A
Δtsi = 3.8 s
Δtsi = 10.6 s
(b)
Time (s)
Freq
(Hz)
Δtsf = 13.8 sΔfm = 0.94 Hz
Δtsf = 3.6 s
Δfm = 0.53 Hz
(c)
Fig. 15. Responses with the faults occurring in DG branch #1 and #2 simultaneously. (a) RMS current waveform of DG branch #1. (b) RMS current waveform of DG branch #2. (c) Frequency waveform.
Time (s)
Load
Cur
rent
Pro
file
(A)
(a)
Time (s)
I rm
s1 (A
) ΔIm = 52.5 A
ΔIm = 16.4 A
Without VI-FCLWith VI-FCL
(b)
Time (s)
I rm
s2 (A
)
ΔIm = 15.6 A
ΔIm = 4.6 A
Without VI-FCLWith VI-FCL
(c)
Time (s)
Freq
(Hz)
Δfm = 2.7 Hz
Δfm = 2.0 Hz
Without VI-FCLWith VI-FCL
(d)
Fig. 16. Responses with continuously variable load. (a) Current profile of the common load. (b) RMS current waveform of DG branch #1. (c) RMS current waveform of DG branch #2. (d) Frequency
waveform.
Time (s)
Torq
ue (N
m)
Without VI-FCLWith VI-FCL
ΔTm = 15.6 Nm
ΔTm = 4.6 NmΔtsT = 0.6 s
(a)
Time (s)
Rot
or S
peed
(rad
/s)
Δωm = 2.6 rad/s
Δωm = 9.6 rad/s
Δtsω = 3.6 s
Δtsω = 1.7 s
Without VI-FCLWith VI-FCL
(b)
Fig. 17. Responses with rotating machine load. (a) Torque waveform. (b) Rotor speed waveform.
Time (s)
I rm
s1 (A
)
40 A
0
(a)
Time (s)
I rm
s2 (A
) 7.3 A
(b)
Time (s)
Freq
(Hz)
59.84 Hz
(c)
Fig. 18. Responses of conventional current based protection scheme. (a) RMS current waveform of DG branch #1. (b) RMS current waveform of DG branch #2. (c) Frequency waveform.
Time (s)
Vrm
s1 (V
)
79 V
0
(a)
Time (s)
Vrm
s2 (V
) 149.5 V
(b)
Time (s)
Freq
(Hz)
59.84 Hz
(c)
Fig. 19. Responses of conventional voltage based protection scheme. (a) RMS voltage waveform of DG branch #1. (b) RMS voltage waveform of DG branch #2. (c) Frequency waveform.
Conv. #1 Conv. #2
...
Conv. #i
...
Conv. #n
Current #iVoltage #i
...
VI-FCL Control Signal
...Secondary Control Signal
Real-time Simulation Model in OPAL-RT
Controller Connected in the Loop
Fig. 20. Configuration of real-time HIL test platform.
Time (s)
I rm
s1 (A
)
Without VI-FCLWith VI-FCL
(a)
Time (s)
I rm
s2 (A
)
Without VI-FCLWith VI-FCL
(b)
Time (s)
Freq
(Hz)
Without VI-FCLWith VI-FCL
(c) Fig. 21. Responses of real-time HIL test. (a) RMS voltage waveform of DG branch #1. (b) RMS voltage waveform of DG branch #2. (c) Frequency waveform.
V. CONCLUSION In order to alleviate the impact of the large fault current in
inverter dominated AC microgrids, VI-FCLs are proposed to suppress the amount of current flowing through the system and mitigate the oscillation during faults and in the post-fault restoration process. The VI-FCLs are embedded in the control diagram of each DG inverters. Hence, it is a low-cost approach that is implemented without additional hardware devices. Furthermore, the impedance model of AC microgrids during faults is derived with the consideration of VI-FCLs, and the impact of the parameters of VI-FCLs on system stability is analyzed. Meanwhile, it is demonstrated that by using the proposed VI-FCLs, the large fault current can be reduced and the oscillations for different fault locations can be significantly eliminated.
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Xiaonan Lu (S’11-M’14) received the B.E. and Ph.D. degrees in electrical engineering from Tsinghua University, Beijing, China, in 2008 and 2013, respectively. From Sep. 2010 to Aug. 2011, he was a guest Ph.D. student at Department of Energy Technology, Aalborg University, Denmark. From Oct. 2013 to Dec. 2014, he was a postdoc researcher in the Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville. In Jan. 2015, he joined the Energy Systems Division, Argonne National Laboratory, where he is currently a postdoc
appointee. His research interests include modeling and control of power electronic
converters in renewable energy systems and microgrids, hardware-in-the-loop real-time simulation, distribution automation, etc. Dr. Lu received the Outstanding Reviewer Award for IEEE Transactions on Power Electronics in 2013 and the Outstanding Reviewer Award for IEEE Transactions on Smart Grid in 2015.
Dr. Lu is a member of IEEE PELS, IAS, PES and IES Society.
Jianhui Wang (M’07-SM’12) received the Ph.D. degree in electrical engineering from Illinois Institute of Technology, Chicago, IL, USA, in 2007.
Presently, he is the Section Lead for Advanced Power Grid Modeling at the Energy Systems Division at Argonne National Laboratory, Argonne, IL, USA.
Dr. Wang is the secretary of the IEEE Power & Energy Society (PES) Power System Operations Committee. He is an associate editor of Journal of Energy Engineering and an editorial board
member of Applied Energy. He is also an affiliate professor at Auburn University and an adjunct professor at University of Notre Dame. He has held visiting positions in Europe, Australia and Hong Kong including a VELUX Visiting Professorship at the Technical University of Denmark (DTU). Dr. Wang is the Editor-in-Chief of the IEEE Transactions on Smart Grid and an IEEE PES Distinguished Lecturer. He is also the recipient of the IEEE PES Power System Operation Committee Prize Paper Award in 2015.
Josep M. Guerrero (S’01-M’04-SM’08-FM’15) received the B.S. degree in telecommunications engineering, the M.S. degree in electronics engineering, and the Ph.D. degree in power electronics from the Technical University of Catalonia, Barcelona, in 1997, 2000 and 2003, respectively. Since 2011, he has been a Full Professor with the Department of Energy Technology, Aalborg University, Denmark, where he is responsible for the Microgrid Research Program. From 2012 he is a guest Professor at the Chinese Academy of Science and the Nanjing
University of Aeronautics and Astronautics; from 2014 he is chair Professor in Shandong University; from 2015 he is a distinguished guest Professor in Hunan University; and from 2016 he is a visiting professor fellow at Aston University, UK, and a guest Professor at the Nanjing University of Posts and Telecommunications.
His research interests is oriented to different microgrid aspects, including power electronics, distributed energy-storage systems, hierarchical and cooperative control, energy management systems, smart metering and the
internet of things for AC/DC microgrid clusters and islanded minigrids; recently specially focused on maritime microgrids for electrical ships, vessels, ferries and seaports. Prof. Guerrero is an Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, and the IEEE Industrial Electronics Magazine, and an Editor for the IEEE TRANSACTIONS on SMART GRID and IEEE TRANSACTIONS on ENERGY CONVERSION. He has been Guest Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS Special Issues: Power Electronics for Wind Energy Conversion and Power Electronics for Microgrids; the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Special Sections: Uninterruptible Power Supplies systems, Renewable Energy Systems, Distributed Generation and Microgrids, and Industrial Applications and Implementation Issues of the Kalman Filter; the IEEE TRANSACTIONS on SMART GRID Special Issues: Smart DC Distribution Systems and Power Quality in Smart Grids; the IEEE TRANSACTIONS on ENERGY CONVERSION Special Issue on Energy Conversion in Next-generation Electric Ships. He was the chair of the Renewable Energy Systems Technical Committee of the IEEE Industrial Electronics Society. He received the best paper award of the IEEE Transactions on Energy Conversion for the period 2014-2015, and the best paper award of IEEE-PES in 2015. In 2014 and 2015 he was awarded by Thomson Reuters as Highly Cited Researcher, and in 2015 he was elevated as IEEE Fellow for his contributions on “distributed power systems and microgrids.”
Dongbo Zhao (S’10–M’14–SM’16) received his B.S. degree from Tsinghua University, China in 2008, M.S. degree from Texas A&M University, College Station, Texas in 2010, and Ph.D degree from Georgia Institute of Technology, Atlanta, Georgia in 2015, all in electrical engineering. Since 2014 he is the Lead Engineer at Eaton Corporation in the corporate research and technology department. He has worked with ABB Inc. US Corporate Research Center located in Raleigh, NC from 2010 to 2011. His research
interests include power system control, protection, reliability analysis, transmission and distribution automation, and electric market optimization.