AbstractAbstractThe purpose of this project is to design a high-performance FPGA-controlled amplifier for Teradyne Corporation. This will constitute Phase IV of an ongoing project for Teradyne. It has to be a characterization of the 100 MHz high-gain, low-noise, and low-distortion amplifier with DC-offset correction and frequency response calibration. The rest of the task will include debugging, tweaking, testing and mid-course corrections from previous projects to meet the design performance goals.

Problem StatementProblem StatementGeneral problems that will be faced by team design:

• Evaluate and consider accurately the existing phase project. • DC-offset needs to be corrected.• Better ADC and DAC controller.• Higher distortion and higher noise.

Possible solutions to the problems:

• Team will meet every week with both advisors and client to discuss the existing phase project.• Double DC-offset are needed to control the amplifier more accurately.• Conduct research on ADC and DAC controller.• Perform the design simulation in order to make sure everything works perfectly.

Operating EnvironmentOperating Environment

Intended Users and UsesIntended Users and Uses• The Teradyne Corporation engineers - the intended users of this system. • Fully assembled spectrum analyzer will be used to test silicon chips.

Assumptions and LimitationsAssumptions and LimitationsThe design team assumes that:

• The end product will not be sale to other companies.• The frequency operation will be 100 MHz.• The board fabrication will take up to 6 weeks.• The design should be done in November.• Fabrication board will be available in January.

The design team’s limitations are:Table 1

Expected End Product & Expected End Product & DeliverablesDeliverables• Teradyne Integra J750 Enhanced Digital Channel Board will be used to test large number

of digital chips for other companies. • The amplifier produced by the team will serve as a pre-amplifier to the spectrum analyzer. • The amplifier will be able to amplify a signal of up to 100MHz. • The amplifier will meet noise, distortion, and DC offset voltage specifications.

Project RequirementsProject RequirementsDesign Objectives

Improve DC-Offset from the previous design that has not yet achieved the required specification.

Functional Requirement

• Wide input frequency range – The amplifier will be able to amplify signals from 0Hz to 100MHz.• Programmable gain settings – The amplifier will have programmable gain settings for the specified frequency range.• DC offset correction – The DC offset correction can be turned on and off.

Design Constraints

Parts constraint, bandwidth constraint, cost constraint need to be minimized.

Measurable Milestones

Testing Simulation Fabrication Understand previous project Research Results Better Design Technology consideration

Proposed Approach & Proposed Approach & ConsiderationsConsiderationsProposed Approach

• Evaluate the previous work done on the design and research is necessary.• Research will be on various textbooks, papers to improve the design.• Create a test plan which includes testing techniques and testing programs.• Research other companies’ websites such as Texas Instrument, Analog Devices and others. • Modifications on layout and PCB fabrication will be done using software provided by Teradyne.

Technologies Considered

• Teradyne Integra J750 Test System is used for testing.• The output signal is generated by connecting the input of the chip to Teradyne machine.

Testing considerations

End product is to be tested by a group of inexperienced students with Teradyne Integra J750.

Estimated Resources and Estimated Resources and ScheduleSchedule

Closing SummaryClosing SummaryThe demand for test equipment will grow as the integrated circuit industry grows. As companies attempt to produce larger volumes, new test equipment will be needed to match this volume. The digital spectrum analyzer will enable Teradyne Corporation to test and monitor integrated circuits quickly, efficiently, and accurately.

   InputInput          TotalTotal   

InputInput VoltageVoltage AvailableAvailable Max OutputMax Output Freq ResponseFreq Response Harmonic Harmonic   

FrequencyFrequency RangeRange Gain SettingsGain Settings VoltageVoltage Flatness Flatness DistortionDistortion NoiseNoise

RangeRange (Volts)(Volts) (dB)(dB) (Volts)(Volts) (dB)(dB) (dB)(dB) (nV/rtHz)(nV/rtHz)

             

DC – 1kHz +/- 5 volts 6, 20, 40, 60 +/- 10 volts 0.05 dB < - 105 dB 1.5 nV/rtHz

> 1kHz - 20 kHz +/- 5 volts 6, 20, 40, 60 +/- 10 volts 0.05 dB < - 95 dB 1.5 nV/rtHz

> 20kHz – 100kHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < -85 dB 2.5 nV/rtHz

> 100kHz - 1MHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < - 80 dB 3.5 nV/rtHz

> 1MHz - 10MHz +/- 2.5 volts 6, 20, 40 +/- 5 volts 0.10 dB < - 70 dB 3.5 nV/rtHz

> 10MHz – 20MHz +/- 2.5 volts 6, 20 +/- 5 volts 0.10 dB < -65 dB 3.5 nV/rtHz

> 20MHz – 50MHz +/- 1.0 volts 6, 20 +/- 2.0 volts 0.10 dB < -50 dB 5.0 nV/rtHz

> 50MHz – 100MHz +/- 1.0 volts 6, 20 +/- 2.0 volts 0.10 dB < -40 dB 5.0 nV/rtHz

The system will be used in a climate-controlled laboratory at room temperature with low humidity.

Group Email: Client Advisor Team Members Acknowledgement sdmay528@iastate.edu Steven Miller Dr. Chris Chu Ian Overton, CprE Dr. Gary Tuttle

Teradyne Corporation 331 Durham Center overtoni@iastate.edu 2132 Coover HallProject Homepage: 978-370-8319 Phone: 515-294-3490 Phone: 515-294-1814 http://seniord.ee.iastate.edu/0528/ steven.miller@teradyne.com Fax: 515-294-8432 Jimmy Tjoa, EE gtuttle@iastate.edu

cnchu@iastate.edu jtjoa@iastate.edu

Agus Leonardo, EE agustan@iastate.edu

Figure 3

Figure 4

Figure 2