ac load flow control in - denver, colorado · source hvdc interties, the static synchronous series...

AC LINK LOAD FLOW CONTROL IN

ELECTRIC POWER SYSTEMS

by

Fernando Mancilla−David

A Dissertation

submitted in partial fulfillment of the

requirements for the degree of

Doctor of Philosophy

(Electrical Engineering)

at the

UNIVERSITY OF WISCONSIN−MADISON

2007

i

Abstract

As congestion in AC power transmission systems increases due to technical

limitations, environmental pressures, economic necessities and developmental demands,

devices with the ability to control power flow with much greater ease than presently

possible would be highly desirable. Furthermore, devices that channel power flow in the

network to fulfill contractual obligations for purchase agreements between power

producers and consumers would facilitate improved operation of the power system in the

emerging deregulated scenario. Following this trend, several power electronic-based

devices capable of accomplishing these objectives have been developed, unified under

the rubric of Flexible AC Transmission Systems, FACTS.

This thesis proposes a new family of FACTS devices: the Π−controller, the

Ξ−controller and the Γ−controller. Based on the vector switching converter (VeSC), these

devices feature similar functional characteristics to the ones encountered in the voltage

source HVDC interties, the Static Synchronous Series Compensator (SSSC) and the Unified

Power Flow Controller (UPFC), respectively. The control function, however, is realized

by direct AC↔AC conversion without frequency change, adopting the strategy of pulse

width modulation (PWM).

A comprehensive analysis is performed, including operating principles,

equivalent circuits, design consideration and dynamic modeling and control. Computer

simulations of illustrative examples are executed to validate the approach.

For the series compensation case, this new technology is contrasted against the

state−of−the−art. A detailed comparative study between the Ξ−controller and the SSSC

shows that the use of VeSC−based power flow controllers could become an alternative for

the next generation of FACTS devices.

In order to fully prove the concept of VeSC−based power flow controllers, a

ii

laboratory prototype was built and tested. The Γ−controller was chosen for experimental

verification, as its topology is the most general of all three controllers.

Finally, a system point of view is studied, incorporating the Ξ−controller into an

Optimal Power Flow (OPF) program.

iii

Acknowledgments

I would like to express my sincere gratitude and thanks to my advisor Professor

Giri Venkataramanan for his guidance, counsel and encouragement at every stage of this

research. I also thank my former advisor Professor Fernando Alvarado who gave me the

opportunity to become a graduate student at the University of Wisconsin and guided my

studies towards my M.S. degree.

I acknowledge the Wisconsin Electric Machines and Power Electronics

Consortium (WEMPEC), the Electric Power Research Institute (EPRI), and the Electrical

and Computer Engineering Department at the University of Wisconsin for funding this

research.

I have been fortunate to work with the WEMPEC and power area professors,

students and support staff who provided an excellent working environment with all the

resources that made this research possible.

I also thank Professor Subhashish Bhattacharya from North Carolina State

University for his contributions to Chapter 6 of this thesis.

I acknowledge the cooperation and support of Patrick Flannery who helped me

implement my experiments at the WEMPEC laboratory.

Last but not least, I express thanks to my dearest father for his effort,

encouragement and inspiration. ¡Te quiero mucho papá!

iv

Table of Contents

Abstract............................................................................................. i

Acknowledgments ........................................................................... iii

Table of Contents ............................................................................iv

List of Figures .............................................................................. xiii

List of Tables .................................................................................. xx

Chapter 1 Introduction ................................................................22

1.1...... General ...................................................................................................... 22

1.1.1 Congestion in Transmission Systems............................................ 24

1.1.2 Loop Flows ................................................................................... 24

1.2...... Power Flow Control through FACTS Technology...................................... 26

1.3...... Dynamic Compensation of Power System with FACTS Devices............... 28

1.4...... Literature Survey....................................................................................... 28

1.5...... State−of−the−Art....................................................................................... 33

1.5.1 The Convertible Static Compensator ............................................ 33

1.5.2 Distributed FACTS .......................................................................... 34

1.6...... Outline of the Research............................................................................. 36

v

Chapter 2 Vector Switching Converters ..................................... 39

2.1...... Introduction ............................................................................................... 39

2.2...... Three−Phase Vector Switching Converters .............................................. 39

2.2.1 Converter Model ........................................................................... 39

2.2.2 Equivalent Circuit ......................................................................... 43

2.2.3 Switch Realization ........................................................................ 46

2.2.4 VeSC Pulse Width Modulation...................................................... 47

2.3...... Multiple−Secondary Phase−Shifter Transformer ..................................... 50

Chapter 3 AC Link Power Flow Controllers............................... 54

3.1...... Introduction ............................................................................................... 54

3.2......Π−Controller: An AC Link Back−to−Back Intertie................................... 55

3.2.1 Topology ....................................................................................... 55


3.2.3 Principle of Operation ................................................................... 58

3.2.4 Control Capabilities ...................................................................... 61

3.2.4.1 Active Power Control.............................................................62

3.2.4.2 Reactive Power Control .........................................................63

3.2.4.3 Angle Control.........................................................................64

3.2.5 Design Considerations .................................................................. 65

3.2.5.1 Parameter Calculations...........................................................65

vi

3.2.5.2 Feasible operating range ........................................................66

3.2.6 Simulation Results ........................................................................ 67

3.2.7 Summary ....................................................................................... 69

3.3...... Ξ−Controller: An AC Link Series Compensator ....................................... 70

3.3.1 Topology ....................................................................................... 71






3.3.7 Summary ....................................................................................... 81

3.4...... Γ−Controller: An AC Link Unified Power Flow Controller...................... 81

3.4.1 Topology ....................................................................................... 82




3.4.4.1 Transmitted Power Control ....................................................90

3.4.4.2 Tap−changing/phase−shifting control....................................91


3.4.5.1 Transformers turn ratio ..........................................................93

3.4.5.2 Filter Capacitors / Switching Frequency................................93


vii

3.4.7 Summary ..................................................................................... 101

Chapter 4 Dynamic Modeling of AC Link Power Flow

Controllers 103

4.1...... Introduction ............................................................................................. 103

4.2...... Generalized Averaging Theory............................................................... 104

4.2.1 Index symmetry........................................................................... 105

4.2.2 Reconstruction............................................................................. 105

4.2.3 Derivative with respect to time ................................................... 106

4.2.4 Average of a product................................................................... 106

4.3...... Dynamics for electric elements............................................................... 106

4.3.1 Resistor........................................................................................ 107

4.3.2 Inductor ....................................................................................... 107

4.3.3 Capacitor ..................................................................................... 108

4.4...... Application to State Space Models for Vector Switching Converters.... 108

4.4.1 Real Excitation............................................................................ 114

4.4.2 Complex Excitation..................................................................... 117

4.5...... Case Studies ............................................................................................ 121

4.5.1 Generalized Averaging Applied to the Ξ−controller .................. 121

4.5.1.1 The Model ............................................................................121

4.5.1.2 Model Accuracy...................................................................124

viii

4.5.1.3 Eigenvalues Pattern..............................................................126

4.5.2 Generalized Averaging Applied to the Γ−controller .................. 127

4.5.2.1 The Model ............................................................................127

4.5.2.2 Model Accuracy...................................................................130

4.6...... Summary ................................................................................................. 133

Chapter 5 Feedback Control for AC Link Power Flow

Controllers 134

5.1...... Introduction ............................................................................................. 134

5.2...... Feedback Control for the Ξ−controller ................................................... 135

5.2.1 Proposed Controller .................................................................... 136

5.2.1.1 Small Signal Model..............................................................138

5.2.1.2 Controller Design via Bode Plots.........................................141

5.2.2 Simulation Results ...................................................................... 145

5.2.2.1 Response to a step change in the reference..........................145

5.2.2.2 Response to disturbances .....................................................146

5.3...... Feedback Control for the Γ−controller.................................................... 148

5.4...... Summary ................................................................................................. 149

ix

Chapter 6 A comparative evaluation of Power Flow Controllers

using AC Link and DC Link Converters........................................ 150

6.1...... Introduction ............................................................................................. 150

6.2...... Candidate Compensators......................................................................... 152

6.2.1 DC Link Series Compensator....................................................... 152

6.2.2 AC Link Series Compensator....................................................... 153

6.3...... Test system description ........................................................................... 155

6.4...... Steady state performance evaluation....................................................... 156

6.4.1 Operating Modes......................................................................... 156

6.4.2 Design Considerations ................................................................ 158

6.4.2.1 Choice of power semiconductors .........................................159

6.4.2.2 Injection Transformer...........................................................161

6.4.2.3 Capacitor ..............................................................................164

6.4.2.3.1 SSSC Capacitor Selection...............................................164

6.4.2.3.2 Ξ−Controller Capacitor Selection .................................166

6.4.2.4 Converter..............................................................................168

6.4.2.4.1 Semiconductors Ratings................................................168

6.4.2.4.2 Device Losses................................................................170

6.4.2.4.3 Waveform Quality.........................................................174

6.5...... Dynamic performance evaluation ........................................................... 175

6.5.1 Dynamic Modeling...................................................................... 175

x

6.5.2 Control Structure......................................................................... 176

6.5.3 Regulator Design......................................................................... 178

6.5.4 Command Response.................................................................... 179

6.5.5 Disturbance Response ................................................................. 180

6.6...... Summary ................................................................................................. 180

Chapter 7 Experimental Verification of the Γ−Controller .......182

7.1...... Introduction ............................................................................................. 182

7.2...... Experiment Layout.................................................................................. 183

7.2.1 Laboratory Prototype of a Transmission Line ............................ 183

7.2.2 Laboratory Prototype of a Γ−Controller ..................................... 185

7.3...... Experimental Waveforms........................................................................ 188

7.3.1 Steady Sate Operation ................................................................. 189

7.3.2 Dynamic Operation ..................................................................... 194

7.4...... Summary ................................................................................................. 195

Chapter 8 Optimal Power Flow with AC Link Power Flow

Controllers Embedded .................................................................197

8.1...... Introduction ............................................................................................. 197

8.2...... Standard OPF............................................................................................ 199

8.3...... OPF with Ξ−controllers embedded ......................................................... 201

xi

8.3.1 The model.................................................................................... 201

8.3.2 OPF Formulation .......................................................................... 202

8.3.3 Amount and Location.................................................................. 204

8.3.4 Case Study................................................................................... 205

8.3.4.1 Economic Dispatch ..............................................................206

8.3.4.2 Interface Power Maximization.............................................208

8.4...... Summary ................................................................................................. 210

Chapter 9 Conclusions and Future Work................................. 211

9.1...... Contributions........................................................................................... 213

9.1.1 Modeling and control .................................................................. 213

9.1.2 Computer simulation................................................................... 213

9.1.3 Comparison against the state−of−the−art technology for series

compensation........................................................................................... 214

9.1.4 Experimental verification............................................................ 215

9.1.5 System level modeling ................................................................ 215

9.2...... Proposed Continuing Research ............................................................... 215

9.2.1 Feedback Control for Γ−controller ............................................. 215

9.2.2 OPF with embedded Γ−controllers............................................... 216

9.2.3 System level dynamics................................................................ 216

9.2.4 Multilevel realization for the Ξ−Controller ................................ 217

9.2.5 Additional topologies .................................................................. 217

xii

9.2.6 Field demonstration..................................................................... 218

References ....................................................................................225

xiii

List of Figures

Figure 1-1 Example of a power system. ............................................................... 22

Figure 1-2 Schematic of a 2-bus system example................................................. 24

Figure 1-3 Schematic of a 3-bus system example................................................. 25

Figure 1-4 Schematic Illustrating Power Flow Control through a Transmission Line. .......................................................................... 26

Figure 1-5 Power Flow Control Evolution............................................................ 29

Figure 1-6 Schematic diagrams of DC link realizations for power flow control.............................................................................................. 31

Figure 1-7 Schematic of the Marcy Substation CSC.............................................. 34

Figure 1-8 Distributed Static Series Compensator (DSSC) Schematic. ................. 35

Figure 2-1 Circuit schematic of a three-phase VeSC synthesizing an adjustable pole voltage obtained from N throws.............................. 40

Figure 2-2 Single−phase equivalent circuit of a VeSC. ......................................... 44

Figure 2-3 Region of pole voltage obtainable for different throw realizations....................................................................................... 45

Figure 2-4 IGBT-Diode realization for the switch.................................................. 47

Figure 2-5 Waveforms Illustrating Pulse Width Modulation for Vector Switching Converters. ..................................................................... 49

Figure 2-6 A Simulink/DSP strategy to generate the gate pulses described in Figure 2-5. ................................................................................... 50

Figure 2-7 A four−winding three phase transformer to generate three secondary vector voltages 120° phase−shifted................................ 51

xiv

Figure 2-8 A five−winding three−phase transformer to generate four secondary vector voltages 90° phase−shifted.................................. 52

Figure 3-1 Schematic of a VeSC−based AC link intertie. ....................................... 55

Figure 3-2 Topology of a VeSC −based AC link intertie. ....................................... 56

Figure 3-3 Single−Phase averaged equivalent circuit. .......................................... 57

Figure 3-4 The ideal AC link intertie. .................................................................... 58

Figure 3-5 The “unity” rhombus. Permissible duty ratio values........................... 60

Figure 3-6 Variation of sets of duty ratios, (a), (b) and reactive power at receiving end, (c) as a function of active power control while Qs=0pu and θ=20°. ....................................................................... 62

Figure 3-7 Variation of sets of duty ratios, (a), (b) and reactive power at receiving end, (c) as a function of reactive power control while PS =1.5pu and θ=20°. .......................................................... 63

Figure 3-8 Variation of sets of duty ratios, (a), (b) and reactive power at receiving end, (c) as a function of phase−shifting control while PS =1.5pu QS=0pu. ................................................................. 64

Figure 3-9 Complex Power Nomogram at the sending end. (a) Entire operating range, (b) restricted and more practical operating range. ............................................................................................... 67

Figure 3-10 Phase−A voltage and current waveforms at the sending end............ 68

Figure 3-11 Phase−A voltage and current waveforms at the receiving end. ........ 69

Figure 3-12 Schematic of a VeSC−based AC link series compensator................... 71

Figure 3-13 Topology of a VeSC−based AC link series compensator. ................... 72

Figure 3-14 Single−Phase Averaged Equivalent Circuit. ..................................... 73

Figure 3-15 The ideal AC link series compensator................................................ 74

Figure 3-16 Equivalent impedance (a) and power at the receiving end (b) as a function of the duty ratio. ......................................................... 76

xv

Figure 3-17 Phase−A Current and Injected Voltage shown over a 60Hz period. .............................................................................................. 79

Figure 3-18 Simulation results for a step−change of the duty ratio (a) from 20 to 80%. (b) and (c) show the response of the line current and the power at the receiving end, respectively............................ 80

Figure 3-19 Simulation results for a ramp−change of the duty ratio (a) from 20 to 80%. (b) and (c) show the response of the line current and the power at the receiving end, respectively. .............. 80

Figure 3-20 Schematic of a VeSC−based AC link Unified Power Flow Controller......................................................................................... 82

Figure 3-21 Topology of a VeSC−based AC link Unified Power Flow Controller......................................................................................... 83

Figure 3-22 Single−Phase Averaged Equivalent Circuit. ..................................... 86

Figure 3-23 The ideal AC link Unified Power Flow Controller. ........................... 87

Figure 3-24 Receiving−end power control. .......................................................... 91

Figure 3-25 Tap−changing, phase−shifting control. ............................................. 92

Figure 3-26 Resonance frequency as a function of the capacitor value................ 94

Figure 3-27 Phase−A Voltage and Current at the receiving−end. ........................ 96

Figure 3-28 Phase−A Capacitor voltages.............................................................. 97

Figure 3-29 Phase−A SPT transformer currents. .................................................. 98

Figure 3-30 Duty Ratio Commands. Stepped from d1=33%, d2=35%, d3=32% d4=0% to d1=0%, d2=18%, d3=57% d4=25%. ................... 99

Figure 3-31 Response to a duty ratio step change of the (a) line current, (b) active power and (c) reactive power, all at the receiving end. .................................................................................................. 99

Figure 3-32 Duty Ratio Commands. Ramped from d1=33%, d2=35%, d3=32% d4=0% to d1=0%, d2=18%, d3=57% d4=25%. ................. 100

xvi

Figure 3-33 Response to a duty ratio ramp change of the (a) line current, (b) active power and (c) reactive power, all at the receiving end. ................................................................................................ 101

Figure 4-1 Schematic of a generic power system with a vector switching converter embedded....................................................................... 109

Figure 4-2 Waveforms corresponding to the switching function, index 0 approximation (duty ratio) and index 0, -N, N approximation. All with d=50%. .................................................. 113

Figure 4-3 Exact model for the Ξ−controller. ..................................................... 122

Figure 4-4 Waveform of the switched capacitor current along with the traditional and augmented approximations. FP=60(Hz), FS=1020(Hz), d=50%. ................................................................... 125

Figure 4-5 Eigenvalues distribution for the different models. FR=30(Hz), FP=60(Hz), FS=1020(Hz)............................................................... 127

Figure 4-6 Exact model for the Γ−controller. ..................................................... 128

Figure 4-7 Capacitor voltage waveforms with FR=1862(Hz) and FS=2400(Hz).................................................................................. 131

Figure 4-8 Capacitor voltage waveforms with FR=1862(Hz) and FS=1800(Hz).................................................................................. 132

Figure 5-1 Configuration for classical control design......................................... 134

Figure 5-2 Block diagram of the control system................................................. 137

Figure 5-3 Block diagram for the small signal model......................................... 140

Figure 5-4 Bode Plot for the partial loop gain βg(jω)......................................... 143

Figure 5-5 Bode Plot for the PI controller h(jω). ................................................ 144

Figure 5-6 Gain and Phase margins from the loop gain T(jω)= βh(jω)g(jω)........................................................................ 144

Figure 5-7 Response to a 15% step change in the reference power. (a) shows the step change applied to the reference power while (b) and (c) show the response on the line current and the measured power at the receiving end, respectively. ...................... 146

xvii

Figure 5-8 Response to a 5% step change in the sending end voltage. (a) shows the step change applied to the magnitude of the sending end voltage while (b) and (c) show the response on the line current and the measured power at the receiving end, respectively.................................................................................... 147

Figure 5-9 Response to a 3° step change in the transmission angle. (a) shows the step change applied to the transmission angle while (b) and (c) show the response on the line current and the measured power at the receiving end, respectively. ................ 147

Figure 5-10 Control system for the Γ−controller. ............................................... 148

Figure 6-1 Schematic of candidate compensators. (a) SSSC (b) Ξ−controller................................................................................... 153

Figure 6-2 Converter realizations. (a) SSSC (b) Ξ−controller.............................. 154

Figure 6-3 Waveforms illustrating AC voltage synthesis. (a) SSSC. (b) Ξ−controller................................................................................... 154

Figure 6-4 One line diagram of the candidate series compensation system. ...... 155

Figure 6-5 Steady sate equivalent circuits. (a) SSSC (b) Ξ−controller................. 157

Figure 6-6 Switch realization in terms of real semiconductors. For the SSSC, 4 series IGCT with antiparallel diode (ABB 5SHX 08F4510) are used. The clamping diode is also realized using 4 diodes in series (ABB 5SDF 03D4502). For the Ξ−controller, 3 parallel IGBT with antiparallel diode (EUPEC FZ600R65KF1) are used. .............................................................. 169

Figure 6-7 Pole current breakup. (a) SSSC, (b) Ξ−controller............................... 173

Figure 6-8 Voltage/Current injected into the transmission line. (a) SSSC, (b) Ξ−controller. ............................................................................ 175

Figure 6-9 Dynamic equivalent circuits. (a) SSSC, (b) Ξ−controller. .................. 176

Figure 6-10 Feedback control loop. TS=5 (ms), β=10-6. (a) SSSC, (b)

Ξ−controller................................................................................... 177

Figure 6-11 Dc voltage equalizing algorithm ..................................................... 177

xviii

Figure 6-12 Small signal frequency response of loop gain of (a) SSSC, (b) Ξ−controller................................................................................... 178

Figure 6-13 Computer simulation waveforms illustrating response to command changes. (a) SSSC, (b) Ξ−controller............................... 179

Figure 6-14 Computer simulation waveforms illustrating response to bus voltage and angle disturbances. (a) SSSC, (b) Ξ−controller. ......... 180

Figure 7-1 Schematic of the Γ−controller system implemented in the laboratory....................................................................................... 182

Figure 7-2 Laboratory prototype of a transmission line...................................... 184

Figure 7-3 Laboratory prototype of a transmission line connecting two stiff voltage busbars....................................................................... 185

Figure 7-4 Laboratory prototype of a Γ−controller............................................. 186

Figure 7-5 Detailed laboratory prototype of a Γ−controller system. ................. 187

Figure 7-6 Picture of hardware built at the laboratory. ...................................... 188

Figure 7-7 Attainable pole voltage (a) and the corresponding power diagram (b). ................................................................................... 189

Figure 7-8 Experimental waveforms showing the gate voltage applied to the IGBTs. ....................................................................................... 191

Figure 7-9 Waveforms showing the voltage at location V2. (a) Experimental (b) Simulated........................................................... 191

Figure 7-10 Waveforms showing the line current. (a) Experimental (b) Simulated. ...................................................................................... 192

Figure 7-11 Waveforms showing the injected voltage. (a) Experimental (b) Simulated. ................................................................................ 193

Figure 7-12 Waveforms showing the fundamental component of the injected voltage. (a) Experimental (b) Simulated.......................... 193

Figure 7-13 Waveforms showing the injected voltage at the switching frequency timescale. (a) Experimental (b) Simulated. .................. 194

xix

Figure 7-14 Experimental waveforms illustrating the transition from one operating point to another by means of duty ratio ramping. ......... 195

Figure 8-1. A 3−area electric power system. ...................................................... 198

Figure 8-2 Simplified Equivalent Circuit for the Ξ−controller........................... 201

Figure 8-3 The IEEE 39−bus system. ................................................................... 205

xx

List of Tables

Table 1-1 Complex Power Sensitivities................................................................ 27

Table 6-1 System Data ........................................................................................ 156

Table 6-2 Operating Modes ................................................................................ 158

Table 6-3 Injection Transformer Rating ............................................................. 163

Table 6-4 Capacitor Requirements Summary..................................................... 167

Table 6-5 Devices Stress..................................................................................... 169

Table 6-6 Devices Capability.............................................................................. 170

Table 6-7 Device Count ...................................................................................... 170

Table 6-8 Converter Losses ................................................................................ 172

Table 6-9 Active state for semiconductors.......................................................... 173

Table 6-10 Analytical description for IT1A .......................................................... 173

Table 6-11 Converter Losses for PL=160(MW), QINJ=7.7(MVAr) .................... 174

Table 6-12 Total Harmonic Distortion (THD).................................................... 175

Table 6-13 Regulator Design Results ................................................................. 179

Table 7-1 Γ−controller component rating ........................................................... 186

Table 7-2 Operating Point................................................................................... 190

Table 8-1 Active Constraints .............................................................................. 206

Table 8-2 Interface Flows ................................................................................... 207

Table 8-3 Active Constraints .............................................................................. 207


xxi


22

Chapter 1 Introduction

1.1 General

The electric power industry has traditionally been divided into three sectors:

generation, transmission and distribution. At the generation stage, electricity is produced

from sources such as fossil fuel, nuclear fuel, or waterfalls. Then, the electric power is

injected into the transmission system which is configured as an interconnected network

of transmission lines and control devices. Finally, at the distribution stage, the power is

taken from the transmission system and delivered to consumers at specific standards of

quality and reliability. These three stages together −generation, transmission and

distribution− are generically known as a power system. Figure 1-1 illustrates a possible

realization of such a system.

Distribution

Transmission Network

Figure 1-1 Example of a power system.

23

Since the ultimate goal of a power system is to deliver power to consumers, a

perfectly valid question is why an interconnected transmission system is needed. Why

not deliver power via radial lines from local generators to local consumers without being

part of a meshed network? The real need for an interconnected transmission system is

twofold: (i) it allows for the pooling of power plants and load centers in order to

minimize the total power generation capacity and fuel cost and (ii) it improves the

reliability of power supply through redundancy.

Following this trend, transmission networks throughout the world have

developed into enormous, complex systems containing thousands of transmission line

segments interconnecting large geographical areas.

However, during the last few decades the electricity industry has had to face two

new issues. On the one hand, due to environmental pressures and right−of−way matters,

it is becoming increasingly difficult, if not impossible, to build new transmission lines in

order to satisfy the always increasing demand for electric power. As a result of this,

existing transmission systems are being pushed to operate close to their capacity limits

and transmission line congestion is being observed in several regions particularly those

with large load growth at large populated centers. On the other hand, due to the

deregulation of the electricity industry that has taken place, channeling power flows

through pre−established contractual paths has become a priority for the system

participants. This issue is known as the loop flow problem. These issues are briefly

reviewed in the following sections.

24

1.1.1 Congestion in Transmission Systems

The concept of congestion in transmission networks can be understood by

considering a simple case of a generator serving a load through two parallel transmission

lines, as suggested in Figure 1-2. Say the transmission line l1 has an impedance X and a

maximum capacity to carry power given by Pm. The second line, l2, has exactly the same

impedance as l1 but its maximum capacity is only 0.5Pm. Since both lines have the same

impedance, the power sent from the generator G to the load L equally splits into the two

transmission lines, as suggested in the figure. When the power demanded by L is less

than Pm, the system operates within its capacity margins since each line is carrying less

power than 0.5Pm. However, when the load L demands more power than Pm, say 1.2Pm,

each line carries 0.6Pm, which overloads the line l2. Notice that the combined capacity of

both lines is 1.5Pm, but the system is unable to carry such an amount of power due to the

congestion in one of the lines. Situations like this, in a more complex context, are

frequently encountered in modern power systems [1].

l1: X, Pm

l2: X, 0.5Pm

P

P

G L

Figure 1-2 Schematic of a 2-bus system example.

1.1.2 Loop Flows

The concept of loop flows, also known as parallel flows, is formally discussed in

Chapter 8, but here it can be described considering a simplified 3−bus system as

25

suggested in Figure 1-3. Say the generator G1 has a contractual obligation of serving the

load L2 by an amount of Pc. For that purpose, the generator “reserves” capacity on the

line 1−2 for that amount. However, since power flows obey Kirchhoff’s laws and not

contractual paths, only a fraction of such a flow (κPc) will actually follow the contractual

path and the remaining amount, (1−κ)Pc, will flow through the bus 3, creating an

undesired loop flow.

Figure 1-3 Schematic of a 3-bus system example.

Thus, the philosophy for modern transmission system operation can be

summarized as follows: “Optimal utilization of the existing transmission network subject

to both system limits and security requirements”. “Optimal” can mean, among other

things, minimum fuel cost, maximum loadability, or minimum loop flows, depending on

the goals pursued. System limits are threefold: thermal limits on transmission lines,

voltage profile limits, and stability limits. The security requirement, known as (n−1)

contingency criterion, is that the system must satisfy the same quality standard even

when any of its facilities has an outage. In order to satisfy these new needs, power

engineers have developed the concept of Flexible AC Transmission Systems, FACTS [1-3].

26

1.2 Power Flow Control through FACTS Technology

The basics of power flow control can be understood by considering a purely

inductive transmission line connecting two buses, as suggested in Figure 1-4(a).

(a) A purely inductive transmission line (b) A transmission line with an embedded FACTS device

Figure 1-4 Schematic Illustrating Power Flow Control through a Transmission Line.

Using elementary phasor ideas it can be shown that the complex power flow

measured at the bus 1 of the line is given by,

)cosX

VV

X

V(jsin

X

VVQjPS 21

2121 θ−⋅+θ=⋅+= (1-1)

where P and Q are the active and reactive power, respectively. It can be seen from

Equation (1-1) that value of the power flow depends upon four parameters, namely, the

magnitude of the voltage at each bus, V1 and V2, the transmission angle, θ, and the line

reactance, X. Consider now the insertion of a FACTS device as shown in Figure 1-4(b)1.

By means of a power electronics−based control, FACTS devices are able to modify one (or

1 The symbol shown in the figure has been introduced in [14] to represent a generic FACTS device.

27

more) of the parameters that define the power flow equation, and therefore realize power

flow control. This simple but powerful idea is the core of FACTS technology.

It is evident from Equation (1-1) that the modification of any of the parameters

affects both the active and reactive power simultaneously. Table 1-1 shows the sensitivity

functions of the complex power with respect to the system parameters for a typical set of

values encountered in a power system.

Table 1-1 Complex Power Sensitivities. V1=V2=1pu, θ=10°, X=0.5pu.

↓∂

→∂ P Q

θ 1.97 0.35 X -0.69 -0.06 V1 0.35 2.03

As can be seen, the transmission angle and the line reactance have a much bigger

relative influence on the active power while the value of the bus voltage mostly affects

the value of the reactive power. Thus, the control of either the transmission angle or the

line reactance can be considered as active power compensation whereas the control of the

bus voltage can be considered as reactive power compensation. This decoupling effect

has been successfully used in other areas of power engineering as well, such as the DC

power flow method [4, 5].

As will be discussed in the Literature Review Section, the power

electronics−based control can take different forms, with semiconductors with no gate

turn−off (only gate turn−on), or with power devices with gate turn−off capability,

depending on the application pursued [6].

28

1.3 Dynamic Compensation of Power System with

FACTS Devices

Although the focus of this research is on steady state power flow control, it is

important to mention that FACTS devices can also enhance the various types of stability

limits of a power system [7]. With respect to the large−signal stability, it can be shown

by means of the equal area criterion [4], that FACTS devices can enlarge the stability

margin of a system upon a short−circuit fault. In the small−signal stability arena, it can

be demonstrated that FACTS are able to damp power oscillations that occur as a result of

minor system disturbances. Finally, voltage stability can also be improved as FACTS

devices are able to reshape the nose−curve [5, 8].

1.4 Literature Survey

Although the concept of FACTS was introduced by Dr. Narain G. Hingorani as a

response of modern power systems needs, the aim of controlling power flows in

transmission network is not new. Ever since power systems were conceived, there was an

interest in controlling the power flows through the transmission network.

The literature review can be performed by following the evolution that the power

flow control technology has featured throughout the years. Figure 1-5 shows the various

technologies that have been applied to effectively realize power flow control.

29

Figure 1-5 Power Flow Control Evolution.

The earliest devices conceived for power flow control, well before the

introduction of FACTS, are the mechanically switched phase−shifter and tap−changer

transformers. The former control the transmission angle and therefore realize active

power flow control whereas the latter control the bus voltage to realize reactive power

compensation [4]. These devices, although still broadly used, have two major drawbacks.

Since they are mechanically switched, they are difficult to operate and have a slow speed

of response. Moreover, since they have a small number of tap positions, they can only act

in a discrete way. With the development of semiconductor devices, however, proposals

have been made to realize the switching with for example, back−to−back thyristors, in

30

order to improve the speed of response [9, 10]. In addition, hybrid approaches embedding

DC−AC inverters have been proposed for the purpose of achieving continuous control [11,

12].

The invention of the mercury valve allowed the development of the high voltage

direct current (HVDC) transmission technology [7, 13]. Modern semiconductors such as

the thyristor, GTOs and IGBTs have also been use to realize HVDC systems. The basic idea

behind HVDC technology is to cascade a rectifier, a DC−link, and an inverter. The DC−link

can be either a capacitor or an inductor, leading to a voltage or current sourced system,

respectively. The control takes place in the rectification and inversion process, as the

firing angle (or the pulse duration) can be externally manipulated. These systems can

continuously control the active power and in the case of converters with gate turn−off

capability, they can realize independent reactive power flow control as well. In addition,

HVDC interties feature the unique property of decoupling the AC dynamics of the systems

being interconnected and, as a result of this, they can be used to interconnect systems

operated at different frequency, as it is done, for example, in the Itaipu interconnection,

that joins the 60Hz Brazilian system with the 50Hz Paraguayan system. The major

disadvantage of these systems is the high rating needed for the semiconductors. They

have to carry the entire power throughput and consequently the cost is high.

Phase controlled devices correspond to the next technology that came about and

are consider the first generation of FACTS controller [14]. Based on thyristors, they come

in two flavors. The shunt connected device, called Static Var Compensator (SVC) [7, 14],

injects an adjustable amount of reactive power in to the system and as a result of the

31

sensitivities explained in Table 1-1 is credited as a voltage regulator. The series

connected device called Thyristor Controlled Series Capacitor (TCSC) [7, 14], can

continuously adjust the reactance of the transmission line hence realizing active power

flow control. Moreover, as these controllers do not involve any change of frequency to

realize the power flow function, they may be considered AC↔AC devices.

The development of high−power semiconductors with turn−off capability paved

the way to the next generation of FACTS devices. Led by Dr. Laszlo Gyugyi, a group of

engineers from SIEMENS have developed the Static Synchronous Compensator

(STATCOM) [15], the Static Synchronous Series Compensator (SSSC) [16], the Unified

Power Flow Controller (UPFC) [17], and the Interline Power flow Controller (IPFC) [18].

Together, these devices constitute the family of voltage source DC link power flow

controllers that have been unified under the Convertible Static Compensator (CSC) [19].

Figure 1-6 shows the various ways these devices are embedded into a transmission line.

(a) The shunt connected STATCOM (b) The series connected SSSC

DC link

Transmission line 1

Transmission line 2

(c) The shunt−series connected UPFC (d) The series−series connected IPFC

Figure 1-6 Schematic diagrams of DC link realizations for power flow control.

32

The STATCOM and the SSSC have, respectively, an analogous function to the SVC

and TCSC i. e., the STATCOM provides voltage support and the SSSC injects quadrature

voltage into the line hence realizing active power flow control. The UPFC can

simultaneously and selectively provide voltage support, and realize active and reactive

power through the line. Lastly, the IPFC can provide series compensation to two (or more)

transmission lines and also allow transfer of real power between the cross−connected

lines. It is important to notice that for each of these devices the inverter realization as

well as the modulation strategy can take different forms [20].

Finally, a few devices that follow the approach of fast switching direct AC↔AC

conversion without frequency change to realize power flow control have recently

appeared in the literature. The research has been conducted in terms of matrix converter

[21] based power flow controllers [22, 23] and in terms of more restricted configurations

such as the vector switching converter (VeSC) [24-28].

As may be observed from Figure 1-5 (left part), there has been a continuous push

and pull between DC link and AC link technology, driven mostly by the availability of

switching power semiconductors. This research focuses on the next leap introducing fast

switching FACTS devices with the potential of better performance and controllability.

33

1.5 State−−−−of−−−−the−−−−Art

The current state−of−the−art for FACTS controllers may be conveniently divided

into two categories. The Convertible Static Compensator installed in the Marcy

Substation in New York may qualify as the state−of−the−art already available technology

while the concept of distributed FACTS devices may be eligible for the state−of−the−art

technology still in a research stage.

1.5.1 The Convertible Static Compensator

The Convertible Static Compensator (CSC), installed at the Marcy 345 kV

substation in Central New York, has been developed through a joint effort between the

New York Power Authority (NYPA), SIEMENS Power Transmission & Distribution, and

the Electric Power Research Institute (EPRI) [19]. It can be considered as the unification

of the various DC link FACTS devices described in Figure 1-6, as it can adapt to operate as

a STATCOM, SSSC, UPFC or IPFC. The general CSC configuration shown in Figure 1-7

consists of two 100MVA inverters, two 100MVA series transformers, and a single

200MVA shunt transformer with two identical secondary windings. The low voltage

disconnect switches allow utilization of the two inverters in various shunt and series

configurations, resulting in eleven different configurations.

34

Line 1

To New Scotland

Line 2

To Coopers Corners

Figure 1-7 Schematic of the Marcy Substation CSC.

This device is already operative and has proven its versatility in controlling the

Marcy 345kV bus voltage as well as in regulating the power flow on the Marcy−New

Scotland and Marcy−Coopers Corners lines.

1.5.2 Distributed FACTS

The concept of distributed FACTS (D−FACTS) has very recently been introduced

[29]. The idea is to use low rated power converters that can be (i) mass−manufactured,

(ii) massively dispersed, and (ii) remotely operated to realize power flow control.

The proposal, shown in Figure 1-8, consists of Distributed Static Series

Compensator (DSSC) modules realized by means of a small rated (~10 kVA) single phase

35

DC link voltage source inverter and a single turn transformer, along with associated

controls, power supply circuits and built−in communications capability.

Figure 1-8 Distributed Static Series Compensator (DSSC) Schematic.

As shown in the above figure, the module consists of two parts that can be

physically clamped around a transmission conductor. The transformer and mechanical

parts of the module form a complete magnetic circuit only after the module is clamped

around the conductor. The weight and size of the DSSC module is low, allowing the unit

to be suspended mechanically from the power line. The module is self−excited from the

power line itself. The unit normally sits in bypass mode until the inverter is activated.

Once the inverter is turned on, the DSSC module can inject a quadrature voltage into the

line, allowing a “small” power flow control action. The overall system control function is

achieved by using a large number of modules coordinated through communications and

36

smart controls.

As can be seen, the state−of−the−art corresponds to FACTS devices based on DC

link voltage source converters. The research proposed in this thesis represents an

alternative to this technology.

1.6 Outline of the Research

The background necessary to understand AC link power flow controllers is

provided in Chapter 2. The concept of the vector switching converter (VeSC) is

introduced, along with the corresponding converter model, equivalent circuit, switch

realization, and modulation strategy. In some of the applications pursued in this thesis,

VeSCs commute between phase−shifted voltage sources of equal magnitude. For that

purpose, multiple−secondary phase−shifter transformers are also discussed.

Chapter 3 is the core of this thesis proposal. It introduces a new family of FACTS

devices: the Π−controller, the Ξ−controller and the Γ−controller. Based on the vector

switching converter, these devices feature functional characteristics similar to the ones

encountered in the voltage source HVDC interties, the Static Synchronous Series

Compensator (SSSC) and the Unified Power Flow Controller (UPFC), respectively. The

control function, however, is realized by direct AC↔AC conversion without frequency

change, adopting the strategy of pulse width modulation (PWM).

In Chapter 4, generalized averaging theory is used to develop the dynamical

model for the controllers proposed in Chapter 3. Averaging theory is a generalization of

the concept of dynamic phasors and becomes especially useful when the natural modes of

37

the physical system are located in the vicinity to the switching frequency. It that case, it

gives a more accurate description of the system behavior, as it is able to capture the

dynamics of the waveforms’ ripple.

Using the dynamical model developed in Chapter 4, closed loop regulation is

assessed in Chapter 5. In the case of the Ξ−controller, the regulator design is performed

analyzing the frequency response of the small−signal transfer function. The ideas of

security margins for stability are used as design criteria. The Γ−controller regulator

design is briefly discussed and proposed as a part of the future work.

For the series compensation case, this new technology is contrasted against the

state−of−the−art in Chapter 6. A detailed comparative study between the Ξ−controller

and the SSSC shows that the use of VeSC−based power flow controllers may become a real

alternative for the next generation of FACTS devices.

In order to fully prove the concept of VeSC−based power flow controllers, a

laboratory prototype was built and tested. The Γ−controller was chosen for experimental

verification, as its topology is the most general of all three controllers. These results are

presented in Chapter 7.

Chapter 8 gives a system point of view of the power flow control problem,

incorporating the Ξ−controller into an optimal power flow (OPF) program. A case study

of the IEEE 39−bus system shows that the economic dispatch as well as control of the

power exchange between control areas can be enhanced by embedding the Ξ−controller

into the transmission lines. Optimal power flow with Γ−controllers is proposed as a part

of the continuing research.

Finally, the conclusions and continuing work for this dissertation are given in

38

Chapter 9.

All computations throughout this thesis were executed using the MATLAB

mathematical analysis software package. Simulations were developed using MATLAB’s

simulator package SIMULINKTM.

39

Chapter 2 Vector Switching

Converters

2.1 Introduction

This chapter introduces the three−phase vector switching converters as well as

multiple−secondary phase−shifter transformers. The former represent the foundations to

realize AC link power flow control while the latter is an auxiliary tool needed in some

applications.

2.2 Three−−−−Phase Vector Switching Converters

The principles of operation of three−phase vector switching converters (VeSC)

have been described in detail in [26]. Although their realization and applications for

power flow control can take various forms, herein the attention is focused on

point−to−point applications. More generalized configurations and operations may be

found in [26].

2.2.1 Converter Model

A schematic of an N throw single pole three−phase VeSC is illustrated in Figure

40

2-1. The system synthesizes an adjustable three phase pole voltage (VP(A-C)) by switching

among N stiff three−phase voltage sources (VT1(A-C), VT2(A-C)… VTN(A-C)).

VT1A

IT1A

VT1B

IT1B

VT1C

IT1C

VT2A

IT2A

VT2B

IT2B

VT2C

IT2C

VTNA

ITNA

VTNB

ITNB

VTNC

ITNC

t1B

t2B

tNB

SB

t1C

t2C

tNC

SC

t1A

t2A

tNA

SA

VPA

IPA

VPB

VPC

IPC

IPB

Figure 2-1 Circuit schematic of a three-phase VeSC synthesizing an adjustable pole voltage obtained from N

throws.

The throws of the switches are assumed ideal for the purpose of the discussion

herein, as is common in preliminary functional analysis of switching power converters.

These assumptions include: (i) negligible forward voltage drop of the switch throws in

their on−state; (ii) sufficient on−state current carrying capacity and off−state voltage

blocking capacity commensurate and compatible with the voltage and current ratings of

the system; and (iii) negligible transition periods between open and closed of the switch

throws that permit repetitive high frequency switching. Furthermore, the nominal

frequency of the three−phase voltages and currents (power frequency) are assumed

41

identical, in the absence of which there could be no net steady state power transfer among

them.

The voltages at the throw terminals of the switch are assumed stiff such that their

variations during a switching period can be neglected. Similarly, the switch pole currents

are assumed stiff such that their variations over a switching period can be neglected.

These assumptions essentially allow the focus to be on the power transfer process and the

functional features. In practical power converters, filter elements appropriately applied at

the input and output ports of the system would ensure that these assumptions are valid.

Snubber circuits may further be applied to provide for appropriate commutation features

during the finite transition periods between switch states. It is important to notice that in

AC systems, the designation of the stiff voltage and stiff currents is arbitrary. Stiff voltage

sources and stiff current sources can be transformed into either by adding series inductors

or shunt capacitors, respectively, in order to fit application considerations.

As indicated in Figure 2-1, the three poles are ganged together i.e., they switch

concurrently between the throws to which they are connected. This can be

mathematically expressed as tiA = tiB = tiC = ti, for i = 1, 2…N.

The transfer properties can be represented using the vector equations consisting of

three components for each of the terminal quantities. In this case, the vectors

representing the throw voltages, throw currents, pole voltages and pole currents become

VTi = [VTiA VTiB VTiC]T, ITi = [ITiA ITiB ITiC]

T, VP = [VPA VPB VPC]T, IP = [IPA IPB IPC]

T

respectively, for i=1,2…N. Thus, the pole voltage and throw currents can be expressed

as,

42

∑=

⋅=N

1iTiiP (t)q(t) VV (2-1)

PiTi (t)q(t) II ⋅= for i = 1, 2,…N (2-2)

where

= otherwise 0

closed is tif 1(t)q ii is the switching function of a throw connecting the

voltage VTi to the current IP. When the repetition frequency of the switching function (or

simply the switching frequency) is large with respect to the power frequency, net power

transfer between the voltage ports and the current ports arises from the average value (DC

component) of the switching function. The DC component of the switching function may

be readily represented by the duty ratio of the particular throw. Thus, under proper

assumptions (discussed in Chapter 4), the transfer relationships (2-1) and (2-2) may be

simplified as

∑=

⋅=N

1ii (t)d(t) TiP VV (2-3)

PTi II ⋅= (t)d(t) i for i = 1, 2,…N (2-4)

where the duty ratio of the ith throw is defined as

∫+

⋅=STt

t

iS

i τd)τ(qT

1)t(d for i = 1, 2...N (2-5)

where TS is the switching period. As may evident from the definition of q(t),

43

∑=

=N

1ii 1(t)d (2-6)

Since the operating principle of these converters is based on controlling the

connectivity between various three−phase AC voltage and/or current vectors by switching

among their components concurrently, these converters have been termed vector

switching converters [26]. The distinguishing features of vector switching converters as

compared to matrix switching converters have been explored also in [26].

2.2.2 Equivalent Circuit

Relationships (2-3) and (2-4) indicate a reciprocal input↔output transfer property

similar to that of a transformer. Therefore, the fundamental component averaged vector

(or single−phase) equivalent circuit of the converter system may be represented as shown

in Figure 2-2. Figure 2-2(a) describes the input↔output reciprocal relationships

explicitly as dependent sources, while Figure 2-2(b) implicitly represents them in the

form of a magnetically coupled transformer with winding turns ratios equivalent to the

duty ratios of the throws.

44

VTN

VT2

VT1

IP

d1IP

d2IP

dNIP

d1VT1

d2VT1

+

+

+dNVT1

VTN

ITN

1/dN

VT2

IT2

1/d2

VT1

IT1

1/d1

IP

1

VP

(a) Controlled source coupling (b) Magnetic coupling

Figure 2-2 Single−phase equivalent circuit of a VeSC.

As is evident in either realization, the net pole voltage, VP, depends on the value

(magnitude and phase) of the throw voltages as well as the corresponding duty ratios.

These equivalent circuits may be conveniently utilized to derive and study the application

of three−phase vector switching converter for AC power flow control by incorporating

them in power system load flow and dynamic analysis programs.

Figure 2-3 shows the realizable pole voltage values, represented by the gray

shaded region in the phasor plane, for different combinations of throw voltages and

number of throws.

45

VT1

VT2

VT3

VT4 PV

VT1V

T2

VT3

VT4

(a) Quadruple−throw switch with random magnitude/phase throw voltages

(b) Quadruple−throw switch with random magnitude/phase throw voltages and one redundant

throw voltage.

VT1

VT2

VT3

PV

VT1

VT2

VT3

VT4

PV

(c) Triple−throw switch with identical

magnitude, 120° phase−shifted throw voltages (d) Quadruple−throw switch with identical magnitude,

90° phase−shifted throw voltages

Figure 2-3 Region of pole voltage obtainable for different throw realizations.

Figure 2-3(a) and Figure 2-3(b) show realizable pole voltage with arbitrary

voltages (VT1–VT4) available for each of the throws (1−4). It may be observed that the

region of the realizable pole voltages is given by the largest polygon whose vertices are

the locations of the corresponding throw voltages and the phasor origin. For power flow

control applications [14, 19], one is usually interested in synthesizing voltages within

symmetric regions in all directions about the origin, which would be given by the largest

circle that can be inscribed inside the polygon about the origin.

It can be seen in Figure 2-3(a) that there is a large unused area outside the

circumference. Figure 2-3(b) shows that not only is it impossible to trace a complete

46

circle circumference but also that there is a redundant voltage source, namely VT2. On the

other hand, Figure 2-3(c) and Figure 2-3(d) show symmetric realizations with three

throws and four throws, respectively. The adaptation of these realizations for power flow

control will be explored in Section 2.3.

2.2.3 Switch Realization

Although the operation of the VeSC converter presented in Figure 2-1 does not

require the three−phase AC sources and loads to be balanced, the analytical development

presented herein is limited to the case of balanced sources and loads. Since balanced

three−phase AC systems may operate as three wire systems, the reference terminal that

provides the return path for the three−phase currents carries no current (shown in gray

line on Figure 2-1) and may be eliminated. As a result, due to inherent symmetry in

three−phase voltage and current waveforms, when all the three−phase AC ports are three

wire systems, the throws may be realized using bi−directional current conducting, but

unidirectional voltage blocking capability as illustrated in Figure 2-4 in terms of

IGBT−diode pairs. Other devices such as GTOs may be used instead of IGBTs in order to fit

rating considerations.

47

Figure 2-4 IGBT-Diode realization for the switch.

2.2.4 VeSC Pulse Width Modulation

Pulse Width Modulation (PWM) is widely used to create the train of pulses that

define the converter switches ON times, which create a desired low−frequency target

output waveform [30, 31]. The basic strategy is to switch at the intersection of a

reference signal and a high−frequency carrier signal. The reference signal carries the

information that defines the properties of the target waveform whereas the carrier signal

defines the switching frequency. The main advantage of PWM is that it moves the

harmonics generated from the switching process to frequencies high enough to make

filtering possible with smaller components [32]. All PWM algorithms have to address the

following three fundamental issues [30]:

• Switch pulse width calculation

• Switch pulse position within a carrier interval

• Switch pulse sequence within a carrier interval

48

Thus, depending on the strategy selected, the target output waveform will feature the

properties needed for the specific application.

For power flow control applications using the vector switching converter, both

input and output waveforms have the same frequency, therefore there is no frequency

change and, similarly to the case of PWM DC/DC converters, a simple algorithm that

compares the duty ratio against a sawtooth carrier signal can be used to generate the

pulses.

Figure 2-5 graphically shows the process to determine the width of the pulses for

a triple throw single pole switch. As can be seen, it uses a predetermined sequence (d1, d2

d3 in this case) and turns a switch on every time the accumulated references intercept the

carrier signal. In addition, every time a switch is turned on, the previous switch in

sequence in turned off.

The practical implementation of this strategy is presented in Figure 2-6 in a

Simulink/DSP environment. It takes the duty ratios as inputs and compares the

corresponding summations against the carrier signal. The output of these comparisons

are transformed into Boolean variables and then manipulated as shown in the figure in

order to fit the restriction of turning off the previous switch in the sequence when the

current switch in turned on. Finally, the various signals are transformed back into real

numbers to generate the pulses.

This process can be readily generalized to any number of throws by simply

adding more duty ratios in Figure 2-5 and Figure 2-6. In addition, in order to fit practical

applications, adequate dead times should be added to avoid switches ON−states

49

overlapping.

Figure 2-5 Waveforms Illustrating Pulse Width Modulation for Vector Switching Converters.

The performance of this strategy clearly depends on the sequence selected to

aggregate the duty ratios. Any arrangement would produce the same fundamental

50

frequency waveforms, but the harmonics content would vary depending on the sequence

selected. Optimal sequence arrangement can be designed for a specific application but

such a topic is beyond the scope of the present study.

d3

d2

d1

1

2

3

+

+

+

+

+

Carrier

>

>

>

P2

P1

1

2

3

NOT AND

NOT AND

P3

double

double

double

True=1False=0

Boolean StageBack to RealNumbers

Figure 2-6 A Simulink/DSP strategy to generate the gate pulses described in Figure 2-5.

2.3 Multiple−−−−Secondary Phase−−−−Shifter Transformer

The synthesis of multiple throws is an essential requirement for using vector

switching converters as power flow controllers some applications. Indeed, as can be seen

in Figure 2-3, the adjustable pole voltage is realized by switching among different stiff

voltage sources.

Three−phase systems feature the property that, given one set of three−phase

voltages, it is possible to synthesize multiple electrically isolated sets of voltages using

multi−winding transformers.

Consider the four−winding three−phase transformer presented in Figure 2-7(a).

The windings drawn parallel are physically located in the same magnetic path. All

51

windings are Y−connected and one of them corresponds to the primary while the

remaining three make a multiple−secondary set. Since there are three sets of three−phase

windings at the secondary side, three isolated voltage sets are created, say A1, B1, C1,

A2, B2, C2 and A3, B3, C3. Moreover, as a result of the convenient phase designation

given to the various windings, the corresponding phase−to−neutral voltage of each set is

120° phase−shifted with respect to each other, as shown in the corresponding phasor

diagram presented in Figure 2-7(b). Thus, using vector notation, the various sets can be

expressed as VT1=[A1 B1 C1]T, VT2=[A2 B2 C2]

T and VT3=[A3 B3 C3]T. It readily follows

that the phasor diagram for the vectors VT1, VT2 and VT3 is as shown if Figure 2-3(c) and

therefore this four−winding three−phase transformer can be used to generate such throws.

2n

2n1n

2n

Figure 2-7 A four−winding three phase transformer to generate three secondary vector voltages 120°

phase−shifted.

52

The major drawback of the topology introduced above is the relatively large

unused area outside the circle in Figure 2-3(c). Specifically, for a given magnitude of the

throw voltages, say VT, the maximum pole voltage that can be obtained is 2/VV TP = .

This limitation can be improved considering the topology sketched in Figure

2-8(a). The transformer in this case has five three−phase windings. The primary side

winding is ∆−connected while in the secondary side there are two windings ∆−connected

and two Y−connected. In addition, as suggested in Figure 2-8(a), the turn ratio of the

∆−connected windings is 3 times the turn ratio of the Y−connected windings. Thus,

with the phase designation given in Figure 2-8(a), it is possible to create four vector

throws phase−shifted 90° with respect to each other, as shown in the phasor diagram of

Figure 2-8(b).

3n 2

2n

2n

1n

3n 2

Figure 2-8 A five−winding three−phase transformer to generate four secondary vector voltages 90°

phase−shifted.

53

Similar to the case with three secondary windings, by defining the vector voltages

as VT1=[A1 B1 C1]T, VT2=[A2 B2 C2]

T, VT3=[A3 B3 C3]T and VT4=[A4 B4 C4]

T, it can

readily be seen that they resemble the phasor diagram shown in Figure 2-3(d). For this

topology, the maximum obtainable pole voltage is 2/VV TP = , which represents a

significant improvement with respect to the topology with three secondary windings.

In order to obtain larger useful pole voltage, other configurations with six or more

secondary winding might be developed but they lack practicality due to the large number

of windings needed.

54

Chapter 3 AC Link Power Flow

Controllers

3.1 Introduction

This chapter introduces the family of power flow controllers proposed in this

research work: the Π−controller [24], the Ξ−controller and the Γ−controller [25]. These

devices are based on the vector switching converter (VeSC) and feature similar functional

properties as some of the DC link controllers discussed Chapter 1. Specifically, as will

become evident through this chapter, there is an intimate correlation between the

Π−controller, the Ξ−controller and the Γ−controller and the HVDC intertie, the Static

Synchronous Series Compensator (SSSC) and the Unified Power Flow Controller (UPFC).

Although functionally AC link controllers are similar to their DC link counterparts,

the control function is realized by direct AC↔AC conversion without frequency change,

adopting the strategy of pulse width modulation (PWM).

As stated in Chapter 1, the HVDC intertie, the SSSC and the UPFC appeared in the

literature chronologically in that order, so in this chapter the same tendency is chosen,

introducing first the Π−controller, followed by the Ξ−controller and the Γ−controller.

55

3.2 ΠΠΠΠ−−−−Controller: An AC Link Back−−−−to−−−−Back

Intertie

DC link interties have been extensively used to interconnect AC systems

throughout the world. They feature the unique property of decoupling the dynamics of

the systems being interconnected and, as a result, they can be used to interconnect

systems operated at different frequencies. However, the most important property of these

devices is the ability to continuously and independently control the active and reactive

power flow through them. The latter property can also be achieved by using AC link

interties based on the vector switching converter, as suggested in Figure 3-1.

Figure 3-1 Schematic of a VeSC−based AC link intertie.

In this section, the details on the implementation of the vector switching converter

to function as an intertie are provided, along with computer simulation results that

validate the approach.

3.2.1 Topology

The schematic of the configuration proposed is presented in Figure 3-2. The main

56

goal is to control the power flowing across the two three−phase AC systems, namely the

sending System S and the receiving System R. As indicated in the figure, the intertie is

configured by including a phase−shifting transformer (SPT), filter capacitors (TFC), a

quadruple throw−single pole three−phase VeSC, and boost transformer (BIT).

Figure 3-2 Topology of a VeSC −based AC link intertie.

The transformer SPT has the double function of lowering the voltage to the level where

the switches can safely operate and of simultaneously phase−shifting the input voltage in

0, 90, 180 and 270° to generate four sets of three−phase voltages of equal magnitude. The

capacitor bank TFC is used to absorb the high frequency currents introduced due to

switching process from permeating into the system across the transformer. The controlled

voltage is synthesized at the poles by modulating the duty ratios d1, d2, d3, d4. Finally, the

transformer BIT located at the receiving side raises the voltage to the corresponding level

57

of the receiving end.


By following the procedure explained in Chapter 2, the single−phase averaged

equivalent circuit shown in Figure 2-3 can readily be obtained. As can be seen, the

controlled source approach has been chosen to represent the converter. In addition, the

turn ratios of transformer STP have been made complex numbers in order to reflect the

corresponding phase−shift. Notice as well that the Systems S and R have been replaced

by their Thévenin equivalent circuits. Although resistive elements are not shown in the

figure, they may be easily added to represent the power losses throughout the various

stages.

Figure 3-3 Single−Phase averaged equivalent circuit.

This equivalent circuit may be conveniently utilized to derive and study the

58

application of VeSC−based interties for AC power flow control by incorporating them in

power system load flow and dynamic analysis programs.

3.2.3 Principle of Operation

In order to understand the principle of operation, consider a purely inductive link

between the sending end system S and the receiving end system R, as indicated in Figure

3-4(a). Also, assume that the voltages VS and VR have equal magnitude, say V, and they

are displaced by a transmission angle of, say θ°.

(a) Systems S and R connected via a purely

inductive link (b) System S and R connected via an inductive link plus

the intertie.

Figure 3-4 The ideal AC link intertie.

Under these assumptions, the power flow equations are

θsinX

VP

2

= (3-1)

)θcos1(X

VQQ

2

RS −=−= (3-2)

59

Now consider a fully ideal AC link intertie i.e., both transformer SPT and BIT are

ideal and have unity turn ratio and also the reactive power injected by the capacitor bank

FTC is negligible so it may be removed. Under these assumptions, the equivalent circuit

of the intertie sketched in Figure 3-2 may be further reduced to the equivalent circuit

presented in Figure 3-4(b). The turn ratio of the transformer is given by

24134231 djd)dd(j)dd(D +=−+−= (3-3)

and reflects both the phase−shift introduced by SPT transformer as well as the action of

the converter. Now the power flow equations take the form of,

]θcosdθsind[XV

P 2413

2

+= (3-4)

)θsindθcosddd(XV

Q 2413224

213

2

S +−+= (3-5)

)1θsindθcosd(XV

Q 2413

2

R −−= (3-6)

Equations (3-4) through (3-6) along with restriction imposed by the continuity of the

converter i. e.,

1dddd 4321 =+++ (3-7)

fully described the ideal AC link intertie. Equations (3-4) through (3-6) also show that the

60

duty ratio differences d13 and d24 give two degrees of freedom that can be conveniently

chosen to control P and Q at one of the ends.

In addition, as can be seen from Figure 3-4, the equivalent circuit has two legs in

shunt that resemble the Greek letter pi, Π, so the AC link intertie can be termed

Π−controller.

Although it is strictly valid only for the ideal case, it is convenient for

visualization purposes to represent the feasible range of values for the various duty ratios

in d13d24 plane, as shown in Figure 3-5. Values inside the “unity” rhombus only are

valid for the duty ratio differences, given the restriction of non−negativity for each duty

ratio (di≥0, for i=1..4) as well as the continuity equation. In the real case, the response of

the converter also depends on 2id factors, but it is largely dominated by the duty ratio

differences, that is, a given set point P,Q is determined mostly by a duple d13, d24.

Figure 3-5 The “unity” rhombus. Permissible duty ratio values.

61

3.2.4 Control Capabilities

Although the model presented in the previous section demonstrates the control

capabilities, a more realistic model would account for the effect of the transformers as

well as the capacitor bank.

A 110kV/100MVA/60Hz case−study system was developed to explore the

performance of the intertie further. In reference to Figure 3-2, consider the system S

(modeled as a stiff voltage source of 01VS ∠= pu) is connected to the system R (modeled

as a stiff voltage source of 201VR −∠= pu) through a resistive−inductive link of

8634.0ZL ∠= pu. Thus, without the Π−controller embedded, one would measure

Ps=1pu Qs=0.1pu and PR=0.99pu QR=0.2pu at the sending and receiving end,

respectively. This will be considered as the base case for the following discussion.

Now consider the insertion of the Π−controller, say at the midpoint of the link,

splitting it into two equal impedances ( 8617.0ZZ RS ∠== pu). The turn ratio of

transformers SPT and BIT were selected to be ap=10:1 and as=1:20, respectively. Typical

values were selected for the parasitic elements of the transformers. Finally, the capacitor

bank was selected to be XC=3pu. Refer to the Design Considerations Section for further

details on the selection of these values and to the Appendix 1 for the complete list of

parameters.

Next, based on the operating point described above, various control strategies are

discussed. The attention is focused on the sending end control variables, namely, PS and

62

QS.

3.2.4.1 Active Power Control

Figure 3-6(a) and (b) show the values of d13 and d24 that must be set in order to

transmit active power in the range -2pu, 2pu shown on the horizontal axis, with zero

reactive power maintained at the sending end. Figure 3-6(c) shows the corresponding

reactive power needed at the receiving end.

-1

0

1

-1

0

1

-2 -1.5 -1 -0.5 0 0.5 1 1.5 20

0.5

1

1.5

d1 - d3

d2 - d4

QR(pu)

Figure 3-6 Variation of sets of duty ratios, (a), (b) and reactive power at receiving end, (c) as a function of active power control while Qs=0pu and θ=20°.

It can be seen that control points around PS=0pu are achieved at a high

requirement of reactive power at the other end, therefore becoming impractical.

However, that can be solved by local reactive power injection at the bus, as it is done in

some HVDC ties [13]. Although the reactive power at the sending end was set at QS=0pu

in this example, it can be set at any other reasonable value that may be desired.

63

Since the intertie can transfer power in both directions, it can be named as a

back−to−back system and the terms sending and receiving ends become interchangeable.

3.2.4.2 Reactive Power Control


regulate the reactive power at the sending end within the range -1pu, 1pu shown on the

horizontal axis, with the active power transfer fixed at PS=1.5pu. Figure 3-7(c) shows the

corresponding reactive power needed at the receiving end.

-1

0

1

-1

0

1

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-1

0

1

d1 - d3

d2 - d4

QR(pu)

Figure 3-7 Variation of sets of duty ratios, (a), (b) and reactive power at receiving end, (c) as a function of

reactive power control while PS =1.5pu and θ=20°.

As can be seen from Figure 3-7(c), the intertie can provide voltage support (QS<0

and QR>0) at both ends while keeping a fixed level of active power transfer.

64

3.2.4.3 Angle Control


keep a given transfer level while the transmission angle θ is varied within the range -

90°, 90° shown on the horizontal axis. Figure 3-8(c) shows the corresponding reactive

power needed at the receiving end. The excellent performance of the intertie as a

phase−shifting controller is evident from Figure 3-8(c). It can keep PS, QS and QR at a

fixed level for a wide transmission angle range.

-1

0

1

-1

0

1

-80 -60 -40 -20 0 20 40 60 800

0.5

1

Figure 3-8 Variation of sets of duty ratios, (a), (b) and reactive power at receiving end, (c) as a function of phase−shifting control while PS =1.5pu QS=0pu.

65

3.2.5 Design Considerations

3.2.5.1 Parameter Calculations

As a general rule, power converters need filter capacitors across the throw

terminals and filter inductors in series with the pole terminals [33]. In the Π−controller,

the pole terminals appear in series with the boost transformer SIT and the transmission

line. These elements provide enough series inductance naturally, eliminating the need for

separate filter reactors. On the other hand, at the throw terminals, filter capacitors are

needed to isolate the high frequency currents introduced due to the switching process

from propagation into the transformer SPT, and further into the system. However, as the

capacitors bank appears directly shunt−connected into the systems, it ends up playing an

undesired major role on the reactive power balance of the entire system.

Furthermore, the selection of the turn ratios of both phase shifting and boost

transformers also plays an important role in system operation. The turn ratio of the

transformer at the sending end also must be compatible with voltage levels where the

switches can safely operate. Hence, the capacitors bank and both transformer turn ratios

must be selected to simultaneously fulfill the various system requirements.

Detailed time−domain simulations showed that the capacitive reactance needs to

be less than 5pu in order to realize satisfactory system performance. With that bound, and

recognizing the operation at zero reactive power at both ends to be a desirable target

under a wide range of power flow conditions, the process of finding an acceptable set of

design parameters can be formulated as an optimization problem. By running

66

optimizations at various points within the range of active power control (-2pu to 2pu in

this case), it is possible to converge to a set of values that satisfactorily meet the system

requirements. For the system data specified in Appendix 1, XC=3pu and turn ratios

aP=0.1 and aS=20 give acceptable performance.

3.2.5.2 Feasible operating range

The full feasible operating range for the Π−controller can be obtained by mapping

the unity rhombus from Figure 3-5 into the PS−QS plane, which is sketched in Figure

3-9(a). However, this operating nomogram is only theoretical, due to the enormous

values of reactive power needed to realize some of the operating conditions. Thus, only a

subset of these operating conditions is practical. By discarding all the impractical points

(accepting a maximum of 1pu of reactive power at both ends), the operating nomogram

becomes restricted as illustrated in Figure 3-9(b). This corresponds to a subset of the

region from Figure 3-9(a). The axis of the figure has been changed to emphasize the

practical feasible region.

It can be seen that the resulting restricted operating region still provides a wide

range of controllability, with a limited variation in duty ratios, especially with low levels

of reactive power requirements, validating the proposed design process.

67

-2

0

2

4

6

-3 -2 -1 0 1 2 3-2

-1

0

1

2

Figure 3-9 Complex Power Nomogram at the sending end. (a) Entire operating range, (b) restricted and more practical operating range.

3.2.6 Simulation Results

A detailed computer simulation model of the system shown in Figure 3-2 was

developed to verify the operation of the Π−controller at various operating conditions.

The switching frequency to operate the converter was selected to be FS=2.4kHz. The base

values and per unit values of the parameters used in the computer simulation example are

shown in Appendix 1.

As an illustration, consider the base case described in the Control Capabilities

Section. It was stated that, without the Π−controller embedded, one would measure

Ps=1pu Qs=0.1pu at the sending end. Now, by inserting the Π−controller, the operating

point described by Ps=2pu Qs=0pu is selected as target, that is, the active power

transfer will be doubled while reducing to zero the requirements of reactive power. From

68

either the power nomogram or the equivalent circuit, the values for the duty ratios for this

condition are easily obtainable: d1=66%, d2=17.4%, d3=16.6%, d4=0. With these duty

ratio values, the simulation is executed, whose results are described next.

Figure 3-10 shows the terminal variables at the sending end over a 60Hz cycle.

As can be seen, the voltage and current appear approximately in−phase so the reactive

power is zero. In addition, these waveforms have been perunitized with respect to their

maximum base values, therefore it can be implied that the active power is effectively

PS=2pu, as predicted early.

Figure 3-10 Phase−A voltage and current waveforms at the sending end.

Figure 3-11 shows the same waveforms but at the receiving end. Although the

fundamental components agree with the predictions made by the equivalent circuit, the

69

main drawback of this approach becomes evident. The rich harmonics content makes the

feasibility of the Π−controller dependent upon big−sized output filters, which may be

impractical at the power level considered.

Figure 3-11 Phase−A voltage and current waveforms at the receiving end.

3.2.7 Summary

This section has introduced the Π−controller: an application of the vector

switching converter acting as a back−to−back intertie. A simplified illustration of the

system was used to demonstrate the principles of power flow control using duty ratio

modulation. Reactive power control, active power flow control and voltage phase shift

were variables identified as controllable. The capabilities of the system under different

modes of operation were demonstrated using more detailed transformer equivalent circuit

70

model. The variation of duty ratio and power flow quantities under three different

operating modes was demonstrated. The results from a computer simulation of the

system including the dynamics of the switching process were presented to validate the

approach. A brief discussion of design considerations indicates the trade−offs in the

design of converter parameters.

Although the capabilities of operation of the converter have been illustrated by

analytical methods and their feasibility has been demonstrated using computer

simulations, the power rating of the converter system and harmonics content are seen as

major limitations of the approach. Therefore, further augmentation of the approach by

embedding the converter in a shunt−series configuration such as the UPFC is seen to be

advantageous in reducing the power converter throughput in relation to the controlled

power flow. The operation of such a configuration is the subject of Section 3.4.

In addition, since with present technology this FACTS device seems impractical, it

will not be discussed further in this thesis.

3.3 ΞΞΞΞ−−−−Controller: An AC Link Series Compensator

The concept of transmission lines compensation by means of series capacitor has

its roots in elementary phasor ideas. Transmission lines have inductive reactance that can

be compensated by adding series capacitive reactance. This very simple concept has

prompted many different devices throughout the years. First, mechanically switched

fixed capacitors were installed onto transmission lines to provide a static amount of

71

reactive compensation. Then, with the development of power semiconductors, devices

such us the Thyristor Controlled Series Capacitor (TCSC) and the Static Synchronous

Series Compensator (SSSC) have been developed. The former has the ability of

continuously controlling the equivalent impedance of the line whereas the latter can

inject a variable amount of quadrature voltage into the line. Both devices though seek the

same ultimate goal of controlling the active power through the line.

In this section, yet another approach to seek the same goal is described. Using the

vector switching converter as a controller, it is possible to modulate the amount of

capacitance injected into a transmission line, as suggested in Figure 3-12.

Figure 3-12 Schematic of a VeSC−based AC link series compensator.

This device has already been introduced in the literature [34] in a slightly

different context. In this thesis, it is adapted onto the formalisms of AC link vector

switching power flow controllers.

3.3.1 Topology

Figure 3-13 shows the detailed three−phase realization of the AC link series

72

compensator. As can be seen, the double throw−single pole three−phase VeSC commutes

between a fixed capacitor bank and a short circuit node. As a result of the switching, a

controlled amount of capacitance is generated which is injected into the line via the SIT

transformer.

Figure 3-13 Topology of a VeSC−based AC link series compensator.

Notice as well that the requirements of stiff voltage at the throw side and stiff

current at the pole side are naturally given by the compensation capacitors and the

leakage inductance of the SIT transformer, respectively.



73


controlled source approach has been chosen to represent the converter. Notice as well

that the systems S and R, the transmission line impedances, and the secondary−side

impedance of the transformer (the one in series with the transmission line), have all been

aggregated into Thévenin equivalent circuits.

Figure 3-14 Single−Phase Averaged Equivalent Circuit.


application of VeSC−based AC link series capacitors for AC power flow control by

incorporating them in power system load flow and dynamic analysis programs.

74


In order to understand the principle of operation, consider the same situation as in

Section 3.2.3, repeated here for convenience. A purely inductive transmission line is

connecting the sending end system S and the receiving end system R, as indicated in

Figure 3-15(a). Also, assume that the voltages VS and VR have equal magnitude, say V,

and they are displaced by a transmission angle of, say θ°.


inductive transmission line (b) System S and R connected via a transmission line plus

an AC link compensation capacitor.

Figure 3-15 The ideal AC link series compensator.

Under these assumptions, the active power flow is given by

θsinX

VP

2

= (3-8)

Now consider the AC link series compensator is connected into transmission line

by an ideal transformer. Under this assumption, the equivalent circuit of the converter

and the SIT transformer can be combined into one as suggested in Figure 3-15(b). By

75

reflecting the capacitor into the transmission line−side of the transformer, the active

power flow equation takes the form of,

θsinXdX

VP

C2

2

−= (3-9)

where Cω/1X pC = is the 60Hz impedance of the capacitor. It becomes evident that by

modulating the duty ratio of the converter, it is possible to control the active power flow

through the transmission line.

In addition, as can be seen from 3-15(b), the equivalent circuit has two legs in

series that resemble the Greek letter xi, Ξ, so the AC link series compensator can be

termed Ξ−controller.


A 110kV/100MVA/60Hz case study system was developed to explore the

performance of the Ξ−controller further. In reference to Figure 3-13, consider the system

S (modeled as a stiff voltage source of 01VS ∠= pu) connected to the system R (modeled

as a stiff voltage source of 201VR −∠= pu) through a transmission line of

8524.0ZL ∠= pu. Thus, without the Ξ−controller embedded, the active power at the

receiving end would be PR=1.4pu. This will be considered as the base case for the

following discussion.

76

Now consider the insertion of the Ξ−controller splitting the transmission line into

impedances ( 8617.0ZS ∠= pu and 8207.0ZR ∠= pu). The turn ratio of the SIT

transformer was selected to be 1:1. Typical values were selected for the parasitic

elements of the transformer. Refer to the Appendix 2 for the complete list of parameters.

The reactance of the compensation capacitor was selected to be XC=0.05pu so it can

provide a maximum compensation of around 20% of the transmission line impedance

base value.

Figure 3-16(a) show the variation of the equivalent impedance as a function of the

duty ratio, and Figure 3-16(b) show the corresponding active power at the receiving end.

Figure 3-16 Equivalent impedance (a) and power at the receiving end (b) as a function of the duty ratio.

It can be seen that the control only becomes effective for values greater than

d=30% This is due to the quadratic nature of control action, as can be observed in

77

Equation (3-9).


As may be evident from Equation 3-9, the maximum degree of compensation is

achieved when d=100%. Therefore, this operating point determines the rating of the

various devices.

The design process starts with deciding the maximum degree of compensation for

the transmission line. This allows computation of the capacitance as,

C = 1 / (ωP ⋅ %Compensation ⋅ XL) (3-10)

where XL is the line impedance. Since for maximum compensation the capacitor appears

directly in series with the transmission line, it has to handle the transmission line

maximum current. Therefore, the voltage and kVAs can be respectively determined as,

VC=IL⋅ XC (3-11)

SC=VC⋅IL (3-12)

where IL is the maximum line current.

Finally, since the converter as well as the SIT transformer is cascaded with the

capacitor, they have to handle the same kVAs as the capacitor.

In addition, it is well known that capacitive series compensation introduces a

78

resonance between inductive reactance of the transmission line and the compensation

capacitor. The resonant frequency can be determined as

L

CPR X

XFdF ⋅⋅= (3-13)

where FP is the power frequency of the transmission system. As may be evident from the

last equation, the resonance frequency varies between zero and a maximum values as the

duty ratio is varied between zero and unity. Thus, if there exist system modes at

resonance frequencies of sustained operation, the dynamic effect should be assessed to

prevent Subsynchronous Resonances (SSR).



developed to verify the operation of the Ξ−controller at various operating conditions. The

switching frequency to operate the converter was selected to be FS=2.4kHz. The base

values and per unit values of the parameters used in the computer simulation example are

shown in Appendix 2.

Figure 3-17 shows, over a 60Hz period, the perunitized waveforms of the voltage

injected into the transmission line as well as the line current for a typical operating point.

As expected, the current leads the fundamental component of the voltage by exactly 90°

so the Ξ−controller is providing reactive power only.

79

Figure 3-17 Phase−A Current and Injected Voltage shown over a 60Hz period.

Although the voltage waveform appears to be rich in harmonics, it only represents

a small percentage of the transmission line voltage, therefore the actual phase−to−ground

as well as the phase−to−phase voltages are mostly free of harmonics.

As an illustration of the open loop dynamic performance of the Ξ−controller,

consider the transition from operating at d=20% to d=80%. Figure 3-18 and Figure 3-19

show the response of the line current and the response of the measured power at the

receiving end, when the duty ratio is stepped up or ramped up, respectively.

80

0

50

100

-2

0

2

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.30.9

1

1.1

1.2

Figure 3-18 Simulation results for a step−change of the duty ratio (a) from 20 to 80%. (b) and (c) show the

response of the line current and the power at the receiving end, respectively.

Figure 3-19 Simulation results for a ramp−change of the duty ratio (a) from 20 to 80%. (b) and (c) show the

response of the line current and the power at the receiving end, respectively.

81

It can be seen that in both cases the system is able to stabilize although in the step

case a significant overshoot is observed, suggesting that for open loop operation it would

more appropriate to slowly tune the duty ratio. Closed loop operation will be studied in

Chapter 5.

3.3.7 Summary

This section has introduced the Ξ−controller: an application of the vector

switching converter acting as a series compensator. A simplified illustration of the

system was used to demonstrate the principles of power flow control using duty ratio

modulation. It was demonstrated that, as other semiconductor−based series

compensators, the Ξ−controller can continuously adjust the transmission line impedance

and therefore realize active power control. The results from a computer simulation of the

system including the dynamics of the switching process were presented to validate the

approach. A brief discussion of design considerations indicates the trade−offs in the

design of converter parameters.

A quantitative comparison of Ξ−controller against its DC link counterpart (SSSC) is

studied in Chapter 6.

3.4 Γ−−−−Controller: An AC Link Unified Power Flow

Controller

The DC link Unified Power Flow Controller (UPFC) has been presented as the

82

ultimate solution for power flow control in transmission network. This is due to its

unique capabilities of simultaneously controlling the bus voltage and both the active and

reactive power down the line [17]. However, it has been recognized, and also realized in

practice, that the main operating mode is power flow control [17]. Bus voltage can

usually be locally controlled at the substation. It has also been agued that by controlling

the three parameters at the same time the system becomes unreliable upon the possible

loss of the UPFC. Thus, controlling two parameters at a time seems to be the most suitable

mode of operation.

The AC link counterpart of UPFC is introduced in this section. The connection into

the system, shown in Figure 3-20, is similar to the DC link UPFC but the topology as well

as the control function is realized in a different manner.

Figure 3-20 Schematic of a VeSC−based AC link Unified Power Flow Controller.

This device can also simultaneously control the active and reactive power through

a transmission line, therefore it can be thought of as a UPFC.

3.4.1 Topology

Figure 3-21 shows the detailed three−phase realization of the AC link UPFC. The

83

central feature of the approach is to control the power flow along the transmission line by

injecting an AC voltage with controllable magnitude and phase angle in series with the

line. The system is configured by including a shunt phase−shifting transformer (SPT),

filter capacitors (TFC), a quadruple−throw single−pole three−phase VeSC, and a series

injection transformer (SIT). This system may be located at any point throughout the line.

Figure 3-21 Topology of a VeSC−based AC link Unified Power Flow Controller.

The SPT transformer (with four secondary winding sets) has the double function

of lowering the impressed voltage to match the capability of the semiconductor switches

and simultaneously phase−shifting the impressed voltage by 0o, 90o, 180o and 270°

respectively, to obtain four sets of three−phase voltage vectors. This clearly resembles

84

the situation sketched in Figure 2-3(d), with (VT1−−−−VT4) representing the throws. The SPT

may be implemented as a five winding per leg three−phase transformer as indicated in

Figure 3-21, where all the set of windings that are drawn parallel are magnetically

coupled together and physically located in the same leg.

The capacitor bank TFC is used to absorb the high frequency currents introduced

due to switching from permeating into the system across the transformer.

The VeSC uses a quadruple−throw single−pole three−phase switch to synthesize a

controllable voltage at the pole terminals by modulating the duty ratios d1, d2, d3, d4.

Invoking Figure 2-3(d) again, given the throw voltages generated by the SPT, the range of

values the pole voltage can take is PP VV0 ≤≤ for the magnitude, and 360V0 P ≤∠≤ for

the phase angle, both which can be independently controlled.

Finally, the SIT transformer accommodates the voltage to an appropriate level to

be injected back in series with the transmission line and also provides the necessary

electrical isolation.

It is important to note that the stiff voltage and stiff current requirements assumed

in the previous section are given by the capacitor bank and SIT transformer leakage

inductance, respectively.

The AC link UPFC system may also be realized by using a four−winding per leg

SPT transformer instead. In this case, the throws should be generated as shown in Figure

2-3(c), which is physically obtained by the transformer illustrated in Figure 2-7. This

realization only needs triple throw−single pole switches and therefore is simpler and

easier to control; however, as is evident from Figure 2-3(c), it needs higher throw

85

voltages to synthesize the same PV .




controlled source approach has been chosen to represent the converter. Notice as well

that the systems S and R, the transmission line impedances, and the secondary−side

impedance of the transformer (the one in series with the transmission line) have all been

aggregated into the Thévenin equivalent circuit.

In addition, the turn ratios of transformer STP have been made complex numbers

in order to reflect the phase−shift introduced. Although resistive elements are not shown

in the figure, they may be easily added to represent the power losses throughout the

various stages.


application of VeSC−based AC link UPFC power flow control by incorporating them in

power system load flow and dynamic analysis programs.

86

Figure 3-22 Single−Phase Averaged Equivalent Circuit.


In order to understand the principle of operation, consider the same situation as in

Sections 3.2.3 and 3.3.3, repeated here for convenience. A purely inductive transmission

line is connecting the sending end system S and the receiving end system R, as indicated

in Figure 3-23(a). Also, assume that the voltages VS and VR have equal magnitude, say

V, and they are displaced by a transmission angle of, say θ°. Thus, the active and reactive

87

power flows through the transmission line are, respectively

θsinX

VP

2

= (3-14)

)θcos1(X

VQQ

2

RS −=−= (3-15)

Consider now the insertion of the AC link UPFC at the sending end of the line. In

order to limit the discussion to the principle of operation, assume that transformers SPT

and SIT are ideal and have a unity transformation ratio. Furthermore, assume that the

reactive power injection at the fundamental frequency due to the bank TFC is negligible

so it may be removed.

Under these assumptions, the single−phase equivalent circuit for the system as

shown in Figure 3-23(b) can be readily obtained following the standard procedure

described in Chapter 2.


inductive transmission line (b) System S and R connected via a transmission line plus

an AC link Unified Power Flow Controller.

Figure 3-23 The ideal AC link Unified Power Flow Controller.

88

The transformation ratio of the SPT transformer becomes, as in the case of the

Π−controller, a complex quantity that may be represented as

24134231 djd)dd(j)dd(D +=−+−= (3-16)

reflecting the simultaneous phase−shifting introduced by the SPT. Furthermore, in order

to satisfy the continuity of switched variables of the VeSC, the duty ratio components

must satisfy

1dddd 4321 =+++ (3-17)

The power flow equations now take the form of,

]θcosdθsindθ[sinX

VP 2413

2

−−= (3-18)

]θsinddd2θcosddθcos1[X

VQ 24

2241313

213

2

S −+−++−= (3-19)

]θsindθcosd1θ[cosX

VQ 2413

2

R +−−= (3-20)

Equations (3-18) through (3-20), along with (3-16)−(3-17) dictate the control

capabilities of the ideal AC link unified power flow controller. It can be seen that, by

choosing appropriate values for d13 and d24, it is possible to control either (P,QS) or

(P,QR), that is, it can independently control the active power and reactive power at either

end of the transmission line. In addition, for a given (P,Q) operating point, it can keep

89

such a point unchanged as the angle θ varies i.e., it has phase−shifting capabilities, or as

the voltage V varies i.e., it also has tap−changer capabilities. Altogether, these

capabilities are comparable to that of the DC link UPFC.

Since the embedded transformer shown in Figure 3-23(b) has a leading shunt leg

followed by a series leg coupled to it, the schematic has the appearance of the uppercase

Greek letter gamma, Γ, so this particular interconnection may be termed Γ−controller.


A 110kV/100MVA/60Hz case study system was developed to explore the

performance of the Γ−controller further. In reference to Figure 3-21, consider the system

S (modeled as a stiff voltage source of 01VS ∠= pu) connected to the system R (modeled

as a stiff voltage source of 201VR −∠= pu) through a transmission line of

8524.0ZL ∠= pu. Thus, without the Γ−controller embedded, the active and reactive

power at the receiving end would be PR=1.4pu and QR=−0.36pu, respectively. This will

be considered as the base case for the following discussion.

Now consider the insertion of the Γ−controller splitting the transmission line into

two impedances ( 8207.0ZS ∠= pu and 8617.0ZR ∠= pu). The turn ratios of the SPT

and SIT transformers was selected to be 2:10 and 1:1, respectively. Typical values were

selected for the parasitic elements of each transformer. Finally, the capacitor bank was

selected to be XC=3pu. Refer to the Design Considerations Section for further details on

90

the selection of these values and to the Appendix 3 for the complete list of parameters.

Next, based on the operating point described above, various control strategies are

discussed. The attention will be focused on the receiving end control variables, namely,

PR and QR. The discussion that follows will be based on the d13−d14 plane, with the

variables of interest implicitly displayed. This is in contrast with the Control Capabilities

Section for the Π−controller, where similar information was generated but with the

controlled variables explicitly displayed.

3.4.4.1 Transmitted Power Control

Figure 3-24 shows the operating plane of d13 and d14. Similar to Figure 3-5, the

unity rhombus represents the operating boundaries in d13 and d24 that are realizable given

the restrictions for each duty ratio. The three lines that are drawn inside the unity

rhombus representing the loci of d13 and d24 that must be set in order to independently

control a particular quantity as labeled. These lines take into account operating

constraints of the design posed by the turn ratios of the transformers, size of the

capacitor, voltage ratings of the different elements, etc.

91

25.0Q,95.0P maxR

minR −==

50.0Q,90.1P minR

maxR −==

01.1PminR =

83.1PmaxR =

17.0QmaxR =

81.0QminR −=

20=θ

Figure 3-24 Receiving−end power control.

Thus, the line labeled as “Active Power” shows that the Γ−controller can vary PR

in the range [1.01, 1.83] while keeping the rest of the parameters from the base case

unchanged. Similarly, the line labeled as “Reactive Power” shows that the Γ−controller

can vary QR in the range [-0.81, 0.17] while keeping the rest of the parameters from the

base case unchanged. Furthermore, the line labeled “Both”, shows that it is possible to

simultaneously control both the active and reactive power in such a way that the power

factor (pf) at the receiving end remains constant.

3.4.4.2 Tap−−−−changing/phase−−−−shifting control

Often during system operation, it may be desirable to deliver constant active and

92

reactive power at the receiving end, while the system operating conditions (VS, VR or θ)

may vary. Figure 3-25 shows the values of d13 and d24 that must be set in order to deliver

constant active and reactive power while either VS, VR or θ are changing within the

specified range.

88.0VminS =

12.1VmaxS =

91.0VminR =

12.1VmaxR =

14min =θ

27max =θ20=θ

Figure 3-25 Tap−changing, phase−shifting control.

The line labeled as “Sending End Voltage” shows that the Γ−controller can

maintain base operating conditions while VS varies in the range [0.88, 1.12]. Similarly,

the line labeled as “Receiving End Voltage” shows that the Γ−controller can maintain

base operating conditions while VR varies in the range [0.91, 1.12]. Furthermore, the line

labeled “Transmission Angle,” shows that it is possible to simultaneously hold the active

and reactive power received steady as the transmission angle θ varies in the range [14o,

27o].

93


The major circuit parameters that need to be selected are the transformer

turn−ratios, filter capacitors, and switching frequency.

3.4.5.1 Transformers turn ratio

The main criteria driving the selection for the transformer turn ratios are the

desired maximum voltage to be injected into the line and the voltage level at which the

switches can safely operate. The former can be expressed as 2/VaaV LSPP = , where aP,

aS and VL are the SPT and SIT transformer turn ratios and the transmission line rated

voltage, respectively. For the latter, the restriction is that aPVL<VB, where VB is the

voltage−withstand capability of the switch. For the particular case studied here,

10/2a P = and 1a S = are selected.

3.4.5.2 Filter Capacitors / Switching Frequency

As a general rule, switching power converters need filter capacitors across the

throw terminals and filter inductors in series with the pole terminals. In the Γ−controller,

the pole terminals appear in series with the injection transformer SIT and the transmission

line. These elements provide enough series inductance naturally, eliminating the need for

separate filter reactors. However, at the throw terminals, filter capacitors are necessary to

isolate the high frequency currents introduced due to the switching process from

propagation into the SPT transformer and further into the system.

These capacitors also introduce resonances into the system (three different in this

94

case) so the capacitance needs to be carefully selected in order to obtain satisfactory

performance.

Figure 3-26 shows the variations of these resonance frequencies ( 1RF , 2

RF and 3RF )

as a function of the capacitance. For each value considered for the capacitance, the

resonance frequency for all possible values of the various duty ratios is computed. Thus,

each entry in the scatter graph actually consists of a cluster of points. The resonance

frequency 1RF (= CLπ2/1 PS ) is independent of the duty ratios. 2

RF has some dependence

on the duty ratios but is largely dominated by the term CLπ2/1 PS , as may be evident

from the figure. However, 3RF results from the interaction between the capacitor and the

rest of the system and is more sensitive to the duty ratios, as shown in the expanded plot

in Figure 3-26, for a particular capacitance value.

0 50 100 150 200 2500

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

109 110 340

345

350

355

360

365

370

375

3RF

1RF

2RF 3

RF

Figure 3-26 Resonance frequency as a function of the capacitor value.

95

On the other hand, the switching process introduces harmonics into the system

with frequency of the form PS FnF ± (n=1,2,…∞), where FS and FP are the switching and

power frequency, respectively [33, 35]. All of these frequencies must far exceed the

resonances of the system in order to avoid excitation of such frequencies. Clearly the

critical case is when n=1. Thus, since normally FP<<FS, it is sufficient to show that FS

exceed the various resonances.

As can be seen from Figure 3-26, this issue may be readily solved by choosing a

large capacitance or a high switching frequency. However, neither of these solutions

comes at low cost. A high switching frequency implies high switching losses whereas a

large capacitance results in large physical size and reactive power circulation. Thus, the

selection of the capacitor and switching frequency involves a difficult trade−off. For the

particular case studied here, we select C=73µF and FS=2.4kHz, which provides sufficient

operating margin, as indicated in the figure.



developed to verify the operation of the Γ−controller embedded in a transmission system

at various operating conditions. The complete set of parameters used in the computer

simulation is shown in Appendix 3.

The first case−study chosen for the simulation corresponds to moving from the

base case stated in Control Capabilities Section i. e., PR=1.4pu and QR=−0.36pu, to a

96

new operating point given by PR=1.5pu and QR=0. This condition is achieved by setting

the duty ratios to d1=0, d2=18%, d3=57% and d4=25%. Figure 3-27 shows, over a 60Hz

period, the voltage/current waveforms at the receiving−end perunitized with respect to

their maximum base value. It can be seen that the voltage and current waveforms are

in−phase so QR=0 and the maximum values match the set point for 1.5pu active power

(vR=1pu, iR=1.5pu).

0.25 0.255 0.26 0.265 0.27 0.275 0.28-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

Figure 3-27 Phase−A Voltage and Current at the receiving−end.

Figure 3-28 and Figure 3-29 show the internal workings of the converter. Figure

3-28 shows, over a 60Hz period, the switch SA (refer to Figure 3-21 and Figure 3-22)

throw voltages. As can be seen, they are 90° phase−shifted as predicted early. On the

97

other hand, Figure 3-29 shows the currents through the various terminal of phase−A SPT

transformer. As can be seen, although the SPT secondary currents (ips(1-4)) are rich in

harmonics, the actual current absorbed from the transmission line (isht) is fairly

sinusoidal.

-1

0

1

-1

0

1

-1

0

1

0.25 0.255 0.26 0.265 0.27 0.275 0.28

-1

0

1

Figure 3-28 Phase−A Capacitor voltages.

98

-1

0

1

-1

0

1

-1

0

1

-1

0

1

0.25 0.255 0.26 0.265 0.27 0.275 0.28

-1

0

1

Figure 3-29 Phase−A SPT transformer currents.

A second case study was developed to evaluate the open−loop dynamic response

of the Γ−controller upon a change on the commanded duty ratios. The transition studied

is a change on an operating point given by PS=1.2pu and QS=0.2pu to a different one

given by PS=1.5pu and QS=0pu. Two different simulations are carried out. First, the duty

ratios are directly stepped to achieve the new operating point. Second, the duty ratios are

ramped, within a 100ms interval, to smoothly move to the new operating point.

Results for the step−change case are presented in Figure 3-30 and Figure 3-31.

The former shows the commanded duty ratios whereas the latter shows the response of

the line current, the active power, and the reactive power. As can be seen, the response is

as a second−order system. Power oscillations take place, which are damped out after

approximately seven 60Hz cycles.

99

0

20

40

20

30

40

20

40

60

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3

0

10

20

30

Figure 3-30 Duty Ratio Commands. Stepped from d1=33%, d2=35%, d3=32% d4=0% to d1=0%, d2=18%, d3=57% d4=25%.

-1

0

1

1

1.2

1.4

1.6

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3

-0.2

-0.1

0

0.1

Figure 3-31 Response to a duty ratio step change of the (a) line current, (b) active power and (c) reactive power, all at the receiving end.

100

Results for the ramp−change case are presented in Figure 3-32 and Figure 3-33.

The former shows the commanded duty ratios whereas the latter shows the response of

the line current, the active power, and the reactive power. As can be seen, the transition is

free of oscillation, which makes the ramping strategy very attractive to be selected to

actually operate the Γ−controller.

0

20

40

20

30

40

20

40

60

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3

0

10

20

30

Figure 3-32 Duty Ratio Commands. Ramped from d1=33%, d2=35%, d3=32% d4=0% to d1=0%, d2=18%, d3=57% d4=25%.

101

-1

0

1

1

1.2

1.4

1.6

0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3

-0.2

-0.1

0

0.1

Figure 3-33 Response to a duty ratio ramp change of the (a) line current, (b) active power and (c) reactive

power, all at the receiving end.

3.4.7 Summary

This section has introduced the Γ−controller: an application of the vector

switching converter acting as a unified power flow controller. It is capable of

independently controlling the active and reactive power flow along a transmission line.

The system consists of a multiple quadrature phase−shifting transformer operated in

conjunction with multiple−throw three−phase switches, which are pulse width modulated

to synthesize an adjustable voltage that is injected in series into the line.

The capabilities of the Γ−controller under different modes of operation have been

demonstrated using a detailed transformer equivalent circuit model. The results from a

computer simulation of the system, including the dynamics of the switching process,

have been presented to validate the approach. A brief discussion of design considerations

102

indicates the trade−offs in the design of converter parameters.

The Γ−controller can be considered to be the AC link counterpart of the more

classical UPFC system based on DC link voltage source converters (VSC). It is based on the

well−established technology of classical phase−shifting transformers with solid−state

electronic control using pulse width modulation. While the control capabilities of both

approaches are similar as has been illustrated in this chapter, they utilize entirely different

topological structures for the realization of the function. The DC link based approach

utilizes well−established multipulse/multilevel VSC technologies with advanced high

voltage, high current power semiconductor switching devices such as the gate turn−off

thyristor with modest switching speeds. The integration of the multipulse VSC converters

to realize high quality waveforms requires the use of multiple phase−shifting

transformers. On the other hand, the AC link VeSC−based approach utilizes gate turn−off

switch technology as well but is operated under pulse width modulation at reasonably

high switching frequencies. Furthermore, it also utilizes multiple phase−shifting

transformers to realize the topological functionality. While it can be shown that the

throughput ratings of the power converters used in both the approaches will be identical,

given identical range of operation and control capabilities, their cost, size and complexity

involve complex trade−offs that are unclear at first glance. A more detailed comparison

of the converter design aspects and their dynamic capabilities will reveal further

trade−offs between the two approaches, which is proposed as one of the future research

paths in Chapter 9.

103

Chapter 4 Dynamic Modeling of AC

Link Power Flow Controllers

4.1 Introduction

Dynamic modeling of vector switching converters can be performed based on

traditional state space averaging techniques to predict performance at power frequencies.

Using the equivalent circuits developed in Section 2.2.2, the dynamic phasors’ state

space model can readily be obtained [8, 36-39]. While this approach provides results

acceptable for the development of load flow models, it falls short in providing

design−oriented information for the realization of these systems, particularly with respect

to the sensitivity of circuit parameters. The main reason for this is that the switching

frequencies attainable with these converters are only a small multiple of the power

frequency, due to the high levels of power throughput involved in relation to the power

capability of switching semiconductors. Therefore, the dynamic phenomena are often

overwhelmed by interactions between power frequency, switching frequency and the

natural modes inherent in the network structure. Thus, refinements to the classical state

space averaging techniques are necessary to obtain better models for the system.

Generalized averaging theory based on Fourier techniques have been developed to study

switching frequency dynamics for DC−DC converters [40-44]. The goal of this chapter is

104

to extend generalized averaging tools for AC link power flow controllers to predict

system behavior with fidelity that extends up to the switching frequency [35].

4.2 Generalized Averaging Theory

Generalized averaging theory has its roots [44] in the fact that a periodic signal

)(x τ can be represented to an arbitrary accuracy on the interval ]t,Tt[ −∈τ using Fourier

series as

∑∞

−∞=

τω⟩⟨=τk

kjk e)t(x)(x (4-1)

where T/2π=ω is the corresponding frequency and )t(x k⟩⟨ is the thk Fourier

coefficient, also referred to as the thk phasor or the index k average, given by:

∫−

τω− ττ=⟩⟨t

Tt

kjk de)(x

T

1)t(x (4-2)

Notice that these Fourier coefficients are function of time as the interval ]t,Tt[ −

slides over the actual waveform. The aim is to determine an appropriate state space

model in which the coefficients given by Equation (4-2) are the state variables.

105

These coefficients feature the properties listed below, which are key for applying

averaging theory to describe the dynamic behavior of vector switching converters.

4.2.1 Index symmetry

When )t(x is a real−valued waveform, it readily follows from Equation (4-2) that

)t(x)t(x *kk ⟩⟨=⟩⟨ − (4-3)

where *⟨⋅⟩ stands for the complex conjugate of ⟨⋅⟩ .

4.2.2 Reconstruction

It can be shown using Equation (4-1) that the reconstruction formula takes the

form of

∑∞

=

ωττ⟩⟨−ωττ⟩⟨+τ⟩⟨=τ1k

Imk

Rek0 )]ksin()(x)kcos()(x[2)(x)(x (4-4)

where the super indices Re⟨⋅⟩ and Im⟨⋅⟩ stand for real and imaginary components of ⟨⋅⟩ ,

respectively.

106

4.2.3 Derivative with respect to time

Differentiating Equation (4-1) yields the following formula to express the

derivative of the kth phasor with respect to time

)t(xdt

d)t(xkj)t(x

dt

dkkk ⟩⟨+⟩⟨ω−=⟩⟨ (4-5)

4.2.4 Average of a product

Using Equation (4-1), the index k average of a product can be expressed by

means of the following discrete convolution relationship

∑∞

−∞=− ⟩⟨⟩⟨=⟩⟨

iiikk )t(y)t(x)t(yx (4-6)

4.3 Dynamics for electric elements

As will become evident in the next section, the index k dynamics for the

various elements present in electric power systems are needed to develop the state space

models using generalized averaging theory. Next, the index k dynamics for resistors,

inductors and capacitors are developed.

107

4.3.1 Resistor

The equation that governs the dynamic of a resistive element is the well−known

Ohm’s Law,

)t(iR)t(v ⋅= (4-7)

Averaging both sides of Equation (4-7) and since averaging is a linear operator, it

readily follows that the index k dynamics for a resistor is,

)t(iR)t(v kk ⟩⟨⋅=⟩⟨ (4-8)

4.3.2 Inductor

Voltage and current are related in an inductor through Faraday’s Law as,

dt

)t(diL)t(v ⋅= (4-9)

Averaging the above equation and using Equation (4-5) the index k dynamics

for an inductor becomes,

)t(ikLωj)t(idt

dL)t(v kkk ⟩⟨+⟩⟨=⟩⟨ (4-10)

108

4.3.3 Capacitor

The terminal current−voltage relationship for a capacitive element is,

dt

)t(dvC)t(i ⋅= (4-11)

With a similar argument as in the inductor case, the index k dynamics for a

capacitor becomes,

)t(vkCωj)t(vdt

dC)t(i kkk ⟩⟨+⟩⟨=⟩⟨ (4-12)

4.4 Application to State Space Models for Vector

Switching Converters

Vector switching converters realize power flow control synthesizing a desirable

pole voltage obtained by switching among stiff−voltage throws. The requirements of

stiff voltage at the throw side and stiff current at the pole side are obtained by

respectively adding capacitors and inductors. The switch itself is modeled by means of

controlled sources, where the switching function q(t) takes the discrete values of 0,1 at

a switching frequency, say FS, depending on the position of the switch. Furthermore,

109

vector switching power flow controllers are embedded in power systems excited by

sinusoidal voltage sources at a power frequency, say FP. This is schematically described

in Figure 4-1.

Figure 4-1 Schematic of a generic power system with a vector switching converter embedded.

The development of the state space model shows that the differential equation that

governs the system has the form of

)t(Bu)t(x))t(q(A)t(xdt

d+= (4-13)

where the state vector, x(t), corresponds to a collection of capacitor voltages and inductor

currents, and the input vector, u(t), corresponds to a collection of excitation voltages.

Notice that the Linear Time Variant (LTV) system described by Equation (4-13) has no

approximations whatsoever i.e., q(t) represents the true switching function and the

excitation voltages embedded in u(t) are the sinusoidal waveforms. Due to the discrete

nature of q(t), the exact determination of the states from Equation (4-13) in an extremely

difficult problem.

The classical approach has been to, under proper assumptions, directly replace the

110

switching function q(t) by the duty ratio d(t). This makes the system described by

Equation (4-13) continuous and therefore solvable. The key underlying assumption for

this is that the switching frequency should exceed both the power frequency and the

natural modes of the physical system. Under these conditions, the ripple becomes

negligible and the response of the states is largely dominated by the interaction between

the DC component of the switching function (i.e., the duty ratio) and the excitation

frequency quantities. Indeed, the response becomes independent of the switching

frequency.

However, in the case of vector switching converters, this assumption may not

always be satisfied. Switching at high frequency may not be possible due to the inherent

switching losses. Thus, the need for a more refined method becomes evident.

Generalized averaging provides the framework in which the dynamic modeling

for vector switching power flow controllers can be achieved at an arbitrary accuracy.

Thus, the analysis, component sizing, and control design can be performed with a greater

degree of accuracy.

To apply the generalized averaging scheme to a system described by Equation (4-

13), it is necessary that the system have a unique identifiable period. In the state equation

presented above, however, there are two different periods: the power period TP associated

with ve(t) and the switching period TS associated with q(t). Therefore, averaging would

not be applicable if TP and TS were arbitrarily chosen. However, that limitation can be

overcome if the analysis is restricted to the special case when the ratio power

period/switching period is an integer number, say N, because then the switching function

111

is also TP−periodic.

Averaging (4-13), the index k differential equation takes the form of

kk )t(Bu)t(x))t(q(A)t(xdt

d⟩+⟨=⟩⟨ (4-14)

Using the fact that averaging is a linear operator and also using (4-5), the equation

above can be further reduced to

kkkk )t(uB)t(x)t(q'A)t(xkj)t(xdt

d⟩⟨+⟩⟨+⟩⟨ω−=⟩⟨ (4-15)

where A’ can readily be deduced from A(q(t)). The simplifying task now becomes the

representation of k)t(x)t(q ⟩⟨ in Equation (4-15) to a summation of various terms at

distinct frequencies using the convolution property (4-6). Therefore, it is first necessary

to develop expressions for q(t) and x(t) in terms of their corresponding phasors.

As stated earlier, q(t) is a TS−periodic function so in terms of the power period

(TP=N⋅TS) it can be expressed as

∑∞

−∞=

⟩⟨=k

tωNkjNk

pe)t(q)t(q (4-16)

Expanding this series,

112

∑∞

−≠−∞=

−− ⟩⟨+⟩⟨+⟩⟨+⟩⟨=

1,1,0kk

tωNkjNk

tωNjN

tωNjN0

pPp eqeqeqq)t(q (4-17)

Notice that the time dependency for the phasor quantities has been dropped to

avoid notational clutter. Since the interest is to capture phenomena at switching

frequency, the switching function is approximated by its three first terms. Therefore,

Equation (4-17) becomes

tNjN

tNjN0

pp eqeqq)t(q ω−

ω ⟩⟨+⟩⟨+⟩⟨≈ (4-18)

Conceptually this corresponds to augmenting the switching function

representation by including the fundamental component in addition to the traditional

representation of the duty ratio only, as suggested in Figure 4-2, shown for the particular

case of d=50%. This allows capture of the high frequency (ripple) dynamics in the state

space model.

113

Figure 4-2 Waveforms corresponding to the switching function, index 0 approximation (duty

ratio) and index 0, -N, N approximation. All with d=50%.

On the other hand, it is known that x(t) is a TP−periodic function but its

harmonics content is not known a−priori. Therefore, it will be assumed that the

harmonics are all present, i.e.,

∑∞

−∞=

><=k

tωkjk

pex)t(x (4-19)

Now it is possible to apply Equation (4-6) to obtain the various index averages

that result from the product k)t(x)t(q ⟩⟨ ,

114

)1N(N)1N(N101 xqxqxqxq −−+− ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨=⟩⟨ (4-20)

1N1N01N xqxqqx −−− ⟩⟨⟩⟨+⟩⟨⟩⟨=⟩⟨ (4-21)

1N1N01N xqxqxq ⟩⟨⟩⟨+⟩⟨⟩⟨=⟩⟨ ++ (4-22)

)1N(N1NN101 xqxqxqxq +−−−−− ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨=⟩⟨ (4-23)

1N)1N(0)1N( xqxqxq ⟩⟨⟩⟨+⟩⟨⟩⟨=⟩⟨ −−−−− (4-24)

1N)1N(0)1N( xqxqqx −−+−+− ⟩⟨⟩⟨+⟩⟨⟩⟨=⟩⟨ (4-25)

g0g xqqx ⟩⟨⟩⟨=⟩⟨ g ≠ ±1, ±(N-1), ± (N+1) (4-26)

In order to exploit certain properties, the various indices presented above are

grouped into (a) positive group: index 1, (N-1), (N+1); (b) negative group: index -1, -

(N-1), -(N+1); and (c) zero group: index g.

The above equations can be notably simplified by examining the nature of the

excitation functions. Although the excitation frequency is always ωP (usually 2π⋅60Hz),

the actual excitation index can take two different forms, as discussed next.

4.4.1 Real Excitation

When the three−phase system is balanced and no phase shifts are introduced by

transformers (resulting from a ∆−Y connection, for example), the equivalent circuit may

be represented by only one of the three−phases (usually phase A). The other two phases

carry no extra information as they are just a phase−shifted repetition of phase A. Hence,

115

for a three−phase system given by

)θtωsin(V2)t(V PA += (4-28)

)120θtωsin(V2)t(V PB −+= (4-29)

)120θtωsin(V2)t(V PC ++= (4-30)

the excitation in the single−phase equivalent circuit takes the form of,

)θtωsin(V2)t(u P += (4-31)

In terms of the average index, u(t) can be expressed as

∑∞

−∞=

−−⟩⟨+⟩⟨=⟩⟨=

k

tωj1

tωj1

tωkjk

ppp eueue)t(u)t(u (4-32)

where,

)θcosjθ(sin2

Vu 1 ⋅−=⟩⟨ (4-33)

)θcosjθ(sin2

Vu 1 ⋅+=⟩⟨ − (4-34)

116

Notice that since u(t) is a real−valued waveform, *11 uu ⟩⟨=⟩⟨ − . Thus, considering

the expression for the index products and the series expansions for the excitation

waveforms, the averaged dynamics given by Equation (4-15) becomes

1)1N(N)1N(N101P1 uBxqxqxq'Axωjxdt

d⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨−=⟩⟨ −−+− (4-35)

xqxq'Ax)1N(ωjxdt

d1N1N01NP1N −−−− ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨−−=⟩⟨ (4-36)

xqxq'Ax)1N(ωjxdt

d1N1N01NP1N ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨+−=⟩⟨ +++ (4-37)

1)1N(N1NN101P1 uBxqxqxq'Axωjxdt

d−+−−−−−− ⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨=⟩⟨ (4-38)

xqxq'Ax)1N(ωjxdt

d1N)1N(0)1N(P)1N( ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨−=⟩⟨ −−−−−−− (4-39)

xqxq'Ax)1N(ωjxdt

d1N)1N(0)1N(P)1N( −−+−+−+− ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨+=⟩⟨ (4-40)

xq'Axgωj)t(xdt

dg0gPg ⟩⟨⟩⟨+⟩⟨−=⟩⟨ g ≠ ±1, ±(N-1), ± (N+1) (4-41)

The examination of Equations (4-35) through (4-41) brings to the discussion two

important conclusions:

(i) Since the excitation is at index -1, 1 only, the state variables from the zero

group have no forcing function and therefore do not exist whatsoever, assuming

no initial condition at those indices. Therefore, Equation (4-41) can be eliminated,

117

as it bears no information.

(ii) Since the input signals are real−valued waveforms, positive−index variables are

the complex conjugate of the corresponding negative−index variable, therefore it

is possible to solve the positive group or the negative group independently of each

other. Moreover, each of them gives a closed−form solution for the state variables

and therefore can be used to predict the dynamic behavior of the entire system.

Therefore, the initially infinite number of averaged differential equations

described by (4-15) has been reduced to three differential equations, namely Equations

(4-35) through (4-37). Notice the final number of variables is (two) x (three) x (number

of original states). Each original state is augmented by three

( )t(x),t(x),t(x)t(x 1N1N1 +− ⟩⟨⟩⟨⟩⟨→ ) and by two after separating in real and imaginary

parts each complex index variable. These equations, as mention before, described the

dynamics of a phase−shift free balanced power systems with vector switching power

flow controllers embedded.

4.4.2 Complex Excitation

In the case of a power system with phase−shifting elements, it is necessary to

generalize the notion of the single−phase equivalent circuit introduced in the previous

section. For example, as discussed in Section 2.3, for the case of multiple secondary

transformers, the desired 90° phase−shift on the secondary side voltage VA2 was obtained

118

by designating as phase A the corresponding primary side voltage VBC. The notion of

complex state vectors [38] fits perfectly in this framework as complex vectors carry the

information concerning the three phases simultaneously. Complex vectors are defined as

))t(xγ)t(xγ)t(x(3

2)t(x CBAV

∗++= (4-42)

where 3

π2jeγ = . The real and imaginary parts of the space vector are equal to the α and β

components when the three−phase quantities are transformed to the Clarke’s αβ

stationary reference frame [45]. For balanced systems, there is a simple inverse

transformation,

))t(xRe()t(x VA = ))t(xγRe()t(x V*

B = ))t(xγRe()t(x VC = (4-43)

Applying this transformation to the set of balanced voltages described by Equations (4-

28)

through (4-30), the state vector for the excitation voltages becomes

))θtωcos(j)θtω(sin(V2)t(u PP +⋅−+= (4-44)

In terms of the average index, u(t) can be expressed as

119

∑∞

−∞=

⟩⟨=⟩⟨=k

tωj1

tωkjk

pp eue)t(u)t(u (4-45)

where,

)θcosjθ(sinV2u 1 ⋅−=⟩⟨ (4-46)

Notice that in contrast with the previous case, now the only excitation index is 1. Thus,

considering the expression for the index products and the series expansions for the

excitation waveforms, the averaged dynamics given by Equation (4-15) becomes

1)1N(N)1N(N101P1 uBxqxqxq'Axωjxdt

d⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨−=⟩⟨ −−+− (4-47)

xqxq'Ax)1N(ωjxdt

d1N1N01NP1N −−−− ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨−−=⟩⟨ (4-48)

xqxq'Ax)1N(ωjxdt

d1N1N01NP1N ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨+−=⟩⟨ +++ (4-49)

xqxqxq'Axωjxdt

d)1N(N1NN101P1 +−−−−−− ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨=⟩⟨ (4-50)

xqxq'Ax)1N(ωjxdt

d1N)1N(0)1N(P)1N( ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨−=⟩⟨ −−−−−−− (4-51)

xqxq'Ax)1N(ωjxdt

d1N)1N(0)1N(P)1N( −−+−+−+− ⟩⟨⟩⟨+⟩⟨⟩⟨+⟩⟨+=⟩⟨ (4-52)

xq'Axgωj)t(xdt

dg0gPg ⟩⟨⟩⟨+⟩⟨−=⟩⟨ g ≠ ±1, ±(N-1), ± (N+1) (4-53)

120

As in the case with real excitation, the examination of Equations (4-47) through

(4-53) brings to the discussion two important conclusions:

(i) Since the excitation is at index 1 only, the state variables from the zero group

have no forcing function and therefore do not exist whatsoever, assuming no

initial condition at those indices. Therefore, Equation (4-53) can be eliminated, as

it bears no information.

(ii) Since the only equation that exhibits excitation is (4-47), the indices present on

that equation 1, N+1, -(N-1) represent the corresponding state variables that are

different than zero. Thus, Equations (4-48), (4-50) and (4-52) may also be

eliminated, as they have no forcing function on the RHS.

Therefore, the initially infinite number of averaged differential equations

described by (4-15) has been reduced to three differential equations, namely Equations

(4-47), (4-49) and (4-51). As in the case of the real excitation, the final count for

variables is (two) x (three) x (Number of original states). These equations described the

dynamics of a balanced power systems with vector switching power flow controllers

embedded.

Since this is a generalization of the case with real excitation, it should be noted

that the vector space approach may also be used in the case of a power system fully

Y−connected. The final time−domain waveforms should be identical.

The augmented schemes developed above have the advantage of incorporating the

121

ripple into the model and therefore could be used for design purposes in the sense that the

predicted RMS quantities give a better approximation of the actual stress that the various

devices will have to tolerate.

Also, closed−loop regulators that are switching frequency dependent can be

designed and therefore capture phenomena that are out of reach with the traditional

approach of approximating the switching function by the duty ratio only.

Finally, note that when approximating the switching function by the duty ratio

only, the traditional state space in terms of dynamic phasors is recovered. This will

become evident in the following examples. The number of variables in this case is (two)

x (number of original states).

4.5 Case Studies

In this section the techniques of generalized averaging are applied to the modeling

of the Ξ−controller and the Γ−controller. In the Ξ−controller case, the advantages

towards the design process are investigated, whereas in the Γ−controller case the

attention is focused on the dynamic performance.

4.5.1 Generalized Averaging Applied to the ΞΞΞΞ−−−−controller

4.5.1.1 The Model

In order to develop the generalized averaged model, consider the equivalent

122

circuit for Ξ−controller presented in Figure 3-14, but now the converter is modeled

directly using the switching function rather that the duty ratio. As usual, the switching

function q(t) takes values 0,1 according to a switching frequency FS (or ωS) and a duty

ratio d. This is shown in Figure 4-3.

Figure 4-3 Exact model for the Ξ−controller.

Let the sending end voltage and receiving end voltage be represented as

)tωsin(V2)t(v PS = and )θtωsin(V2)t(v PR += , respectively. Considering i(t) and

v(t) as state variables, the instantaneous state equation takes the form of

)t(v0L

1

)t(v

)t(i

0C

)t(qL

)t(q

L

R

)t(v

)t(i

dt

dSR

+

−−=

(4-54)

123

where RS RRR += , TRS LLLL ++= and )t(v)t(v)t(v RSSR −= .

Since this is a phase−shifting free system, the rules developed for real excitation

apply. Hence, the generalized averaged state space model becomes

1SR*1N

N1N

*N

10

1p1 vL

1v

L

qv

L

qv

L

qi)

L

Rωj(i

dt

d⟩⟨+⟩⟨

⟩⟨−⟩⟨

⟩⟨−⟩⟨

⟩⟨−⟩⟨−−=⟩⟨ −+

(4-55)

*1

N1N

01Np1N v

L

qv

L

qi)

L

R)1N(ωj(i

dt

d⟩⟨

⟩⟨−⟩⟨

⟩⟨−⟩⟨−−−=⟩⟨ −−−

(4-56)

1N

1N0

1Np1N vL

qv

L

qi)

L

R)1N(ωj(i

dt

d⟩⟨

⟩⟨−⟩⟨

⟩⟨−⟩⟨−+−=⟩⟨ +++

(4-57)

*1N

N1N

*N

10

1p1 iC

qi

C

qi

C

qvωjv

dt

d−+ ⟩⟨

⟩⟨+⟩⟨

⟩⟨+⟩⟨

⟩⟨+⟩⟨−=⟩⟨

(4-58)

*1

N1N

01Np1N i

C

qi

C

qv)1N(ωjv

dt

d⟩⟨

⟩⟨+⟩⟨

⟩⟨+⟩⟨−−=⟩⟨ −−− (4-59)

1N

1N0

1Np1N iC

qi

C

qv)1N(ωjv

dt

d⟩⟨

⟩⟨+⟩⟨

⟩⟨+⟩⟨+−=⟩⟨ +++

(4-60)

where ))1)θ(cos(j)θ)(sin(2/V(v 1SR −+−=>< , dq 0 =⟩⟨ , and

))πd(sinj)πdcos()πd)(sin(π/1(q 2N −=⟩⟨

As can be seen, the state space model described by Equations (4-55) through (4-

59) has six complex differential equations and captures the interaction between the

fundamental and high frequency quantities, as there is an explicit dependency on the

124

switching frequency (ωS=NωP).

On the other hand, approximating q(t) by the duty ratio only ( )t(q)t(q 0⟩⟨≈ ), the

traditional state space model in term of the fundamental quantities is recovered,

1SR1

1

p0

0p

1

1 v0L

1

v

i

jC

qL

q

L

Rj

v

i

dt

d⟩⟨

+

⟩⟨

⟩⟨

ω−⟩⟨

⟩⟨−−ω−

=

⟩⟨

⟩⟨ (4-61)

The above state space has two complex differential equations and there is no

switching frequency dependency. Notice that this index 1 model differs from the exact

model only in two aspects: (i) the switching function has been replaced by the duty ratio

and (ii) the diagonal elements of the state matrix have been augmented by the term –jωP.

4.5.1.2 Model Accuracy

The generalized averaged model can bring insights to the design process. For

example, say the interest is in calculating the steady state capacitor stress, specifically the

RMS current. In order to investigate the accuracy of each model, a comparison of the

prediction made by the traditional model and the generalized averaged scheme against

the true switched waveforms can be made. Figure 4-4 shows the results obtained. The

switched waveform is obtained from a detailed computer simulation. On the other hand,

the index 1 and 1, N-1, N+1 approximations are obtained by first setting to zero the

125

left hand side (LHS) of their corresponding state space representation. This gives the

capacitor voltages so by using Equation (4-12) the corresponding phasor current can

readily be obtained. Finally, the reconstruction formula (4-4) allows determination of the

time−domain waveforms.

Switched

Index 1

1.7 1.705 1.71 1.715 1.72 1.725 1.73

-1.5

-1

-0.5

0

0.5

1

1.5

Time (s)

Index 1, N-1, N+1

Figure 4-4 Waveform of the switched capacitor current along with the traditional and augmented approximations. FP=60(Hz), FS=1020(Hz), d=50%.

As can be seen, the prediction made by the augmented model is much better than

the traditional model. The RMS values for this particular case are ISW=722(A), I1=510(A)

and IN=685(A) for the switched, index 1 and index 1, N-1, N+1 waveforms,

respectively. Although the augmented model still falls short, it gives a more realistic

insight about the current stress the capacitor has to manage.

126

4.5.1.3 Eigenvalues Pattern

It is well known that capacitive series compensation introduces a resonance

between the inductive reactance of the line and the compensation capacitor. However, the

frequency at which this resonance occurs is usually on the order of a few tens of hertz.

On the other hand, the switching frequency is at a few thousands of hertz, therefore a

dynamic interaction between the switching frequency and the modes of the system should

not be expected.

The pattern followed by the eigenvalues is of special interest as it directly relates

to the physical resonance of the system as well as to the power and switching frequency.

The system exhibits a physical resonance of approximately FR=30(Hz) which, neglecting

the various resistances, can be computed as )LC/d)(π2/1(FR = . When the system is

modeled by the index 1 approximation, two extra oscillatory modes are added into the

state matrix whose imaginary parts are given by ±FR±FP (±30, ±90(Hz)). When the

system is augmented to include the fundamental component of the switching frequency

eight extra modes are incorporating, yielding to a total of 12 modes whose imaginary

parts are ±FR±FP±FS (±30, ±90, ±930, ±990, ±1050, ±1110(Hz)). This is summarized in

Figure 4-5.

127

Figure 4-5 Eigenvalues distribution for the different models. FR=30(Hz), FP=60(Hz), FS=1020(Hz).

This observation illustrates a simple litmus test that may be employed to identify

the need for modeling higher index dynamics. By examining the system dynamic

resonant frequencies, power frequency and switching frequency, it is possible to

determine the degree of mathematical complexity needed to obtain a faithful

representation.

4.5.2 Generalized Averaging Applied to the ΓΓΓΓ−−−−controller

4.5.2.1 The Model

Similarly to the Ξ−controller case, the exact dynamic model for the Γ−controller

128

can be obtained from its corresponding equivalent circuit (Figure 3-22) using q(t) instead

of d(t). This is shown in Figure 4-6.

Figure 4-6 Exact model for the Γ−controller.

In this case, vS and vR represent the corresponding space vectors,

))tωcos(j)tω(sin(V2)t(v PPS ⋅−= (4-62)

))θtωcos(j)θtω(sin(V2)t(v PPR +⋅−+= (4-63)

129

Considering as state variables the voltages and currents shown in the equivalent

circuit above, the exact state space model can be constructed as follows,

)t(uB)t(x))t(q(A)t(xdt

d⋅+⋅= (4-64)

where the matrices A and B, as well as the state and input vectors are described below.

−+−+

+−−+

+−+

++

++

=

0000C/1000C/aq

00000C/100C/aq

000000C/10C/aq

0000000C/1C/aq

L/1)jzzj(q-)z-zj(q-)zjzj(q-)zzj(q-/LR-zjzz-jz-jz

)jzz(q-1/L-)zz(q-)zjz(q-)zz(q-jz-/LR-zjzz-z

)jzzj(q)z-zj(q1/L-)zjzj(q)zzj(qz-jz-/LR-zjzjz-

jzzq)z-z(qjz-zq1/L-zzqjzz-jz-/LR-zz-

)jz-z(q-)zz(q-)jzz(q-)z-z(q-jzz-jz-zz

))t(q(A

s4

s3

s2

s1

ps274273272271psps55551

274ps2732722715psps5551

274273ps27227155psps551

274273272ps271555psps51

86486386286133334

(4-65)

−−

−−

=

00

00

00

00

jzjz

zz

jzjz

zz

zz

B 811

811

811

811

109

(4-66)

=

)t(v

)t(v

)t(v

)t(v

)t(i

)t(i

)t(i

)t(i

)t(i

)t(x

4C

3C

2C

1C

4PS

3PS

2PS

1PS

R

(4-67)

=

)t(v

)t(v)t(u

R

S (4-68)

The constants zi (i=1,2,..,11) are functions of the parameters of the equivalent

circuit. See Appendix 4 for a complete description of them. Also, notice that the explicit

130

time dependence of qi (i=1,2,…,4) in the state matrix has been dropped to avoid

notational clutter.

Since in this case the excitation is complex, the rules developed in Section 4.4.2

have to be applied in order to develop the generalized averaged model. However, the

resulting model is a (two) x (three) x (nine) = 54 state space system. Therefore, it will not

be shown here. It can easily be calculated via symbolic computation using standard

software such as MatlabTM, MapleTM or MathematicaTM.

As in the case of the Ξ−controller, the traditional index 1 state space model can

be computed by adding -jωP onto the diagonal elements of the state matrix (4-65) and

replacing the switching functions by the corresponding duty ratios. The resulting model

in this case would be a (two) x (nine) = 18 state space system.

4.5.2.2 Model Accuracy

The Γ−controller exhibits a resonance between the phase−shifter transformer

secondary−side leakage inductor and the filter capacitor ( CL2/1F PSR π= ), which might

be in the order of the switching frequency and therefore lead to unstable operation.

Although in the Design Considerations Section for the Γ−controller (Section 3.2.5) the

way in which to approach this issue qualitatively was discussed, it will now be formally

discussed in terms of the generalized averaging theory.

It has been shown that the switching process introduces harmonics into the system

with frequencies of form PS FnF ± (n=1,2,…∞). These frequencies need to far exceed the

131

resonances of the system in order to avoid their excitation. Clearly, the critical case is

when n=1 ( PS FF ± ), since RPSRPS F)FnF(F)FF( >±⇒>± . The case of n=1 is fully

captured by the index 1, N-1, N+1 model and therefore it can describe the actual

system at a much higher degree of accuracy as discussed in the example below.

As an illustration, the parameters that define the resonance frequency are selected

as Lps= 0.3mH and C=73µF so the resonance occurs at 1862(Hz). These values are the

same ones used to show steady state operation in the Control Capabilities Section

(Section 3.4.4), so they may be considered reasonable.

Detailed switched simulations were conducted considering FS=2400(Hz) and

FS=1800(Hz), whose results are shown in Figure 4-7 and Figure 4-8, respectively.

-1

0

1

-1

0

1

-1

0

1

0.25 0.255 0.26 0.265 0.27 0.275 0.28

-1

0

1

Time (sec)

(a)

(b)

(c)

(d)

Switched,

and

Index 1

Index 1, N+1, -(N-1)

Figure 4-7 Capacitor voltage waveforms with FR=1862(Hz) and FS=2400(Hz).

132

-1

0

1

-1

0

1

-1

0

1

0.25 0.255 0.26 0.265 0.27 0.275 0.28

-1

0

1

Figure 4-8 Capacitor voltage waveforms with FR=1862(Hz) and FS=1800(Hz).

The state variables plotted are the capacitor voltages vCi (i=1,2,…4) from the

equivalent circuit shown in Figure 4-6. The simulated switched waveforms are plotted

against the index 1 and index 1, N+1, -(N-1) approximations, which are obtained

from their corresponding state space models.

As can be seen in Figure 4-7, when the resonance frequency and switching

frequency are sufficiently different, the index 1 model describes the system accurately

and the augmented scheme gives no extra information. However, when the resonance

frequency becomes closer to the switching frequency, Figure 4-8 shows that the duty

ratio based model fails to predict the oscillatory behavior of the state variables. The

augmented scheme does capture such behavior and hence its potential becomes evident.

Since these devices have been developed to control power flows along

transmission lines, it is likely that a closed−loop regulator would be used to maintain

133

appropriate set−points. In such cases, the ripple phenomena would not be captured

whatsoever by measuring net P and/or Q at 60Hz. Therefore, the duty ratio−based

approximation would be blind to the potential instabilities that may be incipient in the

system.

4.6 Summary

This Chapter has introduced the dynamic modeling for AC link power flow

controllers under the generalized averaging framework. The presence of excitation at

power frequencies that interact with the switching frequency requires a systematic

integration of the techniques developed for multifrequency averaging for DC−DC

converters and phasor dynamic modeling common for study of AC converters. The

mathematical development of the integration is presented under the condition that the

switching frequency be an integer multiple of the power frequency.

The application of the technique to predict system behavior was illustrated using

the Ξ−controller and the Γ−controller. The results indicate that the augmented

multifrequency averaged model is superior to the traditional DC averaged model in

predicting high frequency interactions. The nature of the augmentation of the eigenspace

of the system under DC averaged and multifrequency averaged models was also

illustrated. In addition, it was briefly discussed how the augmented state matrix can lead

to identifying potential system resonances, especially when the system exhibits

oscillatory modes in the vicinity of the switching frequency.

134

Chapter 5 Feedback Control for AC

Link Power Flow Controllers

5.1 Introduction

Since AC link vector switching power flow controllers have been developed to

control power flows along transmission lines, it is likely that a closed−loop regulator

would be needed to maintain appropriate set−points.

Figure 5-1 shows, in the Laplace domain [46, 47], the basic structure for a

feedback control system. The plant, g(s), represents the power circuit whose outputs, y,

need to be maintained at a certain level dictated by yREF. The approach is to measure the

outputs via a transducer (β) and compare such measurements against the references to

generate an error signal (ε). This error is then processed by an appropriate compensator

h(s) to generate the manipulated inputs uM, which drive the controllable devices of the

plant. In addition, the plant usually has other inputs represented by u.

yREF yuMController

h(s)Plantg(s)

u

Figure 5-1 Configuration for classical control design.

135

The control design problem is to determine h(s) in order to meet the functional

requirements of the overall system. These requirements include, among others, stability,

maintenance of the desired operating condition in case of disturbances, and acceptable

dynamic performance (overshoot, settling time).

As will become evident throughout this chapter, the Ξ−controller, although it

corresponds to a nonlinear system, is a single−input, single−output (SISO) system so the

control design problem for a nominal operating condition can be assessed by classical

techniques such as Bode plots [46, 47]. On the other hand, the Γ−controller, in addition

to being nonlinear, is a multiple−input, multiple−output (MIMO) system; therefore,

techniques that are more refined are required for the analysis [48].

5.2 Feedback Control for the ΞΞΞΞ−−−−controller

The control design problem starts with the identification of the dynamic model for

the power circuit. The model chosen for this purpose is based on the single−phase index

1 averaged equivalent circuit shown in Figure 3-14. The mathematical description was

deduced in Section 4.5.1.1. It was found that the corresponding state space is described

by Equation (4-61), repeated here for convenience,

136

[ ]1SR1

1

p

p

1

1 V0L

1

V

I

jC

dL

d

L

Rj

V

I

dt

d⟩⟨⋅

+

⟩⟨

⟩⟨⋅

ω−

−−ω−=

⟩⟨

⟩⟨⋅ (5-1)

As the interest is in controlling the active power at the receiving end, the output of

the system can be defined as,

Re*11RR IVP ⟩⟨⟩⟨= (5-2)

Before proceeding further, notice the following: (i) Equations (5-1) and (5-2)

presented above are both in terms of complex quantities, so separation into real and

imaginary parts is necessary; (ii) Since there is a single (manipulated) input, d, and a

single output, PR, Equations (5-1) and (5-2) describe a SISO system; (iii) Due to the

inherent nonlinearities introduced by the products between the manipulated input, d, and

the state variables, 1I⟩⟨ and 1V⟩⟨ , linearization is needed in order to apply classical

control techniques.

5.2.1 Proposed Controller

Traditionally, the first attempt in controlling a process has been to linearize the

plant around a nominal operating condition and try a combination of a proportional (P),

integral (I), and/or derivative (D) controller. PID controllers are widely used in industry

137

and have become the standard for control system design. Only when the PID approach

fails are more sophisticated techniques considered.

In the case of processes involving switching power converters, differentiation is

particularly undesirable. Switching power converters are rich in high frequency noise

generated by the switching process. Derivative controllers have a gain that increases with

frequency and hence tends to amplify high frequency noise. Thus, as in most processes

involving switching power converters, a PI controller is proposed here. A formal

justification will be given in Section 5.2.1.2.

The overall closed loop system is shown in Figure 5-2. The PI controller acts

upon the error to generate the duty ratio as,

∫ ττε+ε=t

0

IP d)(K)t(K)t(d (5-3)

PRPREF

Carrier

PIController

PWMPulse

Generator

d Pulses

vS(t)

Power Systemwith a-Controller

vR(t)

Figure 5-2 Block diagram of the control system.

Since the model for the power circuit is the index 1 average, the PWM pulse generator

138

may be considered to have a unity transfer function so the duty ratio, d, acts directly upon

the plant. In addition, since the power circuit is nonlinear, the plant may be modeled by

its small signal transfer function.

5.2.1.1 Small Signal Model

The small signal model for the plant can be obtained by linearizing Equations (5-

1) and (5-2) around a nominal operating point. For that purpose, consider the general

form of Equations (5-1) and (5-2),

))t(u),t(u),t(x(f)t(x M=ɺ (5-4)

))t(u),t(u),t(x(g)t(y M= (5-5)

Since the interest is in the transfer function with respect to the manipulated inputs,

the linearization of f(x(t),u(t),uM(t)) and g(x(t),u(t),uM(t)) around 0x becomes

.t.o.h)u)t(u(u

f)x)t(x(

x

f)u,u,x(f))t(u),t(u),t(x(f 0MM

0M0

00M00M +−

∂∂

+−∂∂

+= (5-6)

.t.o.h)u)t(u(u

g)x)t(x(

x

g)u,u,x(g))t(u),t(u),t(x(g 0MM

0M0

00M00M +−

∂∂

+−∂∂

+= (5-7)

where h.o.t. stands for higher order terms. The operating point x0 can readily be obtained

139

by assigning some value to the duty ratio, say d0, and then solving Equation (5-4) for

steady state i. e., making the LHS equal to zero.

Applying Laplace’s transform to Equations (5-4) through (5-7), the small signal

model becomes

MuB~

xA~

xs ∆⋅+∆⋅=∆⋅ (5-8)

MuD~

xC~

y ∆⋅+∆⋅=∆ (5-9)

where,

0xf

A~

∂∂

= , 0Mu

fB~

∂∂

= , 0x

gC~

∂∂

= , 0Mu

gD~

∂∂

= , and )xx(x 0−=∆ , )yy(y 0−=∆ ,

)uu(u 0MMM −=∆ .

For the particular case of the Ξ−controller, each term of Equations (5-8) and (5-9)

becomes,

[ ] TIm1

Re1

Im1

Re1 VVIIx ⟩⟨⟩⟨⟩⟨⟩⟨= (5-10)

[ ] TIm10

Re10

Im10

Re100 VVIIx ⟩⟨⟩⟨⟩⟨⟩⟨= (5-11)

RPy = (5-12) 0R0 Py = (5-13) duM = (5-14) 00M du = (5-15)

ω−

ω

−−ω−

−ω−

=

0C/d0

00C/d

L/d0LR

0L/dLR

A~

p0

p0

0p

0p

(5-16)

⟩⟨

⟩⟨

⟩⟨−

⟩⟨−

=

CI

CI

LV

LV

B~

Im10

Re10

Im1SR

Re1SR

(5-17)

[ ]00VVC~ Im

1RRe1R ⟩⟨⟩⟨= (5-18) 0D

~= (5-19)

140

Notice that the separation in real and imaginary parts for the states variables has

taken place. The plant’s input/output transfer function, g(s), readily follows from

Equations (5-8) and (5-9),

C~

B~

)A~

sI(d

P)s(g 1R +−=

∆

∆= − (5-20)

On the other hand, the PI controller’s input/output transfer function, h(s), can be

obtained applying Laplace’s transform to Equation (5-3),

)s

KK(

d)s(h I

P +=ε∆∆

= (5-21)

The overall small signal model developed in this section is shown in Figure 5-3.

The control design problem can now be visualized as calculating appropriate values for

the gains KP and KI in order to satisfy system performance.

C~

B~

)A~

sI( 1 +− −PREF PRd

sK

K IP +

Figure 5-3 Block diagram for the small signal model.

Notice that the global input/output transfer function is

141

)s(T1

)s(T1

P

P

REF

R

+⋅

β=

∆

∆ (5-22)

where T(s) is the loop gain defined as

)s(g)s(h)s(T ⋅⋅β= (5-23)

5.2.1.2 Controller Design via Bode Plots

The controller design is usually done by “shaping” the frequency response of the loop

gain, T(s), as it carries most of the information of interest [46, 47]. The Bode Plots

approach focuses on three performance indices:

(i) Stability margins: As may be evident from Equation (5-22), the situation

o1801)j(T ∠=ω should be avoided in order to maintain stability in the

bounded−input, bounded−output (BIBO) sense. In practical situations, control

designers impose security margins to keep the system away from such a

critical value. The quantitative definition of these security margins begins by

introducing the gain crossover frequency (GCF) and the phase inversion

frequency (PIF). The former refers to the frequency at which the magnitude of

T(jω) equals one ( 1|)j(T| =ω ) while the latter refers to the frequency at which

the angle of T(jω) becomes 180° ( o180)j(T =ω∠ ). Thus, at the GCF, the

142

corresponding angle should be away from 180° by an acceptable phase

margin (φM). In addition, at the PIF, the corresponding magnitude should be

away from 1 by an acceptable gain margin (GM). Furthermore, it should be

evident that in order to have a stable system, the GCF has to occur before the

PIF (GCF < PIF). This provides a positive φM at GCF and a positive GM at PIF. A

GM of 2 and a φM of 60° are usually considered acceptable, and are used as

targets in the control design process.

(ii) Bandwidth: Equation (5-22) shows that the feedback is effective only for

large values of T(s). The GCF is also called the bandwidth of the regulator as it

defines the value at which the feedback becomes ineffective. The bandwidth

also features the property of being proportional to the speed of response of the

regulator. For both of these reasons, it is important to keep the bandwidth as

high as possible.

(iii) Steady state error: The steady state error can be directly evaluated from T(0).

It should be evident from Equation (5-22) that it T(0)=∞ drives the steady

state error to zero.

These indices sometimes conflict with each other and the designer has to evaluate the

tradeoffs involved in the design process.

Based on the data shown in Appendix 2, the regulator for the Ξ−controller is designed

as follows. The transducer β is considered as a pure gain free of noise. The value of

β=10−6 is selected as it measures power in the order of MW. The frequency response of

the partial loop gain βg(s) is shown in Figure 5-4. It can be seen that PIF<GFC which is a

143

sufficient condition for instability, so the first and most important task is to stabilize the

system with an appropriate regulator.

-100

-50

0

50

10-2

10-1

100

101

102

103

104

-400

-300

-200

-100

0

Figure 5-4 Bode Plot for the partial loop gain βg(jω).

Notice that as a result of modeling the system with the index 1 average, two

resonant peaks are observed in the frequency response. These peaks occur at FR±FP, as

predicted early by analyzing the eigenvalues’ pattern.

Figure 5-5 shows the frequency response for the proposed PI regulator, which is

obtained by selecting the gains as KP=10-4 and KI=0.5. Cascading this regulator as shown

in Figure 5-3, the frequency response of the final loop gain, T(s)=βh(s)g(s), becomes as

shown in Figure 5-6.

144

-100

-50

0

50

10-2

10-1

100

101

102

103

104

-400

-300

-200

-100

0

Figure 5-5 Bode Plot for the PI controller h(jω).

-100

-50

0

50

10-2

10-1

100

101

102

103

104

-400

-300

-200

-100

0

Figure 5-6 Gain and Phase margins from the loop gain T(jω)= βh(jω)g(jω).

It can be seen that now GFC<PIF and the Nyquist’s criterion for stability [46]

would show that the system is indeed stable. It can also be seen that the stability security

margins are within the specified range (GM=7.5dB=2.4, φM=89°) and the integral part of

145

the regulator guarantees to have T(0)=∞. The bandwidth, however, seems low but

adequate for the application, as will become evident in the next section.


Once the regulator has been designed, computer simulations are carried out in

order to verify the regulator performance. The typical tests evaluated are the response of

the system upon a step change in the reference and upon small disturbances on the

non−manipulated inputs.

5.2.2.1 Response to a step change in the reference

This test is carried out to verify the BIBO stability of the system as well as to

evaluate the dynamic performance of the regulator. Figure 5-7 shows the results for a

15% step change in the reference power. As can be seen, a first order stable response is

obtained. The regulator is also able to track the reference and the speed of response is

about 0.5s, which indicates that the bandwidth is adequate.

146

0.9

1

1.1

1.2

-2

0

2

0.9 1 1.1 1.2 1.3 1.4 1.50.9

1

1.1

1.2

Figure 5-7 Response to a 15% step change in the reference power. (a) shows the step change applied to the reference power while (b) and (c) show the response on the line current and the measured power at the

receiving end, respectively.

In addition, Figure 5-7 may be directly compared to the open loop response

shown in Figure 3-18, as the step change in the reference power was made coincident to

the duty ratio step change (notice that the steady state measured power in both figures is

the same). It can be seen that the closed loop regulator dramatically improves both the

overshoot and the oscillatory behavior observed in the open loop case.

5.2.2.2 Response to disturbances

This test is carried out to evaluate the ability of the system to track the reference

upon small disturbances on the non−manipulated inputs. Figure 5-8 shows the response

of the system for a step change of 5% in the magnitude of the sending end voltage. Figure

5-9 shows the response of the system to a step change of 3° in the transmission angle.

147

0.9

0.95

1

1.05

-2

0

2

0.9 1 1.1 1.2 1.3 1.4 1.50.7

0.8

0.9

1

1.1

Figure 5-8 Response to a 5% step change in the sending end voltage. (a) shows the step change applied to the magnitude of the sending end voltage while (b) and (c) show the response on the line current and the

measured power at the receiving end, respectively.

20

22

24

-2

0

2

0.9 1 1.1 1.2 1.3 1.4 1.50.7

0.8

0.9

1

1.1

Time(s)

(a)

(b)

(c)

Figure 5-9 Response to a 3° step change in the transmission angle. (a) shows the step change applied to the transmission angle while (b) and (c) show the response on the line current and the measured power at the

receiving end, respectively.

It can be seen that the regulator is able in both cases to track the reference,

148

although the oscillatory response of the power might not be acceptable. Suitable changes

in the regulator design, including a different control approach, may be needed in order to

improve these responses. This is discussed in the Future Work Chapter.

5.3 Feedback Control for the Γ−−−−controller

The overall control system for the Γ−controller is shown in Figure 5-10. Since

this device was realized to simultaneously control the active and reactive power through

a transmission line, it naturally has two outputs. References to track the corresponding

outputs are likely to be used as shown in the figure. It becomes evident that, under these

circumstances, this is the case of a MIMO system. Classical techniques such as the

Nyquist’s stability criterion or feedback loop design using Bode Plots are not easily

extendable.

?Controller

PWMPulse

Generator

d1Pulses

vS(t)

Power Systemwith a-Controller

vR(t)

Carrier

d2d3d4

Q

P

PR

QRQ

PREFP

QREF

Figure 5-10 Control system for the Γ−controller.

149

Therefore, as suggested in the figure, at first glance it is not clear what regulator

to use in order to satisfy the various performance indices introduced in the previous

section. In addition, notice that the regulator needs to generate three outputs (one of the

duty ratios can be expressed as 1−summation of the other three) from two input errors. It

has also been observed that there is cross−coupling between the outputs i. e., a change in

say εP would also affect the output value of QR.

On the other hand, as discussed in Section 4.5.2.2, it is not clear whether the

index 1 average model is precise enough to describe the behavior of the Γ−controller,

as it exhibits a resonance that might be in the same order the switching frequency. The

augmentation to the indices 1, N+1, -(N-1) average might be needed for satisfactory

closed loop performance.

All of these issues make the Γ−controller regulator design a challenging problem

that is under investigation is proposed as future research in Chapter 9.

5.4 Summary

This chapter has introduced the notion of closed loop regulation for AC link power

flow controllers. In the case of the Ξ−controller, the dynamic modeling for the power

circuit was made by using the index 1 average model introduced in Chapter 4.

Classical control techniques indicated that a PI regulator would perform satisfactorily. On

the other hand, in the case of the Γ−controller, a brief introduction to the control design

problem was made, indicating that the subject is left as an open question for further

investigations.

150

Chapter 6 A comparative

evaluation of Power Flow

Controllers using AC Link and DC

Link Converters

6.1 Introduction

When introducing a new technology it is customary to contrast its features against

the state−of−the−art. As pointed out in Chapter 1, power flow controllers that use a DC

link voltage source inverter are considered to be superior to previous realizations in terms

of harmonic performance, dynamic response and ease of operation.

Although the functional equivalency between the AC link and DC link approaches

has been illustrated in the literature [14, 27], a detailed comparison between their features

was not attempted. It is the goal of this chapter to present a comparative evaluation of the

two approaches.

A comparative evaluation of particular solutions for a given application may be

made on the basis of several performance features. Salient features include: harmonics of

waveforms, operating losses, ratings of power converters, reactive component

requirements, transformer kVA requirements, complexity of control, dynamic response in

terms of improving voltage stability, small signal and large signal stability, damping of

151

sub−synchronous resonance, etc. Given the degree of variability based on the application

of these devices in the form of shunt, series, shunt−series and interline connections, a

definitive evaluation appears to be a formidable task. Therefore, in order to maintain a

focus in the evaluation, a particular application, namely series compensation is

considered in this chapter. Furthermore, the evaluation is limited to solutions that feature

superior waveform quality arising from high frequency or high pulse number switching

with sinusoidal line current waveforms. This precludes the consideration of TCSC, TSSC

and GCSC [14] solutions from evaluation in this study. It is felt that due to their

fundamentally different harmonic characteristics due to phase controlled switching, the

benchmarking would not be consistent, and unreasonably extend the scope of the chapter.

In this chapter, a focused analytical modeling and design study of a candidate

application using the DC link and the AC link power converters is performed in order to

evaluate their performance. The comparison criteria used for the evaluation include

voltage, current and power throughput ratings of the main power circuit components

(including transformers, capacitors, and semiconductors), quality of terminal voltage and

current waveforms in terms of harmonics, losses in power semiconductors and transient

performance of the solutions in tracking commands and rejecting disturbances. No

attempt is made herein to estimate the comparative cost of these solutions, as such costs

are a complex function of market trends, economic factors and engineering development,

and would change considerably with respect to time and location. However, the design

ratings for transformers, capacitors and power semiconductors together may be

considered to be a proxy for the capital costs of equipment.

152

6.2 Candidate Compensators

6.2.1 DC Link Series Compensator

The DC link series compensator, termed SSSC, can be realized in a variety of

manners. DC capacitors or DC inductors could be used to realize the DC link, leading to

the use of a voltage source inverter or a current sourced inverter, respectively. Moreover,

multi−pulse or PWM can be selected as a modulation strategy to synthesize the output

voltage. The multi−pulse (48−pulse) voltage source inverter option is chosen here as it is

considered the state−of−the−art approach and it is commercially available with ratings up

to 100(MVA) [19].

Figure 6-1(a) shows a simplified schematic of the main stages involved in the

realization of the 48−pulse system [49]. As can be seen, the DC link is realized using two

series connected DC capacitors with access to their mid−point N [50-52]. This allows

three voltage levels (VC1, VC2, 0). Four independent diode−clamped three−phase

three−level converters are connected to the DC bus. Figure 6-2(a) shows the detailed

switch realizations for each converter. The voltage synthesis for phase A is shown in Fig.

3(a). Phase−shifted waveforms (±120o) are synthesized for phases B and C. As suggested

in Figure 6-1(a), each three−level converter is then connected to a magnetic structure

based on Y−zigzag ∆−zigzag phase−shifting transformers that allows creation of a

24−pulse waveform. The final 48−pulse waveform is obtained by making the conduction

angle of each converter σ=172.5o. Thus, the lowest characteristic harmonic numbers

153

present in the output waveforms are 47 and 49.

It may be concluded from Figure 6-1(a) and Figure 6-2(a) that stable operating

points are achieved only when the output voltage is in quadrature (±90o) with the output

current, because otherwise there would be active power exchange between the DC

capacitors and the AC system, leading to a permanent charge or discharge of the

capacitors and therefore unstable operation. The same argument is used to control the

magnitude of the AC output voltage. By allowing a small real power exchange for a short

duration between the DC link and the AC system, it is possible to drive the capacitors’

voltage to a desirable value and therefore adjust the output voltage. Finally, it should be

noted that in order to generate symmetric AC output voltage waveforms, a suitable

algorithm for equalizing the average value of VDC1 and VDC2 needs to be implemented

[53]. Section 6.5.2 describes the implementation of such algorithm.

Figure 6-1 Schematic of candidate compensators. (a) SSSC (b) Ξ−controller.

6.2.2 AC Link Series Compensator

The Ξ−controller was extensively studied in Section 3.3. As the goal of this

chapter is to contrast the features of this device against the SSSC, some schematics and

154

concepts will be repeated here for convenience.

Figure 6-1(b) shows a realization for the Ξ−controller that naturally follows from

the SSSC topology introduced in the previous section. As can be seen, four banks of

three−phase AC capacitor make up the AC link. Each bank is switched using a

three−phase vector−switching converter whose principle of operation is depicted in

Figure 6-2(b) and Figure 6-3(b). The former shows the switch realization of a

double−throw single−pole three−phase switch and the latter the voltage synthesis process

for phase A. Phase−shifted waveforms (±120o) are synthesized for phases B and C.

VB

VC

VA

IA

IB

IC

VCA

VCB

VCC

T2A

T2B

T2C

T1A

T1B

T1C

+

-

N

VDC1

VDC2

VB

VC

VA

IA

IDC1

IDC2

IB

IC

T1A

T2A

T3A

T4A

T1B

T2B

T3B

T4B

T1C

T2C

T3C

T4C

(a) (b)

D1A

D2A

D3A

D4A

DC1A

DC2A

D1B

D2B

D3B

D4B

DC1B

DC2B

D1C

D2C

D3C

D4C

DC1C

DC2C

D1A

D1B

D1C

D2A

D2B

D2C

N

Figure 6-2 Converter realizations. (a) SSSC (b) Ξ−controller.

180 360

T2AT3A

T2AT3A

T2AT3A

T3AT4A

T1AT2A

VDC1

VDC2

Multi-pulse Injected Voltage

0

t (deg)

(a)

t (deg)

Carrier

Duty Ratio

T1A

T2A

PWM Injected Voltage

(b)

Figure 6-3 Waveforms illustrating AC voltage synthesis. (a) SSSC. (b) Ξ−controller.

As can be seen from Figure 6-3(b), the AC voltage generated by each capacitor

155

bank is rich in harmonics and hence unless output filters are used, the resulting waveform

would be unacceptable for utility applications. However, by using the magnetic structure

suggested in Figure 6-1(b) and phase−shifting the PWM carriers of each bank by 90o, it is

possible to operate with no output filter at a modest frequency of FS=720(Hz). This, as in

the SSSC case, also limits the lowest characteristic harmonic numbers to be 47 and 49. A

more detailed contextual comparison of the waveforms injected by each compensator is

discussed later in Section 6.4.2.4.3.

6.3 Test system description

Figure 6-4 shows the case study system that will be used to perform the

comparative evaluation. As can be seen, it corresponds to a simple transmission line with

a two bus power system on which a series compensator has been embedded. The

compensator can be either the SSSC or the Ξ−controller.

Figure 6-4 One line diagram of the candidate series compensation system.

In order to make the comparison meaningful, both the SSSC and the Ξ−controller

are assumed to provide the same amount of compensation. Table 6-1 shows the specific

values for the transmission system considered in this case study. Due to the lumped

156

resistance of the transmission line, the line power slightly varies depending on the

location where the measurement is taken. The location downstream of the converter (at

V2 in Figure 6-4) is selected to measure the power. It readily follows that, without

compensation, the nominal line power is PLNom=140(MW). A 40(MW) increase is

selected for full compensation, which represents a ~30% increase above the nominal

value. Thus, at full compensation, one would measure PLComp=180(MW).

Table 6-1 System Data Base Values: 110kV/100MVA/60Hz Bus Voltage (pu) Impedance (pu)

SV 1 0= ∠ ZS=0.01+j 0.17

RV 1 20= ∠− ZR=0.01+j 0.07

6.4 Steady state performance evaluation

6.4.1 Operating Modes

As suggested in Figure 6-4, each compensator can operate in different control

modes. Although the ultimate objective is the control of the active power through the

line, this can be achieved through different regulation strategies. The most direct

approach involves commanding a certain amount of desired power PL and synthesizes a

voltage waveform to achieve such an amount. This approach has the advantage of

maintaining the active power through the line at a pre−established value but, under some

contingences, this may not be desirable or possible [14]. Alternatively, one can command

a certain amount of injected voltage VINJ or a certain amount of injected impedance

157

ZINJ=VINJ/IL. These three control methods, namely power mode, voltage mode and

impedance mode, can be used in each approach to realize power flow control.

The remarks made in Section 6.2 readily lead to the steady state equivalent

circuits presented in Figure 6-5. As can be seen, the natural steady state representation of

the SSSC is a controlled voltage source while for the Ξ−controller is a controlled

capacitor. For the SSSC, the manipulated input is the magnitude of the DC voltage (VDC)

while for the Ξ−controller it is the duty ratio (d). The operation of the SSSC depends on

the synthesis of AC voltage waveforms using the constituent inverters appropriately

synchronized to the AC line using a phase−locked−loop (PLL). On the other hand, the

Ξ−controller is regulated through a simple duty ratio control that varies the amount of

injected AC capacitance with the line in the open loop mode. However, through

appropriate feedback control, both of these devices can be regulated to operate in any o

the operating modes described above.

Figure 6-5 Steady sate equivalent circuits. (a) SSSC (b) Ξ−controller.

In order to explicitly show the ability of each compensator to operate under the

various operating modes, formulas that relate the line power (PL), the injected voltage

158

(VINJ) and the injected impedance (ZINJ), with respect to the manipulated inputs are

presented in Table 6-2 [29]. These formulas readily follow from the equivalent circuits

from Fig. 5. For the sake of simplicity, it is assumed that the transmission line is purely

inductive and |VS|=|VR|=V. In addition, it is assumed that the injection transformer is

ideal (XT=0) and has unity turn ratio. Finally, it is also supposed that the line current is

instantaneously available for control purposes. In the case of the Ξ−controller the

assumption of XT=0 is removed to explicitly show that this device can provide a certain

degree of inductive compensation (when XT>d2XC). However, it has been pointed out in

the literature [16] that series compensators seldom provide steady state inductive

compensation due to the increase in reactive power circulation associated with it, so the

focus herein is on capacitive compensation only.

Table 6-2 Operating Modes

Operating Mode SSSC Ξ−Controller

Voltage DCINJ mVV = IJN 2L T C

2VV sin

21 X /(X d X )

θ=+ −

Impedance INJ LDC

1Z X

1 (2Vsin / 2) / mV=± θ

C2

TINJ XdXZ −=

Power 2

L DCL L

V VP sin mV cos

X X 2

θ= θ ±

2

L 2L T C

VP sin

X (X d X )= θ

+ −


As may be evident from Figure 6-4, the main components to be rated are the

injection transformer, the compensation capacitors and the power converter. The overall

design process begins by assuming that the bus voltages at locations VS and VR are

159

known so that the nominal operation of the transmission line without compensation can

be found. Next, defining the percentage (say λ) by which the line power is going to be

increased above its nominal value, the line power at full compensation can be computed

as LComp LNomP (1 )P= + λ . Finally, in reference to Figure 6-4, by solving Equations (6-1)

and (6-2), the electrical variables at the injection transformer terminals, VINJ and IINJ(=IL)

can be found.

S S L INJ L R L RV Z I | V | ( I 90 ) Z I V 0− ⋅ − ∠ − ° − ⋅ − =∢ (6-1)

*R R L L LComp3 (V Z I ) I Pℜ ⋅ + ⋅ ⋅ = (6-2)

It should be noted that Equations (6-1) and (6-2) provide three scalar equations

that allow the unknown variables |IL|, LI∢ and |VINJ| to be solved.

The values of VINJ and IINJ are independent of the type of compensator used and

provide the basis for the design process. For the case study, λ=30% so the solution of

Equations (6-1) and (6-2) gives VINJ=6.1(kV) and IINJ=965(A). It follows that the injected

power is QINJ=3VINJIINJ=17.6(MVAr).

6.4.2.1 Choice of power semiconductors

Power semiconductor switch ratings and properties remain the limiting factor that

determines the highest possible power throughput in any application. Selection and

application of switching devices involves a careful trade−off between the various

families of power semiconductors matched against the ratings required for the particular

power converter. An examination of the topology of the converters indicates that single

quadrant force commutated semiconductors and diodes form the building block for both

160

realizations. The device families that fit these needs at voltage levels in the order of a few

kV are GTOs, IGCTs and IGBTs. Among these, GTOs and IGCTs belong to the thyristor

family of devices while the IGBT belongs to the transistor family of devices. While both

families of devices are capable of turning off without the need for any snubbers, due to

the regenerative mechanism that dominates the turn on process in thyristors, GTOs and

IGCTs require di/dt limiting reactors to be included in their realizations. The introduction

of di/dt limiting reactor further necessitates a ‘pole clamp’ that captures the trapped

stored energy in the di/dt limiting reactors and diverts it to the DC bus during each

turn−off event. A detailed discussion of realization and performance of IGCT switching

devices for DC link converters along with a comparison with GTO devices may be found

in the literature [54]. Furthermore, series connected IGCT devices for continued converter

operation during device failures in such applications to enhance system reliability have

also been demonstrated. However, such series operation requires RC networks in parallel

with the devices to ensure steady state and dynamic voltage sharing. On the basis of these

evaluations, IGCT may be concluded to be the preferable switching device for the SSSC

system.

In comparison to the DC link converter used in realizing the SSSC which involves

single quadrant switching during commutations, the switching mechanism in the

three−phase vector switching converters to realize the Ξ−controller involves

four−quadrant switching during commutations. For each throw, the commutation process

involves leaving a forward or reverse conducting state and entering a forward or reverse

voltage blocking state during turn−off and vice−versa during turn−on. The actual

161

quadrants of conduction and commutation sequence are in fact determined by the phase

of the three−phase excitation waveforms and also the operating duty ratio. Due to this

situation, the viability of including a di/dt limiting reactor for each throw and devising a

suitable mechanism for absorbing the trapped energy in a lossless and effective manner is

challenging. Therefore, the use of IGCTs in the realization of Ξ−controller is considered to

be demanding.

On the other hand, high power IGBTs are capable of operation without snubbers

for turn−on and turn−off, and are capable of operating in parallel with ease [55].

Furthermore, various laboratory prototypes of three−phase vector switching converters

have been realized using IGBTs [27, 56]. The application of a four−step switching strategy

during commutation for effective and efficient clamp−free four quadrant switching using

IGBT realizations have been demonstrated in matrix converters, and can be readily

extended to the three−phase vector switching converters [26]. Therefore, the IGBT is

chosen to be the preferred power semiconductor for realizing the Ξ−controller.

The detailed engineering design of the switch realization including appropriate

snubbers to manage the commutation, thermal management and protection features for

both the SSSC and Ξ−controller are beyond the scope of this evaluation and is not

considered in this thesis. However, the ratings and selection of particular devices and the

losses in them will be considered further in the evaluation.

6.4.2.2 Injection Transformer

The total transformer fundamental kVA ratings are the same for both types of

162

compensators as they are meant to deliver the same amount of compensation for the line.

However, the number of transformers and turn ratio of the transformers are selected on

the basis of harmonics and voltage compatibility with the power converters.

The selection of the number of transformers (T) is related to the harmonic pulse

number that can be realized across the entire series compensator, given a switching

strategy or frequency. Recommendations of acceptable harmonics injected in power

systems from power converters are specified up to the 40th harmonic [57]. As discussed

earlier, the realizations illustrated in Figure 6-1 with T=4 transformers in series, limits the

lowest harmonic numbers to be 47 and 49, thereby meeting the recommended waveform

quality levels.

The turn ratio of each transformer (n) is selected on the basis of the maximum

voltage blocking capability of the semiconductor switches, namely IGCTs for the SSSC and

IGBTs for the Ξ−controller. A more detailed discussion of this including the provision for

(n−1) reliability for each of the realization is presented in a subsequent sub−section

(Section 6.4.2.4.1). The chosen values for the turns ratio and different transformer

parameters are summarized in Table 6-3. It should also be noted that, in the case of the

SSCC, minor arrangements ought to be made in order to properly rate each winding

considering the zigzag and ∆ connections [58]. Although the current through each of the

transformers are substantially sinusoidal, as will be illustrated further, the excitation

voltage waveforms for both type of compensators contain a significant amount of

harmonics. Thus, the transformer design features will have to be modified to

accommodate this. First, the core area of the transformers will have to be derated to

163

account for the increased flux arising from the non−sinusoidal voltage waveforms in

order to prevent saturation. A core area derating factor DFφ for each of the compensators

may be defined as the ratio of the area of one half cycle of the excitation voltage

waveforms shown shaded in Figure 6-3 to the area of one half cycle of a sinusoidal

waveform with a corresponding amplitude of the fundamental component. Secondly, the

non−sinusoidal nature of the waveforms leads to variations in core losses in the

transformer [59, 60]. Various loss penalty factors corresponding to classical eddy current

losses (PFCE), excess eddy current losses (PFEE) and hysteresis losses (PFH) for each of

the compensator that accounts for any increase in core losses have been determined by

studying the excitation waveforms in each case. These derating factors and penalty

factors for the both the compensators are shown in Table 6-3 [60].

Table 6-3 Injection Transformer Rating

Rated Power: ST =3·(VINJ/T)·IINJ , Turn Ratio: n= VLS/VCS

Transmission Line Side (LS): VLS = √3 (VINJ/T), ILS = IINJ

Converter Side (CS): VCS = √3 (1/n) (VINJ/T), ICS = n IINJ

SSSC Ξ−controller

ST = 4.4(MVA), n= ¼ ST = 4.4(MVA), n= 1

VLS = 2.6(kV), ILS = 965(A) VLS = 2.6(kV), ILS = 965(A)

VCS = 10.6(kV), ICS = 241(A) VCS = 2.6(kV), ICS = 965(A)

DF (8sin / 2) /( ) 0.86φ = σ σπ = maxDF (2d ) / 0.99φ = ξ =

CEPF 8 /( ) 0.84= σπ = 2CE maxPF (4d ) /( ) 1.1= ξ =

EEPF 16 /(7 2 ) 1.44= σ = 32

CEPF (12 2) /(7 ) 1.0= ξ =

HPF 1= HPF 1=

The parameter σ, dmax and ξ are properties of the converters operating conditions

164

and therefore are properly defined in the next subsections. It may be observed from these

derating and penalty factors, that although the SSSC would require a marginally larger

core size, and larger excess eddy current losses in comparison to the Ξ−controller, it

would feature correspondingly smaller classical eddy current losses. It may be concluded

that on balance, the transformer features would be comparable for both cases.

6.4.2.3 Capacitor

As a general rule, capacitors in power converters must be selected so that the

ripple is minimized and the resonance frequency resulting from the interaction of the

capacitor and the AC side inductors is far away from the harmonics associated with the

switching process.

6.4.2.3.1 SSSC Capacitor Selection

The “Unit Capacitance Constant” (UCC) was introduced in the literature [53] as a

rule of thumb for the preliminary selection of the total capacitance value of the DC link. It

is defined as

2DC CONVUCC (1/ 2 C V ) /S= ⋅ ⋅ (Joule/MVA) (6-3)

where C, VC and SCONV represent the DC link capacitance value, the DC voltage, and the

converter’s throughput power (MVA), respectively. It is analogous to the unit inertia

constant in synchronous rotary condensers. As in Equation (6-3) each variable represents

equivalent total values, it follows that

165

DC INJV (1/ m) (1/ n) (V / T) 13.6(kV)= ⋅ ⋅ = (6-4)

CONV INJ INJS 3 V I 17.6(MVA)= ⋅ ⋅ = (6-5)

In (6-4), m = (√2/π)·sin(σ/2) is the converter gain that relates the total DC voltage to the

fundamental RMS output voltage. For ideal shunt connected reactive power compensators,

the UCC value can be quite small – in the range of 1000 to 1500 (Joule/MVA) [53, 61].

This is because the voltage source converter does not exchange any real power with the

utility and DC bus capacitance requirement for only reactive power compensation is

rather small [61]. However, for voltage source converters used in an SSSC, any line

disturbance will transiently cause real power transfer between the converter and system.

Therefore, UCC values ranging from 3000 to 6000 (Joule/MVA) are considered typical

for voltage source converters used for series reactive power compensators [16, 62, 63].

Using Equations (6-4) and (6-5) and choosing UCC=5250, the solution of (6-4) gives

C=1000(µF). However, as shown if Figure 6-2(a), the DC link in the three level neutral

point clamped converter is actually realized using two capacitors connected in series.

Therefore, the ratings for each capacitor are,

1 2C C 2C 2000( F)= = = µ (6-6)

DC1 DC2 DCV V V / 2 6.8(kV)= = = (6-7)

The RMS current through the DC capacitors can be computed analytically in terms of IINJ

considering the converter’s switching function [51] and the phase−shift introduced by the

166

various transformers,

RMSDC INJ

1 3 6 3 5 2 1 3 6 3 3 3 2 3I [( ) ( ) cos ] I

2 16 4 16 2 4 4 4 2= ⋅ + + + ⋅π + + + + ⋅ σ ⋅

π (6-8)

At full compensation it turns out to be RMSDCI 130(A)= .

6.4.2.3.2 ΞΞΞΞ−−−−Controller Capacitor Selection

In this case, as all variables are AC, the selection of the capacitance value is

directly determined by the amount of compensation required by the transmission line. For

security reasons, the operation of the PWM switches is usually restricted to dmin<d<dmax,

so the targeted increase in the line power should be achieved at d=dmax. Typical values

for dmin and dmax are 10% and 90%, respectively. Considering the realization shown in

Figure 6-1(b), the capacitance of each individual capacitor bank can be computed as

2 2max

P INJ INJ

T (d ) nC 1360( F)

(2 F )V / I

⋅ ⋅= = µ

π (6-9)

where FP=60(Hz) is the line frequency. As the capacitor is by nature a voltage−stiff

variable, the voltage across it can be assumed to be harmonic−free and therefore the RMS

value can be computed as,

C max INJV (1/ d ) (1/ n) (V / T) 1.7(kV)= ⋅ ⋅ = (6-10)

On the other hand, the capacitor current is a switched variable so the RMS value has to

167

account for both the fundamental as well as the harmonics generated from the switching

process. From the converter’s switching functions, the RMS capacitor current can be

computed a

RMSC max INJI d n I 915(A)= ⋅ ⋅ = (6-11)

On the other hand, the fundamental component alone, as computed from Equations (6-9)

and (6-10) is

C C P max INJI V (2 F ) C d n I 869(A)= ⋅ π ⋅ = ⋅ ⋅ = (6-12)

The amount of stored energy is a rough measure of the physical size of the capacitors and

may be determined from the voltage and capacitance ratings. Table 6-4 summarizes the

capacitor requirements for each compensator.

Table 6-4 Capacitor Requirements Summary

SSSC Ξ−Controller

Capacitance (µF) 2000 1360 Voltage (kV) 6.8 (DC) 1.7 (RMS AC) Rms Current (A) 130 915 Number of Capacitor Banks 2 12 Total stored energy capacity (kJ) 92.48 47.16

Computer simulations have shown that in the SSSC case and the Ξ−controller case, these

choices for the capacitance leads to acceptable voltage ripple with no resonant

interactions.

168

6.4.2.4 Converter

6.4.2.4.1 Semiconductors Ratings

High power semiconductor datasheets usually specify the maximum voltage a

device can block, the maximum average on−state current and the maximum controlled

interruptible current. Analytical formulas to express these requirements in terms of the

compensation level have been developed and are presented in Table 6-5, along with the

numerical values for the case study system.

In addition, any realization of switch using discrete power semiconductors needs

to account for continued operation during possible failures. This generally requires a

parallel and/or series connection of power semiconductors, typically with ‘n−1’

reliability. Parallel connected devices are able to ride−through an open circuit failure,

while series connected devices are able to withstand a short circuit failure, if the

remaining devices in the realization have adequate margins of safety. This leads to the

choice of series connected string of IGCTs for the SSSC and a parallel connected IGBTs for

the Ξ−controller. Since IGCTs have been readily available as press−packs and IGBTs have

been readily available as planar modules, the choice naturally fits the ride−through

criteria. Such realizations have been demonstrated and definitively evaluated in previous

investigations [54, 55].

A simplified schematic of the switch realization is shown in Figure 6-6. The

blocking voltage / conducting current capability of each of these arrangements under

normal operation as well as under ‘n−1’ contingency are summarized in Table 6-6. These

169

may be compared against the converter operating requirements listed in Table 6-5. Table

6-7 shows the device count for each compensator. As can be seen, although the device

count for the SSSC largely exceeds the Ξ−controller, total semiconductor MVA required is

only 60% higher.

Figure 6-6 Switch realization in terms of real semiconductors. For the SSSC, 4 series IGCT with antiparallel diode (ABB 5SHX 08F4510) are used. The clamping diode is also realized using 4 diodes in series (ABB 5SDF 03D4502). For the Ξ−controller, 3 parallel IGBT with antiparallel diode (EUPEC FZ600R65KF1) are

used.

Table 6-5 Devices Stress

sssc Ξ−Controller

Blocking Voltage VDC/2 = 6.8(kV) √3·√2·VC=4.2(kV)

Max. Ave.

On−State Current INJ2n I (cos 1)

2 2

σ⋅ ⋅ +

π=58(A)

INJ2n I

2⋅ ⋅ ⋅ ξ

π=390(A)

Notes: maxsin(2d 1) / q1

sin / q

− πξ = +

π

q= FSW / FP =12

Max. Switching

Current INJ2 n I sin2

σ⋅ ⋅ =339(A) INJ2 n I⋅ ⋅ =1360(A)

170

Table 6-6 Devices Capability

SSSC

4 Series IGCT−Diode Ξ−Controller

3 Parallel IGBT−Diode

Normal Operation

Blocking Voltage 4·2.8 = 11.2(kV) 6.5 (kV)

Max. Ave. On−State Current 250 (A) 3·600 =1800(A)

Max. Switching Current 630 (A) 3·1200=3600(A)

n−1 Contingency

Blocking Voltage 3·2.8 = 8.4(kV) 6.5 (kV)

Max. Ave. On−State Current 250 (A) 2·600 =1200(A)

Max. Switching Current 630 (A) 2·1200 =2400(A)

Table 6-7 Device Count

Device SSSC Ξ−Controller

IGBT − 72

IGCT 192 −

Diode 288 72

Total semiconductor MVA 561.6 336

6.4.2.4.2 Device Losses

Typically, semiconductor losses are categorized as conduction loss and switching

loss. The former occur during the semiconductor’s on−state while the latter take place at

the transition from on−state to off−state (or vice−versa).

The conduction loss for diodes as well as for IGBT and IGCT is usually modeled by

the product of the voltage drop across the device and the current through it. If the voltage

drop is approximated by a linear dependence on the current

171

ON ON 0 ON ONV (I ) V r I= + (6-13)

then, it readily follows that the average power loss can be determined as

2ON 0 ONave ON ONrmsP V I r I= + (6-14)

The on−state voltage V0 and rON are usually available on the device datasheet. On the

other hand, the switching loss depends on the energy dissipated at every switching event.

The switching energy is usually assumed to be proportional to the blocking voltage and

the conducting current at the switching event

R

i i iR R

EE V I

V I= (6-15)

where, ER, VR, and IR represent the reference values for the energy loss, the blocking

voltage and the conducting current. These values are usually available on the

manufacturer’s datasheets. The subindex i represents the switching event. The power loss

over a power period is computed as

P ii

P F E= ∑ (6-16)

where, the subindex i sweeps all switching events that occur during the

corresponding period. In the case of IGBT and IGCT there is loss at both the turn−on and

turn−off events. While for diodes switching loss occurs only during the reserve recovery

172

that takes place at the turn−off.

Given the symmetries encountered in the voltage and current waveforms,

analytical formulas to express the losses in terms of the compensation level have been

developed and are presented in Table 6-8.

Table 6-8 Converter Losses

Type SSSC Ξ−Controller

Conduction

C INJ

INJCE0 F0 CE F

P s 24 n I

n I2(V V ) (r r )

2

= ⋅ ⋅ ⋅ ⋅

⋅+ + +

π

C INJ

INJCE0 F0 CE F

P p 12 (n I / p)

(n I / p)2(V V ) (r r )

2

= ⋅ ⋅ ⋅ ⋅

⋅+ + +

π

Switching

INJ INJS P

ON OFF RRR R R R R RON ON OFF OFF RR RR

3 V IP F

2

E E E4 4 6V I V I V I

π= ⋅

+ +

INJ INJS P

ON OFF RRR R R R R RON ON OFF OFF RR RR

2 2cosd cos(1 d)

V I q qP F 3q 9

2d sinq

E E E

V I V I V I

π π − ⋅ = ⋅ + ⋅π

+ +

Notes: 1) Subindex CE refers to IGBTs and IGCTs and subindex F refers to diodes 2) s is the number of IGCTs connected in series 3) p is the number of IGBTs connected in parallel

In order to illustrate the development of these formulas, the situation presented in

Figure 6-7 may be considered. The top plot shows the Phase−A pole current along with

the pole voltage. Depending on the throw connected to the pole is, the pole current flows

through different semiconductors. The waveforms of current carried by the different

semiconductors for the positive half cycle of the current is shown in the various plots.

The labels are consistent with Figure 6-2 and Figure 6-3. Table 6-9 summarizes the

semiconductors’ active states for an entire cycle of the current.

173

IAVA

IA

VA

(a) (b)3600

t (deg)

180 3600

t (deg)

180

Figure 6-7 Pole current breakup. (a) SSSC, (b) Ξ−controller.

Table 6-9 Active state for semiconductors

SSSC Ξ−controller

VDC1 VDC2 N VCA N

IA>0 T1A T2A D3A D4A DC1A T2A IA>0 T1A T2A

IA<0 D1A D2A T3A T4A DC2A T3A IA<0 D1A D2A

As established by Equations (6-13) through (6-16), the calculation of losses

involves computing an average or RMS quantity, or the identification of a switching

instant, for waveforms such as the ones presented in Figure 6-7. Once these waveforms

are described analytically, then the formulas for the losses are easily computed using the

definitions of Equations (6-13) through (6-16). As an example, Table 6-10shows the

analytical description for the current through T1A.

Table 6-10 Analytical description for IT1A

SSSC Ξ−Controller

T1A AˆI I sin( t)= ω

( ) / 2 t ( ) / 2π−σ < ω < π+σ

T1A AˆI I sin( t)= ω

i 2 / q t (i d) 2 / q⋅ π < ω < + ⋅ π

i=0..q/2

174

These formulas can further be integrated and/or summed in order to obtain the

final formulae presented in Table 6-8. Table 6-11 shows the numerical values of loss

distribution for a typical operating point given by PL=160(MW). In order to achieve such

operating point, the compensators need to inject QINJ=7.7(MVAr). It can be seen that the

total converter losses are very similar for each approach, and they represent about 1% of

the converter’s throughput power. In addition, the power loss in the transmission line is

in the order of few megawatts, so the losses added by the converter represent a very small

fraction of the losses of the entire system.

Table 6-11 Converter Losses for PL=160(MW), QINJ=7.7(MVAr)

SSSC (kW) Ξ−Controller (kW)

Conduction Diode 36.0 14.1

Conduction IGCT/IGBT 21.0 18.9

Turn−on 0.4 23.5

Turn−off 4.8 13.9

Reverse Recovery 3.7 6.3

Total 65.9 76.7

6.4.2.4.3 Waveform Quality

Figure 6-8 shows typical injected waveforms for each compensator. The IEEE Std.

519−1992 [57] establishes that for the power level involved in this case study, the total

harmonic distortion (THD) for the bus voltage should be <2.5% and <10% for the line

current. As can be seen in Table 6-12, the injected voltage’s THD does not meet the

values established by the standard, but this is a differential voltage. The actual

175

line−to−ground voltages (V1 and V2 in Figure 6-4) as well as the line current are well

below the value established by the standard.

Table 6-12 Total Harmonic Distortion (THD)

Variable SSSC (%) Ξ−Controller (%)

VINJ 3.60 17.50

IL 0.01 0.04

V1 0.30 0.60

V2 0.10 0.20

Figure 6-8 Voltage/Current injected into the transmission line. (a) SSSC, (b) Ξ−controller.

6.5 Dynamic performance evaluation

6.5.1 Dynamic Modeling

The dynamic equivalent circuits presented in Figure 6-9 can be used to develop

the state space model for each compensator. These circuits are a generalization of the

steady state equivalent circuit presented in Figure 6-5. It should be noticed that only the

interaction between fundamental quantities is considered, so the resulting state space is a

176

dynamic phasors−based model [35, 51].

VDC

+

IDC

-

+ -VINJ

IL

+

m VDC

-m IL

IC

VC

+

-

+ -VINJ

IL

+

d VC

-d IL

(a) (b)

Figure 6-9 Dynamic equivalent circuits. (a) SSSC, (b) Ξ−controller.

In the SSSC case, the converter gain is a phasor quantity defined as

Lm m ( I 90 )= ∠ ± +α

∢ (6-17)

where, α is the control angle that allows charging/discharging the capacitors in order to

achieve the desired compensation. In the Ξ−controller case, the duty ratio, d, provides the

means to vary the compensation level.

6.5.2 Control Structure

Section 6.4.1 has shown that both the SSSC and the Ξ−controller can operate in

voltage, impedance or power control mode. The operation under power control mode has

been chosen in order to illustrate the regulator design process.

Figure 6-10 shows the control structure for each compensator under power

control mode. As can be seen, the main loop that allows the line power to be set to a

reference value is the same in both cases. In order to compute the instantaneous value of

the line power, the voltage/current at location V2 are measured, transformed into the dq

coordinates and processed through a first order filter. This allows computation of the line

power as PL=VdId+VqIq. The value of PL is then passed through a feedback gain and

177

compared to the reference power P*. The error signal generated is processed through a

regulator to finally obtain the control variable of each compensator (α, d).

Figure 6-10 Feedback control loop. TS=5 (ms), β=10

-6. (a) SSSC, (b) Ξ−controller.

In the case of the SSSC two additional inner loops are necessary to operate the

converter. As shown in Figure 6-10(a), a phase−lock−loop is needed to assure that the

injected voltage is in quadrature with the line current. In addition, a voltage equalizing

algorithm is needed to ensure that the DC capacitors share the same voltage. Details of the

implementation of such an algorithm are presented in Figure 6-11 and discussed in the

literature [53].

Figure 6-11 Dc voltage equalizing algorithm.

178

6.5.3 Regulator Design

The procedure for the design of the feedback regulator was extensively discussed

in Chapter 5. The same approach is used here for both the SSSC and the Ξ−controller. The

transfer functions g(s)=PL/α for the SSSC and g(s)=PL/d for the Ξ−controller are both

nonlinear functions so small−signal transfer functions linearized around a typical

operating point are actually considered in the design process. Figure 6-12 illustrate the

design process: T(s) is first deployed without compensation (T(s)=β·g(s)). Next, adequate

regulators h(s) are introduced in order to achieve acceptable gain margin (GM), phase

margin (PM) and bandwidth (BW). In the SSSC case, only proportional action is needed as

T(s) has a natural infinite DC gain [64]. In contrast, the Ξ−controller needs both

proportional and integral action in order to achieve adequate performance. Table 6-13

summarizes the particulars of each design.

-100

-50

0

50

100

150

200

10-1

100

101

102

103

0

90

180

270

Freq (Hz)

SSSC Bode Diagram

g(s)|

h(s)g(s)|

g(s) h(s)g(s)

PM=84o

BW=1.8(Hz) GM=20(dB)

10-1

100

101

102

103

-180

0

180

360

-100

-50

0

50

100

150

200

Freq (Hz)

-Controller Bode Diagram

g(s)|

h(s)g(s)|

g(s)PM=86o

BW=1.7(Hz)GM=16(dB)

h(s)g(s)

(a) (b)

Figure 6-12 Small signal frequency response of loop gain of (a) SSSC, (b) Ξ−controller.

179

Table 6-13 Regulator Design Results

Variable SSSC Ξ−Controller

KP 3.7 10-3 3.0 10-7

KI 0 0.16

GM (dB) 20 16

PM (deg) 84 86

BW (Hz) 1.8 1.7

6.5.4 Command Response

Figure 6-13 shows the system response upon changes in the commanded power.

The top trace shows the changes applied to the reference power along with the response

of the line power. The line current, capacitor voltage and the control variables are also

shown in the figure. The comparison of Figure 6-13(a) and (b) shows that the SSSC and

the Ξ−controller respond in a very similar manner, as predicted by similar values of GM,

PM and BW.

160

170

1.1

1.2

0.6

1

1 2 3 4 560

80

Time (sec)

Instantaneous Line Power

Duty Ratio

Instantaneous Line Current

AC Link Voltage

PREF

PMEAS

160

170

1.1

1.2

0.4

0.8

1 2 3 4 5-3

0

3

Time (sec)


Control Angle


DC Link Voltage

PREF

PMEAS

(a) (b)

Figure 6-13 Computer simulation waveforms illustrating response to command changes. (a) SSSC, (b)

Ξ−controller.

180

6.5.5 Disturbance Response

In order to test the ability of the SSSC and the Ξ−controller to maintain control

upon system’s changes, two types of disturbances are considered. Figure 6-14 shows the

system’s response when a voltage sag/swell at the sending end bus occur and when

disturbances on the transmission angle take place. These are four independent events that

have been plotted together for convenience. The two top plots show the disturbances

while the two bottom ones show the response of the line power and the line current,

respectively. The response of the Ξ−controller and the SSSC response are similar to each

other.

0.95

1

17

20

150

160

170

1 2 3 4 51

1.1

1.2

Time (sec)

Voltage Disturbance

Transmission Angle Disturbance

PREF

PMEAS

SagSwell

Decrease Increase



0.95

1

17

20

150

160

170

1 2 3 4 51

1.1

1.2

Time (sec)

Voltage Disturbance

Transmission Angle Disturbance

PREF

PMEAS

SagSwell

Decrease Increase



(a) (b)

Figure 6-14 Computer simulation waveforms illustrating response to bus voltage and angle disturbances.

(a) SSSC, (b) Ξ−controller.

6.6 Summary

This chapter has presented an analytical comparative evaluation of a modern DC

link based power flow control device, namely the Static Synchronous Series

Compensator and one of the devices introduced in this thesis, namely the Ξ−controller.

181

Although these approaches represent radically different principles of operation to realize

reactive series compensation for power flow control, they feature similar functional

capabilities.

Extensive analytical formulations that determine the various design elements have

been developed in this chapter. They have been used to realize a benchmark case study to

provide numerical values for various design features. The measures of comparison that

have been presented in various tables in the chapter include: transformer ratings,

capacitor ratings, semiconductor ratings, semiconductor losses, waveform quality indices

and dynamic control properties. The analytical solutions and operation of both the

designs have been verified using detailed computer simulations. Selected computer

simulation results that compare the performance have been presented in this chapter.

Based on the comparison of the results from the case study, it may be concluded

that suitably designed DC link and AC link approaches are both competitive against each

other in realizing series power flow control. The DC link approach requires about twice as

much capacitive energy storage and about 66% additional power semiconductor MVA

rating, while the AC link approach has about 15% more losses in power semiconductors,

using state of the art semiconductor devices. All other summative measures indicate

similar levels of steady state and dynamic performance.

182

Chapter 7 Experimental

Verification of the Γ−Γ−Γ−Γ−Controller

7.1 Introduction

This chapter describes efforts aimed at experimentally proving the concept of

using a vector switching converter for realizing power flow control. Out of the Π, Ξ and

Γ controllers introduced in Chapter 3, the Γ−controller was selected for experimental

verification as it can be considered the most general case. The reason for this is twofold:

(i) the circuital interconnection involves a shunt−series arrangement and (ii) the converter

involves the realization of a multiple−throw switch.

Figure 7-1 shows a schematic of the system implemented in the laboratory.

AC link VESCSITSPT Transmission

Line

VS S

Bus S

VR R

-Controller

Bus R

Figure 7-1 Schematic of the Γ−controller system implemented in the laboratory.

Notice that the above figure strongly resembles Figure 3-20, which was use to introduced

the Γ−controller in Section 3.4. The following sections describe the experiment layout,

183

along with experimental waveforms contrasted against computer simulation results.

7.2 Experiment Layout

As explained in Chapter 3, the Γ−controller operates embedded into a

transmission line. Therefore, a laboratory prototype of a transmission line is discussed

first followed by a laboratory prototype of the Γ−controller itself. Also, given the

availability of resources at the laboratory, the prototype described below is conceived to

operate in a three−phase 230V/60Hz system.

7.2.1 Laboratory Prototype of a Transmission Line

A complete model of a transmission line usually includes four distributed

parameters: series resistance, series inductance, shunt conductance and shunt capacitance.

However, it is customary in power flow controller studies to consider only the effect of

the series elements. Moreover, the distributed nature of these parameters is also neglected

which leads to the representation of the transmission line as shown in Figure 1-1 i.e., as a

series combination of constant resistance and constant inductance [4]. This is

implemented with an adjustable inductor available in the laboratory. The inductor is set at

L=5.6mH and the measured series resistance is R=0.27Ω. This leads to a ratio XL/R of

7.8 which is within the typical values encountered in transmission lines. The inductor is

rated at Imax=40A.

184

Figure 7-2 Laboratory prototype of a transmission line.

As suggested in Figure 7-1, the transmission line connects busbars whose

voltages (magnitude and angle) are stiff quantities. This reflects the operation of actual

power systems where at every busbar the voltage magnitude is kept very close to its

nominal value and the power flows result mostly from angle differences between the

busbars. Figure 7-3 shows a laboratory prototype of a transmission line connecting two

busbars that properly takes into account these effects [65]. As can be seen in the figure, a

phase−shifted transformer connected in the so−called “Marserau configuration” [66] has

been introduced in order to create a transmission angle. This configuration allows

introduction of a transmission angle between the busbars without changing the magnitude

of the voltage. This is shown in the phasor−diagram accompanying the figure. The actual

value of the transmission angle θ is determined by the windings turn ratio. Each

transformer is rated at 230V at the primary side and 36V at the secondary side. This

allows creation of a transmission angle θ=15o.

185

H

L

n 3n

n 2 tg2

= =θ

⋅

ax

a

V / 2sin2 V

θ=

Figure 7-3 Laboratory prototype of a transmission line connecting two stiff voltage busbars.

7.2.2 Laboratory Prototype of a Γ−Γ−Γ−Γ−Controller

Figure 7-4 shows the schematic of the Γ−controller laboratory prototype. The

blocks labeled as SPT, AC link and 3T−1P 3φ VeSC were built for a different application

and in this thesis they have been adapted to operate as a power flow controller. As can be

seen, a realization with one primary and three secondary transformers is being

considered. This leads to the implementation of a triple throw single pole three−phase

vector switching converter for synthesizing the pole voltage. This topology with

Y−connected transformers was studied in detail in Chapter 2. The use of ∆−connected

transformers does not change any of the claims made in Chapter 2 whatsoever. On the

contrary, it adds to the versatility of VeSC−based topologies.

186

SPT

A

BC

Sb

Vai

Sa

Sc

Va1

Va3

Va2

Vb1

Vb3

Vb2

Vc1

Vc3

Vb2

a1

b1c1

b2

c2a2

c3

a3b3

Vbi

Vci

ACLINK3T-1P 3 VESC

SIT

Figure 7-4 Laboratory prototype of a Γ−controller.

The ratings of the main components are presented in Table 7-1.

Table 7-1 Γ−controller component rating

Item Ratings

SPT Transformer 240V/240V 6kVA

AC Capacitor 30µF 300V 4A

IGBT−Diode Modules

Fuji 1MB15D−060 600V 15A

SIT Transformer 230V/36V 5.4kVA

The IGBTs are driven by a standard DSP/FPGA/PC system developed at the University of

Wisconsin [67]. The switching frequency was randomly picked to be FSW=5kHz.

Computer simulations showed that no resonance frequencies are excited at 5kHz. The

converter is embedded in the system as shown in Figure 7-1. For completeness, the entire

system is shown again in Figure 7-5 along with a picture of the hardware built in the

laboratory in Figure 7-6.

187

Figure 7-5 Detailed laboratory prototype of a Γ−controller system.

188

Figure 7-6 Picture of hardware built at the laboratory.

7.3 Experimental Waveforms

Although the system was designed to operate at 230V, experimental waveforms

were captured with the variac set at 100V. This was for the safety of the semiconductors

because no protective devices were installed.

In reference to Figure 7-3, Equation (1-1) allows calculation of the complex

power without the Γ−controller embedded in the transmission line, which is found to be

S=1246 +j 11 (VA). This is the base power which will be subject to alterations by the

insertion of the Γ−controller.

A detailed computer simulation of the Γ−controller system shown in Figure 7-5

was implemented in order to contrast experimental waveforms against theoretical

189

predictions. Two sets of measurements are considered. A steady state case study is used

to show the internal workings of the Γ−controller operation and a dynamic case study is

also implemented in order to show the system level operation of the Γ−controller.

7.3.1 Steady Sate Operation

As mentioned in Section 7.3, the complex power flow through the transmission

line without the Γ−controller embedded is given by S=1246 +j 11 (VA). The insertion of

the Γ−controller into the transmission line allows complex flow control over a region

determined by the voltage synthesized by the converter. Figure 7-7(a) shows that this

voltage can be anywhere inside the triangle formed by the throw voltages of the

converter. However, it was explained in Chapter 3 that the interest is in symmetrical

realizations for the pole voltage and therefore the operation of the converter is limited to

the circle inscribed in the triangle.

-1 -0.5 0 0.5 1-1

-0.5

0

0.5

1

Re

Im

V1

V2 V3

800 900 1000 1100 1200 1300 1400 1500 1600 1700-400

-300

-200

-100

0

100

200

300

400

Base case

Target

P (W)

Q (VAr)

(a) (b) Figure 7-7 Attainable pole voltage (a) and the corresponding power diagram (b).

Figure 7-7(b) shows the power diagram that results from mapping the pole

190

voltage circle into the P−Q plane. The complex power to generate this diagram is

measured right before the RL branch, at location V2 in Figure 7-5. The power diagram

indicates all reachable values for the complex power that can be obtained by modulating

the duty ratios of the converter. In order to show the operation of the converter, a random

operating point specified in Table 7-2 was selected.

Table 7-2 Operating Point

Item Value

Duty ratios d1=33% d2=50% d3=17%

Voltage @ V2 (peak) V2= 81(V)

Line Current (peak) IL= 8.4 (A)

Injected Voltage (peak) Vinj= 3.8 (V)

Active Power P= 1023 (W)

Reactive Power Q= −40 (VAr)

Figure 7-8 shows the gate voltage applied to the IGBTs. The top, middle and bottom trace

shows the gate voltage applied to the IGBTs corresponding to the throws 1, 2 and 3,

respectively. It should be noted that the average value of those voltages corresponds to

the duty ratios specified in Table 7-2.

191

Figure 7-8 Experimental waveforms showing the gate voltage applied to the IGBTs.

Figure 7-9 and Figure 7-10 show the voltage at location V2 and the line current,

respectively. In both figures, part (a) shows the experimental waveforms while part (b)

shows waveforms obtained from simulations.

-125

-100

-75

-50

-25

0

25

50

75

100

125

Figure 7-9 Waveforms showing the voltage at location V2. (a) Experimental (b) Simulated.

192

-10

-8

-6

-4

-2

0

2

4

6

8

10

Time

(a) (b)

Ib

Ic

Ia

Ic

Ia

Ib

Figure 7-10 Waveforms showing the line current. (a) Experimental (b) Simulated.

In order to help the visualization, the grid from the simulated waveforms has been

made to match the division from the oscilloscope screen. The match between

experimental and simulated waveforms is evident. In the experimental case, some

unbalance between the phases is observed. This is because the inductors used to emulate

the transmission line were not exactly equal.

Figure 7-11 through Figure 7-13 illustrate the pole voltage synthesized by the

converter. Again, part (a) shows experimental results and part (b) shows the

corresponding simulated waveforms and the grid of the simulated waveforms is made to

match the divisions of the oscilloscope screen. Figure 7-11 shows the actual three−phase

switched voltages, but due to the high frequency switching process taking place the

pictures in both cases are blurry.

193

-25

-20

-15

-10

-5

0

5

10

15

20

25

Time

(a) (b) Figure 7-11 Waveforms showing the injected voltage. (a) Experimental (b) Simulated.

Thus, in order to be able to contrast these waveforms, two extra sets of plots are

presented. Figure 7-12 shows the fundamental component of the switched waveforms

depicted above and Figure 7-13 shows an experimental versus simulated comparison of

one of the phases at the switching frequency timescale. Once again, the match between

experiments and predictions made by simulations is evident.

-25

-20

-15

-10

-5

0

5

10

15

20

25

Figure 7-12 Waveforms showing the fundamental component of the injected voltage. (a) Experimental (b)

Simulated.

194

-25

-20

-15

-10

-5

0

5

10

15

20

25

Time

(a) (b) Figure 7-13 Waveforms showing the injected voltage at the switching frequency timescale. (a)

Experimental (b) Simulated.

7.3.2 Dynamic Operation

The previous section has shown an experimental verification of the Γ−controller

from the converter’s point of view. The intent of this section is to illustrate the operation

of the Γ−controller from the system’s point of view i.e., to show the transition between

different operating points. These ideas were discussed in Section 3.4 where the

Γ−controller was first introduced. It was shown through computer simulations that the

transitions between operating points are smooth and free of oscillation if the converter’s

duty ratios are slowly ramped from one value into another. Figure 7-14 shows an

example of this. The top trace shows the duty ratios applied to the converter. It can be

seen that the transition takes place in “one division” which corresponds to two seconds.

The next traces show, from top to bottom, the voltage at location V2, the line current and

the injected voltage, respectively.

195

Figure 7-14 Experimental waveforms illustrating the transition from one operating point to another by

means of duty ratio ramping.

As can be seen from all three traces, the transition is smooth and free of

oscillation which confirms the theoretical claim that duty ratio ramping is an appropriate

strategy for the operation of VeSC−based power flow controllers.

7.4 Summary

This chapter has been devoted to discussion of efforts to experimentally prove the

concept of using VeSC−based devices for realizing power flow control in transmission

networks. Out of the three topologies proposed in this thesis, the Γ−controller was

selected for experimental verification as it is seen by the author as the most general case.

196

A Γ−controller prototype was built and tested at the WEMPEC laboratory.

Experimental waveforms were contrasted against predictions made by computer

simulations. Several illustrative experimental waveforms were presented which very

closely matched the corresponding simulated waveforms.

Also, the idea of duty ratio ramping to change operating points was implemented

in the hardware. Once again, the results from experiments confirmed theoretical

predictions.

As mentioned above, this experiment did not include the actual measurement of

the complex power. The reason is that the laboratory does not have proper equipment to

measure instantaneous complex power, especially in the presence of harmonics and

unbalanced currents. This is indeed an ongoing research topic that is beyond the scope of

this thesis.

197

Chapter 8 Optimal Power Flow

with AC Link Power Flow

Controllers Embedded

8.1 Introduction

In the previous chapters, AC link power flow controllers were analyzed in great

detail, but the focus was on the device itself rather than its function. This chapter is

intended to give a system point of view for the problem of load flow control in electric

power systems with AC link power flow controllers embedded.

Electric power systems can be operated in a variety of ways, depending on the

specific goals to be attained. Typically, such goals may include the minimization of the

overall energy production cost of the system (economic dispatch), the minimization of

the emission of particles (environmental dispatch), the minimization of system losses, or

a combination of these goals [5]. In addition, modern power systems consist of various

control areas, so the optimization of the power exchange between them is an additional

goal that one may want to achieve. This particular issue is of special interest within the

deregulated power markets framework. This is closely related to what is referred to as

loop flow problem, as explained next [68].

Consider a power system consisting of three control areas, as suggested in Figure

198

8-1. The control areas are connected via interfaces, which correspond to a number of

transmission lines that interconnect the corresponding control areas [69]. Assume that,

initially, area A is exchanging power with areas B and C by an amount of PAB and PAC,

respectively.

Figure 8-1. A 3−area electric power system.

In addition, consider that areas A and B want to increase their power exchange by

an amount of ∆PAB, but the power exchange between areas A and C needs to be held

constant, because, for example, the interface is at its limit. In order to perform the

transaction, Area A increases its net power by ∆PAB and Area B decreases its net

production by the same amount. However, the actual flows would be as shown in the

figure. A portion of ∆PAB would effectively flow through the corresponding interface, but

some of it, a loop flow, would go through the Area C, violating the restriction of holding

the AC interface flow constant. This is because power flows are not ruled by contractual

paths but by Kirchhoff’s laws.

Loop flows, as well as the optimal dispatch problem, can be greatly improved by

embedding FACTS devices into the transmission system, as has been shown in numerous

199

publications [1, 3, 7, 69-78]. The methodology consists of developing a steady state

model for the corresponding FACTS device and incorporating this model into the

so−called Optimal Power Flow problem (OPF).

Next, the standard OPF problem is formulated followed by its adaptation when

Ξ−controllers are present. A case study is also discussed.

8.2 Standard OPF

The standard optimal power flow [5] is formulated as follows:

Objective Function

),V(fOptimize bb θ Bb∈ B: All system Buses (8-1)

Equality Constraints

Lgbbg P),V(PP +θ= Gg∈ G: Generation Buses (8-2)

Lgbbg Q)θ,V(QQ += (8-3)

),V(PP bbLd θ= Dd∈ D: Load Buses (8-4)

),V(QQ bbLd θ= (8-5)

Inequality Constraints

maxbb

minb VVV ≤≤ (8-6)

maxbb

minb SSS

θ≤θ≤θ SS Bb ∈ BS: Same as B excluding slack bus (8-7)

maxgg

ming PPP ≤≤

(8-8)

maxgg

ming QQQ ≤≤

Gg∈ (8-9)

maxlbbl S|)θ,V(S| ≤ Ll∈ L: Transmission Lines (8-10)

200

The state of a power system is fully defined by the magnitude and angle of the

bus voltages, Vb’s and θb’s, so they are used as explicit variables in the problem

formulation.

Equation (8-1) represents the objective function to be optimized. In the economic

dispatch case, it corresponds to the minimization of the energy production costs

summation,

∑g

bbgg ))θ,V(P(CMin Gg∈ (8-11)

where Cg represents the cost function of the various generators. If the goal is to maximize

the power exchange through an interface, the objective function becomes,

∑ θi

bbi ),V(PMax Ii∈ (8-12)

where I represents the set of transmission lines belonging to the interface. Other objective

function can be readily formulated; and via the Pareto’s optimality criterion [76],

multiple objective functions can be pursued.

The equality constraints described by Equations (8-2) through (8-5) represent the

power flow equations that dictate the physical restrictions of the problem. They force a

balance between the power injected into the network by the generators and the power

demanded by the loads plus the transmission losses.

201

Finally, the inequality constraints described by Equations (8-6) through (8-10)

represent the operational limits of the various components. Equations (8-6) and (8-7) say

that every bus in the system has to operate within acceptable voltage ranges. Equations

(8-8) and (8-9) dictate the capacity limits for generators. Lastly, Equation (8-10) specify

the most important restriction within the FACTS context, saying that transmission lines

have a limited capacity to carry power. This transmission line limit can be expressed in

terms of either current, active power, or apparent power. The last approach is chosen

here.

8.3 OPF with ΞΞΞΞ−−−−controllers embedded

8.3.1 The model

The steady state model for the Ξ−controller readily follows from its equivalent

circuit. Aggregating the distributed parameters of Figure 3-14, the following simplified

model can be obtained,

Figure 8-2 Simplified Equivalent Circuit for the Ξ−controller.

where )LLL(X TRSPL ++ω= , RSL RRR += , and C/1X PC ω= . Thus, the overall

transmission line impedance can now be thought of as,

202

)XdX(jRZ C2

LL −+= (8-13)

The additional degree of freedom introduced by the controllable variable d can be

interpreted as having a tunable line reactance within range LCL XXXX ≤≤− . Once the

value for X has been determined, the corresponding duty ratio can be calculated as,

C

L

X

XXd

−= (8-14)

8.3.2 OPF Formulation

The OPF problem for a power system with Ξ−controllers embedded can be

formulated as follows,

Objective Function

)X,,V(fOptimize bb ξθ Bb∈

Ξ∈ξ

B: All system Buses

Ξ: Lines with a Ξ−controller (8-15)

Equality Constraints

Lgbbg P)X,,V(PP +θ= ξ Gg∈ G: Generation Buses (8-16)

Lgbbg Q)X,,V(QQ +θ= ξ (8-17)

)X,,V(PP bbLd ξθ= Dd∈ D: Load Buses (8-18)

)X,,V(QQ bbLd ξθ= (8-19)

203

Inequality Constraints

maxbb

minb VVV ≤≤ (8-20)

maxbb

minb SSS

θ≤θ≤θ SS Bb ∈ BS: Same as B excluding slack bus (8-21)

maxgg

ming PPP ≤≤

(8-22)

maxgg

ming QQQ ≤≤

(8-23)

maxlbbl S|)X,,V(S| ≤θ ξ Ll∈ L: Transmission Lines (8-24)

ξξξξ ≤≤− LCL XXXX (8-25)

Equations (8-15) through (8-24) have the same interpretation as in the standard

OPF formulation, but now they feature an extra degree of freedom introduced by the

explicit variables Xξ. Equation (8-25) forces the corresponding duty ratios for Xξ to be

within admissible range ( 1d0 ≤≤ ξ ).

When control areas are present, additional constraints in the form of inequalities

or equalities can be added on the corresponding interfaces in order to satisfy operating

restrictions. For example, to avoid the loop flow between areas A and B in the

introductory discussion, the following equality constraints can be added,

Additional Equality Constraints

∑ =θi

ACbbi P),V(P ACIi∈ IAC: AC Interface (8-26)

∑ =θi

BCbbi P),V(P BCIi∈ IBC: BC Interface (8-27)

where PAC and PBC represent pre−established values for the total power exchange

204

between the areas.

The OPF problem described above was implemented in the MATLAB environment.

It clearly corresponds to a non−linear optimization problem. The optimality conditions,

known as Karush−Kuhn−Tucker (KKT) conditions, are obtained by successively

approximating the objective function by a quadratic function and the constraints by linear

functions. This problem, known as a quadratic programming (QP), is solved by standard

methods described in the literature [79, 80].

As will become evident in the case study discussed below, the presence of the

Ξ−controllers allows for more flexible operation of the overall system, yielding better

results in the objective function pursued.

8.3.3 Amount and Location

In the OPF formulation discussed above, nothing was said about the nature of the

set Ξ (the set of transmission lines containing Ξ−controllers), in terms of how many

devices should be used and where to locate them. The number of controllers as well as

the allocation within the system has been the subject of many publications throughout the

last few years [69, 74, 78, 81, 82]. Results vary depending on the objective function to be

pursued and the nature of the controller considered. This topic however, is beyond the

scope of this thesis. In addition, since the Ξ−controller is functionally similar to the SSSC

and TCSC, previous studies for these devices can be utilized for this purpose.

205

8.3.4 Case Study

In order to appreciate the flexibility resulting from the presence of the

Ξ−controller, consider the IEEE 39−bus system sketched in Figure 8-3. This system

represents a simplification of the New England interconnection, in the Northeastern U.S.

The 39−bus system has 10 generators, 19 loads, 35 transmission lines and 12

transformers. In addition, the system is organized into three areas. The complete set of

data is presented in Appendix 5.

32

10

13

12

14

11

6

31

4

39

5

7

8

9

Area C

15

16

28

21

29

38

35

22

24

23

19

20

34 33

36

Area A27

26

25

37

18

17

30

2

1

3

Area B

IAB

IBC

IAC

Lines Generators

Buses Loads

Figure 8-3 The IEEE 39−bus system.

The study considers the economic dispatch OPF and the interface power

maximization OPF separately. In each case, the results obtained with the system as is i.e.,

206

without any Ξ−controller, are compared against the results obtained with a fully

controlled system i. e., with a Ξ−controller embedded in every transmission line. The

amount of maximum compensation for each Ξ−controller is assumed to be 50% of the

corresponding transmission line reactance. Thus, the value of the equivalent reactance of

each line can vary within the range,

LL XX2

X≤≤ ξ L∈ξ L: Transmission Lines (8-28)

8.3.4.1 Economic Dispatch

For the economic dispatch OPF, Equation (8-11) describes the objective function.

The cost function for each generator is assumed quadratic, as shown in TABLE II,

Appendix 5.

(i) Results without Ξ−controllers embedded

Objective function: 98,674 ($/h)

Table 8-1 Active Constraints

Bus Generator Line Max V Min V 38 20, 30, 33, 36

Max P Max Q Min Q 30, 31, 32, 36, 37, 38, 39

31, 32, 39

Max MVA 16-17

Since this case will be used as base case for the interface power maximization

discussion, these results are also provided,

207

Table 8-2 Interface Flows

A−B A−C B−C Line Rating

(MVA) P

(MW) 28-26 500 181 16-17 500 499 29-26 500 232 Total 1500 912

Line Rating (MVA)

P (MW)

15-14 500 178 Total 500 178

Line Rating (MVA)

P (MW)

1-39 500 363 3-4 500 102 Total 1000 465

In the above table, the total values represent the power exchange between the

corresponding control areas.

(ii) Results with Ξ−controllers embedded

Objective function: 80,106 ($/h)

Table 8-3 Active Constraints

Bus Generator Line Equivalent Impedance Max V

Min V

10, 19, 22, 25, 29, 36

Max P

Max Q

Min Q

30, 31, 33, 36, 37, 38, 39

31

Max MVA 16-17

Max Min 2-3, 2-25, 3-4, 4-5, 10-13, 13-14, 17-27, 21-29, 25-26, 16-17, 19-20

3-18, 4-14, 5-6, 6-7, 7-8, 8-9, 9-39, 14-15, 15-16, 16-19, 16-21, 16-24, 17-18, 21-22, 22-23, 28-29, 12-13, 6-31, 23-36

For this case, Equation (8-28) is added into the OPF formulation. As can be seen,

embedding Ξ−controllers into the transmission lines leads to a reduction of almost 20%

in the operation cost of the overall system. An adequate economic evaluation based on

the cost benefit ratio (C/B) would give insights about whether it is worth it to invest in

208

these devices [83, 84].

In addition, the active constraints on the equivalent impedance of the lines give

valuable information about the real need of Ξ−controllers. Thus, as may be implied from

Equation (8-25), the equivalent impedances at their maximum limit are not receiving any

compensation from the Ξ−controllers whatsoever and may therefore be eliminated.

Similarly, equivalent impedances at their minimum limit are receiving 100% of

compensation indicating a potential need for an even larger compensator.

Finally, although the active constraints on the bus voltages and generators have

changed, the interface AB remains congested, limiting Area B from obtaining cheaper

power from Area A. This leads to the next discussion on power exchange between

control areas.

8.3.4.2 Interface Power Maximization

As was seen in the previous case study, the transmission line 16-17 is acting as a

bottleneck binding further power exchange from Area A to B. Say the interest is in

somehow increasing the power transfer through the Interface AB. However, due to

contractual paths restrictions [71], this must be done while keeping the power exchange

between Areas A and C and Areas B and C at their nominal values specified in Table 8-2.

For the situation described above, Equation (8-12) describes the OPF objective

function while Equations (8-26) and (8-27) force the total power exchange through

interfaces AC and BC to remain constant.

209

(i) Results without Ξ−controllers embedded

Objective function: 968 (MW)



(MVA) P

(MW) 28-26 500 209 16-17 500 499 29-26 500 260 Total 1500 968

Line Rating (MVA)

P (MW)

15-14 500 178 Total 500 178

Line Rating (MVA)

P (MW)

1-39 500 363 3-4 500 102 Total 1000 465

As can be seen, although it is possible to boost the A−C power transfer without

using controllable devices, the actual increase is 56(MW), only a 6% of the nominal

value.

(ii) Results with Ξ−controllers embedded

Objective function: 1288 (MW)



(MVA) P

(MW) 28-26 500 368 16-17 500 499 29-26 500 421 Total 1500 1288

Line Rating (MVA)

P (MW)

15-14 500 178 Total 500 178

Line Rating (MVA)

P (MW)

1-39 500 454 3-4 500 11 Total 1000 465

210

As in the previous case study, a considerable improvement in the objective

function is now observed. The power exchange has been boosted by 376(MW), a 41%

with respect to its nominal value. Notice that the flows through the Interface BC have

readjusted but the total exchange has remained constant.

8.4 Summary

This chapter has given a system point of view for AC link power flow controllers.

It has been demonstrated that, by embedding Ξ−controllers into the transmission

network, dramatic improvements can be achieved in the flexibility of operation for the

overall power system. It was shown that the system model of the Ξ−controller can be

thought as having transmission lines with tunable reactance. Using the IEEE 39−bus

system as an example, typical operational issues were addressed. Specifically, the

optimal power flow formulation showed that the economic operation as well as the loop

flow problem can be greatly improved by adding the extra degree of freedom provided by

Ξ−controller.

211

Chapter 9 Conclusions and Future

Work

This thesis has introduced a new family of FACTS devices: the Π−controller, the

Ξ−controller and the Γ−controller. Based on the vector switching converter (VeSC), these

devices feature similar functional characteristics to those encountered in the voltage

source HVDC interties, the Static Synchronous Series Compensator (SSSC) and the Unified

Power Flow Controller (UPFC), respectively. The control function, however, is realized

by direct AC↔AC conversion without frequency change, adopting the strategy of pulse

width modulation (PWM).

A comprehensive analysis of each of these devises has been performed, including

operating principles, equivalent circuits, design considerations, and dynamic modeling

and control. Computer simulations of illustrative examples were executed to validate the

approach. Due to the level of power involved, it was concluded that the Π−controller

may not be practical with the current state−of−the−art gate turn−off semiconductors.

However, the Ξ−controller and Γ−controller would be able to compete with their DC link

counterparts. A case study for series compensation has shown the Ξ−controller is indeed

favorably comparable to the SSSC.

The dynamic modeling for these devices was accomplished using generalized

212

averaging theory. This approach, in contrast with the traditional dynamic phasors model,

explicitly incorporates the switching frequency into the state space model, and therefore

is able to predict oscillatory behavior of the state variables due to switching and thus

preclude potential instabilities in cases when there are system modes in the vicinity of the

switching frequency. It was also shown that it can be used for design purposes, as it can

predict component stress levels as RMS quantities with a higher degree of accuracy than

the traditional model.

Feedback control of power flow using the proposed devices was also investigated.

For the Ξ−controller case, it was shown that closed loop regulation can be approached by

means of classical control design techniques, such us Bode plots and Nyquist’s stability

criterion. For the Γ−controller, however, more sophisticated techniques are needed.

A laboratory prototype of the Γ−controller developed at the WEMPEC laboratory

has proved further the real viability of the use of VeSC−based topologies for power flow

control. Laboratory results indicate excellent agreement with the analytical predictions

and computer simulations.

Finally, a system point of view was given, incorporating the Ξ−controller into an

Optimal Power Flow (OPF) program. It was shown that the Ξ−controller adds extra

flexibility to the OPF program and dramatically improves the objective function for

different goals pursued.

213

9.1 Contributions

The main contribution of this thesis is the introduction of AC link VeSC-based power

flow controllers. Within this context, several specific contributions are enumerated

below.

9.1.1 Modeling and control

• Development of equivalent circuits based on controlled sources as presented here

allows easy representation of VeSC-based topologies for circuit analysis, computer

simulations, steady state and dynamic interaction between the converter and the

rest of system, and sizing the various components (capacitors, semiconductors,

transformers).

• Novel approach for dynamic modeling based on generalized averaging theory

applicable to VeSC-based topologies when the ratio between switching frequency

and power frequency is an integer number leads to capturing the oscillatory

behavior of the state variables when the switching process excites the physical

resonances.

• The development of the small signal loop gain of the power flow control permits

application of classical feedback control design with ease.

9.1.2 Computer simulation

• Switched simulations modeling the switches as switching function−controlled

sources allow capturing the dynamic of the switching process and can be used to

214

estimate the behavior of the converter during commutation events. The main

drawback of switched simulations is the relatively long time they take to run.

• Averaged simulation modeling the switches as duty ratio−controlled sources are

useful when the interest is in the interaction between the fundamental quantities

only. They can be used to test the selection of feedback control gains and for

system level dynamic behavior. They run much faster than switched simulations.

9.1.3 Comparison against the state−−−−of−−−−the−−−−art technology for

series compensation

A detailed comparison between the SSSC and the Ξ−controller was performed.

The particulars considered in the comparative evaluation are as follows:

• Detailed design considerations of power circuit components − capacitors and

semiconductors

• Topological approach integrating transformers and appropriate modulation

techniques for meeting benchmark harmonic performance levels.

• Semiconductors loss modeling using analytical techniques to allow fast

computation of thermal performance

• Injection transformer design considerations including core loss components

• Design and verification of closed loop regulator with more than adequate dynamic

performance

• Computer simulations verifying functional operation and controller performance

during command changes and disturbances.

215

9.1.4 Experimental verification

• Experimental waveforms were contrasted against computer simulation predictions.

This validated the concept of using VeSC-based topologies for power flow control.

• Experimental verification of dynamic operation via duty ratio damping.

Experiments confirmed that the best strategy to move from one operating point on

to another was via duty ratio ramping. Duty ratio ramping leads to a smooth

transition of the line current with no oscillations or overshoot.

9.1.5 System level modeling

• Incorporation of AC link VeSC-based series power flow controllers into the optimal

power flow problem. It was shown that by embedding VeSC-based series power

flow controllers in the transmission lines, a much flexible operation of the system

is achieved.

9.2 Proposed Continuing Research

Several opportunities for future investigation have been identified that would

provide valuable extensions of the research conducted in this thesis.

9.2.1 Feedback Control for Γ−Γ−Γ−Γ−controller

The problem of power flow control using the Γ−controller being a MIMO system

with multiple degrees of freedom was stated in Section 5.3 referring to Figure 5-10 [48].

216

The aim is to find an appropriate regulator that can guarantee stable operation of the

overall system as well as an adequate dynamic performance, in terms of DC error, speed

of response, overshot and oscillations. Since the Γ−controller has been conceived as a

complex power flow controller, a proper method to measure instantaneous three−phase

reactive power in the presence of harmonics is seen as a critical part of the

implementation of the feedback regulator. Advanced control techniques such Mode

Predictive Control (MPC) [85] and Passivity Based Control (PBC) [86] are seen by the

author as particularly suitable for developing the control structure. There are several

needs and opportunities for investigations of feedback control for the Γ−controller, as

well as other topologies.

9.2.2 OPF with embedded Γ−Γ−Γ−Γ−controllers

The development of a suitable model for the Γ−controller to be incorporated into

an OPF program. A research group at CINVESTAV in Mexico has recently initiated work on

this topic [87, 88].

9.2.3 System level dynamics

The performance of AC link power flow controllers for system level dynamics

present wide opportunities for research work. System level dynamics topics include

subsynchronous resonance damping, power oscillations damping, transient stability

enhancement, voltage stability, etc. Numerous publications have shown the performance

of DC link power flow controllers in this area [1-3, 14]. Similar studies using AC link

217

power flow controllers may reveal further tradeoffs between these two technologies. The

same Mexican group has been working on this topic as well [87].

9.2.4 Multilevel realization for the Ξ−Ξ−Ξ−Ξ−Controller

This thesis presented the Ξ−controller as a series device whose principle of

operation was based on commuting between a three−phase capacitor bank and a short

circuit node. A natural expansion of this concept that may lead to better performance is to

use multilevel converters [30] extended to AC link. This would be achieved by using one

(or more) three−phase capacitor bank instead of (or in combination with) the short circuit

node.

9.2.5 Additional topologies

This thesis has studied the use of VeSC–based AC link power flow controllers

connected in back−to−back, series and shunt−series configurations. As pointed out in the

introduction, DC link power flow controllers can be configured, in addition of these three

configurations just mentioned, as shunt (STATCOM) and series−series (IPFC) devices.

Topologies based on AC link VeSC can also be derived for these configurations, which

could bring forth a treasure−trove of research opportunities. For example, the AC link

VeSC−based shunt configuration was studied for a flicker mitigation application [89].

This topology can readily be extended to operate as an AC link STATCOM.

218

9.2.6 Field demonstration

It is the hope of the author that the ideas discussed in this thesis may become a

reality through a field demonstration in a utility power system. This thesis has established

that this technology is viable and the natural continuation of this work would be the

actual construction of a utility scale AC link VeSC−based power flow controller.

219

Appendix 1 Parameters for the

Π−Π−Π−Π−controller case study

TABLE I

SYSTEM PARAMETERS

Symbol Per unit value

Actual value 110kV 100MVA

60Hz VS 1 110kV RS 0.01 1.21 Ω XS 0.17 54.5 mH VR 1 110kV RR 0.01 1.21 Ω XR 0.17 54.5 mH FP 1 60 Hz

TABLE II TRANSFORMER STP PARAMETERS

Symbol Per unit value Actual value

110/11/6.3/11/6.3kV 180MVA 60Hz

VP 1 110kV RP 0.001 0.2 Ω XP 0.01 5.3 mH VS1 1 11kV RS1 0.001 2 mΩ XS1 0.01 53 µH VS2 1 6.3kV RS2 0.001 0.67 mΩ XS2 0.01 18 µH VS3 1 11kV RS3 0.001 2 mΩ XS3 0.01 53 µH VS4 1 6.3kV RS4 0.001 0.67 mΩ XS4 0.01 18 µH

TABLE III FILTER CAPACITOR FTC PARAMETERS

Symbol Per unit value Actual value

11 kV 100MVA 60Hz XC 3 730 µF

TABLE IV TRANSFORMER BIT PARAMETERS


Actual value 5.5/110 kV 180MVA

60 Hz VP 1 5.5 kV RP 0.0001 16 µΩ XP 0.01 5.3 mH VS 1 110kV RS 0.0001 6.7 mΩ XS 0.01 53 µH

TABLE V CONVERTER PARAMETERS

Symbol Per unit Value Actual Value

60 Hz FS 40 2400 Hz

220


Ξ−Ξ−Ξ−Ξ−controller case study

TABLE I

SYSTEM PARAMETERS




TABLE II CAPACITOR PARAMETERS


Actual value 15.5 kV 20MVA

60Hz XC 1 438 µF RC 500 6 kΩ

TABLE III TRANSFORMER SIT PARAMETERS


Actual value 15.5/15.5 kV 20MVA

60Hz VSP 1 15.5 kV RSP 0.0001 1.2 mΩ XSP 0.01 0.3 mH VSS 1 15.5kV RSS 0.0001 1.2 mΩ XSS 0.01 0.3 mH RPM 500 6 kΩ XPM 500 16 H

TABLE IV CONVERTER PARAMETERS

Symbol Per unit value Actual value 60Hz

FS 40 2.4kHz

221


Γ−Γ−Γ−Γ−controller case study

TABLE I SYSTEM PARAMETERS




TABLE II TRANSFORMER SPT PARAMETERS


Actual value 110/15.5/8.9/15.5/8.9kV

20MVA 60Hz VPP 1 110kV RPP 0.001 0.6 Ω XPS 0.01 16.0 mH VPS1 1 15.5kV RPS1 0.001 12 mΩ XPS1 0.01 0.3 mH VPS2 1 8.9kV RPS2 0.001 4 mΩ XPS2 0.01 0.1 mH VPS3 1 15.5kV RPS3 0.001 12 mΩ XPS3 0.01 0.3 mH VPS4 1 8.9kV RPS4 0.001 4 mΩ XPS4 0.01 0.1 mH RPM 500 302 kΩ XPM 500 800 H

TABLE III FILTER CAPACITOR FTC PARAMETERS


Actual value 15.5 kV 20MVA

60Hz XC 3 73 µF RC 500 6 kΩ

TABLE IV TRANSFORMER SIT PARAMETERS


Actual value 15.5/15.5 kV 20MVA

60Hz VSP 1 15.5 kV RSP 0.0001 1.2 mΩ XSP 0.01 0.3 mH VSS 1 15.5kV RSS 0.0001 1.2 mΩ XSS 0.01 0.3 mH RPM 500 6 kΩ XPM 500 16 H

TABLE V CONVERTER PARAMETERS

Symbol Per unit value Actual value 60Hz

FS 40 2400Hz

222

Appendix 4 Parameters zi for the

ΓΓΓΓ−−−−controller state space description

z0=(4*Lsp*as^2*Ls*ap^2+4*Lsp*as^2*Lpp*ap^2+4*Lr*Ls*ap^2+...

4*Lr*Lpp*ap^2+4*Ls*Lpp*ap^2+4*Lss*Ls*ap^2+4*Lss*Lpp*ap^2+...

Lsp*as^2*Lps+Ls*Lps+Lss*Lps+Lr*Lps);

z1=ap*(Rs*Lsp*as^2+Rs*Lr+Rs*Lss-Rss*Ls-Rr*Ls-Rsp*as^2*Ls)/z0;

z2=1/Lps*ap*(Lsp*as^2*Lpp*ap+Lsp*as^2*Ls*ap+Lss*Lpp*ap+...

Lss*Ls*ap+Ls*Lpp*ap+Lr*Lpp*ap+Lr*Ls*ap)/z0;

z3=((4*Ls*Rpp-4*Rs*Lpp)*ap^3-(-Ls*Rps+Rs*Lps)*ap)/z0;

z4=(-Rsp*as^2*Lps-4*ap^2*Lpp*Rsp*as^2-4*ap^2*Lpp*Rss...

-4*ap^2*Lpp*Rr-4*ap^2*Ls*Rss-4*ap^2*Rs*Lpp-4*...

ap^2*Ls*Rr-Rr*Lps-Rss*Lps-Rs*Lps-4*ap^2*Ls*Rsp*as^2)/z0;

z5=1/Lps*ap^2*(Lpp*Rps*Lr+Lpp*Rps*Lss+Lpp*Rps*Ls+...

Rps*Ls*Lr+Rps*Ls*Lss-Rs*Lps*Lr-Rs*Lps*Lsp*as^2-...

Rs*Lps*Lss+Rps*Ls*Lsp*as^2+Lpp*Rps*Lsp*as^2-Rpp*Lps...

*Lsp*as^2-Rpp*Lps*Ls-Rpp*Lps*Lss-Rpp*Lps*Lr)/z0;

z6=as*(Lps+4*ap^2*Lpp+4*ap^2*Ls)/z0;

z7=1/Lps*ap*as*Ls*Lps/z0;

z8=ap*Ls/z0;

z9=(4*Lpp*ap^2+Lps)/z0;

z10=(-(4*Lpp+4*Ls)*ap^2-Lps)/z0;

z11=ap*(Lr+as^2*Lsp+Lss)/z0;

223

Appendix 5 OPF Data

TABLE I BUS DATA

Number Type Pd (MW) Qd (MVA) Vmax (pu) Vmin (pu) θmax ° θmin ° 1 1 0 0 1.1 0.9 90 -90

2 1 0 0 1.1 0.9 90 -90

3 1 322 2.4 1.1 0.9 90 -90

4 1 500 184 1.1 0.9 90 -90

5 1 0 0 1.1 0.9 90 -90

6 1 0 0 1.1 0.9 90 -90

7 1 233.8 84 1.1 0.9 90 -90

8 1 522 176.6 1.1 0.9 90 -90

9 1 0 0 1.1 0.9 90 -90

10 1 0 0 1.1 0.9 90 -90

11 1 0 0 1.1 0.9 90 -90

12 1 8.5 88 1.1 0.9 90 -90

13 1 0 0 1.1 0.9 90 -90

14 1 0 0 1.1 0.9 90 -90

15 1 320 153 1.1 0.9 90 -90

16 1 329.4 32.3 1.1 0.9 90 -90

17 1 0 0 1.1 0.9 90 -90

18 1 158 30 1.1 0.9 90 -90

19 1 0 0 1.1 0.9 90 -90

20 1 680 103 1.1 0.9 90 -90

21 1 274 115 1.1 0.9 90 -90

22 1 0 0 1.1 0.9 90 -90

23 1 247.5 84.6 1.1 0.9 90 -90

24 1 308.6 -92.2 1.1 0.9 90 -90

25 1 224 47.2 1.1 0.9 90 -90

26 1 139 17 1.1 0.9 90 -90

27 1 281 75.5 1.1 0.9 90 -90

28 1 206 27.6 1.1 0.9 90 -90

29 1 283.5 26.9 1.1 0.9 90 -90

30 2 0 0 1.1 0.9 90 -90

31 3 9.2 4.6 1.1 0.9 90 -90

32 2 0 0 1.1 0.9 90 -90

33 2 0 0 1.1 0.9 90 -90

34 2 0 0 1.1 0.9 90 -90

35 2 0 0 1.1 0.9 90 -90

36 2 0 0 1.1 0.9 90 -90

37 2 0 0 1.1 0.9 90 -90

38 2 0 0 1.1 0.9 90 -90

39 2 1104 250 1.1 0.9 90 -90

224

TABLE II

GENERATOR DATA Cost ($/h) aP2+bP+c Number Pmax (MW) Pmin (MW) Qmax (MVA) Qmin (MVA) a b c

30 300 0 300 -300 0.06 0.1 0

31 500 0 500 -500 0.01 0.4 0

32 750 0 750 -750 0.05 0.3 0

33 1000 0 1000 -1000 0.01 0.3 0

34 1000 0 1000 -1000 0.04 0.2 0

35 1000 0 1000 -1000 0.07 0.3 0

36 1000 0 1000 -1000 0.01 0.5 0

37 400 0 400 -400 0.02 0.7 0

38 1000 0 1000 -1000 0.006 0.3 0

39 500 0 500 -500 0.006 0.3 0

TABLE III

BRANCH DATA

From To R(pu) X(pu) Rating (MVA) Tap 1 2 0.0035 0.0411 2500 0

1 39 0.001 0.025 500 0

2 3 0.0013 0.0151 2500 0

2 25 0.007 0.0086 2500 0

3 4 0.0013 0.0213 500 0

3 18 0.0011 0.0133 2500 0

4 5 0.0008 0.0128 2500 0

4 14 0.0008 0.0129 2500 0

5 6 0.0002 0.0026 2500 0

5 8 0.0008 0.0112 2500 0

6 7 0.0006 0.0092 2500 0

6 11 0.0007 0.0082 2500 0

7 8 0.0004 0.0046 2500 0

8 9 0.0023 0.0363 2500 0

9 39 0.001 0.025 2500 0

10 11 0.0004 0.0043 2500 0

10 13 0.0004 0.0043 2500 0

13 14 0.0009 0.0101 2500 0

14 15 0.0018 0.0217 500 0

15 16 0.0009 0.0094 2500 0

16 19 0.0016 0.0195 2500 0

16 21 0.0008 0.0135 2500 0

16 24 0.0003 0.0059 2500 0

From To R(pu) X(pu) Rating (MVA) Tap 17 18 0.0007 0.0082 2500 0

17 27 0.0013 0.0173 2500 0

21 22 0.0008 0.014 2500 0

21 29 0.0008 0.014 2500 0

22 23 0.0006 0.0096 2500 0

23 24 0.0022 0.035 2500 0

25 26 0.0032 0.0323 2500 0

26 27 0.0014 0.0147 2500 0

26 28 0.0043 0.0474 500 0

16 17 0.0007 0.0089 500 0

26 29 0.0057 0.0625 500 0

28 29 0.0014 0.0151 2500 0

12 11 0.0016 0.0435 2500 1.006

12 13 0.0016 0.0435 2500 1.006

6 31 0 0.025 2500 1.07

10 32 0 0.02 2500 1.07

19 33 0.0007 0.0142 2500 1.07

20 34 0.0009 0.018 2500 1.009

22 35 0 0.0143 2500 1.025

23 36 0.0005 0.0272 2500 1

25 37 0.0006 0.0232 2500 1.025

2 30 0 0.0181 2500 1.025

29 38 0.0008 0.0156 2500 1.025

19 20 0.0007 0.0138 2500 1.06

225

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