acer aspire 4750g je40-hr rev -1

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Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

JE40-HR -1Cover Page

A3

1 102Thursday, December 02, 2010

HR UMA

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HR UMA

ANNIE: ONLY FOR ANNIE solution.PSL: KBC795 PSL circuit for 10mW solution installed.10mW: External circuit for 10mW solution installed.65W: for 65W adaptor installed.90W: for 90W adaptor installed.

DY :None InstalledDIS:DIS installedDIS_Muxless :BOTH DIS or Muxless installedDIS_PX:BOTH DIS or PX installedDIS_PX_Muxless:DIS or PX or Muxless installed.Muxless: Muxless installed.(PX4.0)PX:MUX installed.(PX3.0)PX_Muxless:BOTH PX or Muxless installed.UMA:UMA installedUMA_Muxless:BOTH UMA or Muxless installedUMA_PX_Muxless:UMA or PX or Muxless installed

Intel PCH

DIS/UMA/Muxless Schematics DocumentSandy Bridge

JE40 HR

55

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JE40-HR -1Block Diagram

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HR UMA

INPUTSVGA

DCBATOUTOUTPUTS

26

RT8208BGQWVGA_CORE

0D75V_S0

3D3V_AUX_S5

NCP6131S52MNRINPUTS

VCC_COREOUTPUTS

SYSTEM DC/DCUP6165BQKF

DDR_VREF_S3

OUTPUTS

CPU DC/DC

DCBATOUT

1D5V_S3INPUTS

UP6183PQAG

DCBATOUT 5V_S5

OUTPUTS

3D3V_S5

UP6128PQDDOUTPUTS

SYSTEM DC/DCINPUTS

DCBATOUTINPUTSSYSTEM DC/DC

DCBATOUT

1D5V_VGA_S0

OUTPUTS

OUTPUTS

SYSTEM DC/DCINPUTS

BQ24745RHDRINPUTS

TI CHARGER

DCBATOUT

5V_AUX_S5

INPUTSSYSTEM DC/DC

OUTPUTS

26

RT9025

3D3V_S0

3D3V_VGA_S03D3V_S0

1D8V_S0

DCBATOUT

PCB LAYERL1:TopL2:VCCL3:Signal

VCC_GFXCORE_PWR

1D5V_S3

NCP5911MNTBG

1D8V_VGA_S0

SYSTEM DC/DC

Switches

INPUTS OUTPUTS

1D05V_VTT

42~43

45

41

46

44

92

47

93

2869 2569

40

RT9025-25PSP

INPUTS OUTPUTS

1D5V_S3 1V_VGA_S0

L4:SignalL5:GNDL6:Bottom

3D3V_S5

APL5916KAIINPUTS

0D85V_S0OUTPUTS

SYSTEM DC/DC

1D05V_PWR

48

PCIE x 1USB x 1

57

60 71LPC debug port

Nvidia N12P

Project code : 91.4IQ01.001PCB P/N : 48.4IQ01.0SA Revision : 10267-1

ENE P2800ENE P2793

ALC271X

DMIx4

1000 NIC

RJ45CONN

SIM

S

P

I

Flash ROM4MB

51

Mini-Card

HDMIHDMI

88,89,90,91

83.84,85,86,87

BCM57780A1

KBC

ThermalInt. KB

L

P

C

B

u

s

DDRIII1066/1333

Intel CPUDDRIII 1066/1333 Channel A Slot 0

14

15

4,5,6,7,8,9,10,11,12,13

Slot 1

JE40 HR Block Diagram(Discrete/UMA/co-lay)

Bluetooth 63

Left Side:USB x 1

WWAN

Right Side:USB x 1

CAMERA 49

MIC IN

Mini-Card802.11a/b/g

LVDS(Dual Channel)

CRT

Intel

56

LCDRGB CRT

ODD

56

14 USB 2.0/1.1 ports

High Definition Audio

SATA x 2

SATA ports (6)

ACPI 1.1LPC I/F

HDD

SD/MMC+/MS/MS Pro/xD

AzaliaCODEC

USB2.0 x 4

29

2CH SPEAKER

HP1

Internal Analog MIC

ETHERNET (10/100/1000Mb)

NPCE795P

PCIE ports (8)

NUVOTON

28

DDR3800MHz

2GB/1GB/512MB

Fan

VRAM

27

49

17,18,19,20,21,22,23,24,25,26

PCIe x 16

TouchPAD

FDIx4x2(UMA only)

Discreet/UMA/PX Co-lay

AZALIA

65

66 66

31

59

64

50

(Discrete only)

Level shifter

##OnMainBoard

SMBus

USB 2.0 x 1

PCIE x 1,USB x 1

PCIE x 1

Sandy BridgeFSB: 1066 MHz

DDRIII1066/1333

DDRIII 1066/1333 Channel B

PCHCougar Point

75

PCIE x 1USB x 2

USB3.0uPD720200

BT+

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

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JE40-HR -1Table of Content

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PCIE Routing

LANE2LANE3 Card Reader

Onboard LANLANE4

Mini Card1(WLAN)SATA TablePair

SATADevice

0

54321

HDD1

ODD

N/AHDD2

N/A

ESATA

LANE1 Mini Card2(WWAN)

LANE5LANE6LANE7LANE8 New Card

Intel GBE LAN

CFG[6:5]

CFG[7]

Processor Strapping

CFG[2]

Disabled - No Physical Display Port attached toEmbedded DisplayPort.CFG[4]

Pin Name Strap Description Configuration (Default value for each bit is 1 unless specified otherwise)

1:

Huron River Schematic Checklist Rev.0_7

0:PCI-Express StaticLane Reversal

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

DefaultValue

PCI-ExpressPort BifurcationStraps

11 : x16 - Device 1 functions 1 and 2 disabled10 : x8, x8 - Device 1 function 1 enabled ;function 2 disabled01 : Reserved - (Device 1 function 1 disabled ;function 2 enabled)00 : x8, x4, x4 - Device 1 functions 1 and 2enabled

PEG DEFER TRAINING

1

0

1

1:

0: Enabled - An external Display Port device isconnectd to the EMBEDDED display Port

11

1:0: PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

SPKRName Schematics Notes

HAD_DOCK_EN#/GPIO[33]

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.HDA_SYNC

Huron River Schematic Checklist Rev.0_7

INIT3_3V# Weak internal pull-up. Leave as "No Connect".GNT3#/GPIO55GNT2#/GPIO53GNT1#/GPIO51

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-downusing a 1k +/- 5% resistor. When this signal is sampled high at the rising edge ofRSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode isenabled.

PCH Strapping

SPI_MOSI

Internal weak Pull-down. Connect to Vcc3_3 with 8.2-k- 10-k weak pull-up resistor.

NV_ALE

Enable Danbury:

Disable Danbury:NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

GPIO15

GPIO8

Reboot option at power-upDefault Mode:No Reboot Mode with TCO Disabled:

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

Low (0) - Flash Descriptor Security will be overridden. Also,when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.High (1) - Security measure defined in the Flash Descriptor will be enabled.Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND asrequired by the functional strap, the signal should be pulled low through a weakpull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internalpull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset forstrapping functions.

GPIO27Default = Do not connect (floating)High(1) = Enables the internal VccVRM to have a clean supply foranalog rails. No need to use on-board filter circuit.Low (0) = Disables the VccVRM. Need to use on-board filtercircuits for analog rails.

Voltage RailsVOLTAGE DESCRIPTIONACTIVE IN

POWER PLANE

CPU Core RailGraphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

3D3V_AUX_KBC

3.3V

DSW, Sx ON for supporting Deep Sleep states

S0

S3

All S states

WOL_EN

G3, Sx

5V_S03D3V_S01D8V_S01D5V_S01D05V_VTT0D85V_S00D75V_S0VCC_COREVCC_GFXCORE1D8V_VGA_S03D3V_VGA_S01V_VGA_S0

5V3.3V1.8V1.5V1.05V0.95 - 0.85V0.75V0.35V to 1.5V0.4 to 1.25V1.8V3.3V1V

5V1.5V0.75V

5V_USBX_S31D5V_S3DDR_VREF_S3

BT+DCBATOUT5V_S55V_AUX_S53D3V_S53D3V_AUX_S5

6V-14.1V6V-14.1V5V5V3.3V3.3V

3.3V3D3V_LAN_S5

3.3V

3D3V_AUX_S5

GNT[3:0]# functionality is not available on Mobile.Mobile: Used as GPIO onlyPull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:Disable Danbury:

Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with noconfidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentialityNote : This is an un-muxed signal.This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#.CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLK

DeviceI C / SMBus Addresses2

EC SMBus 1BatteryCHARGER

EC SMBus 2PCHeDP

PCH SMBusSO-DIMMA (SPD)SO-DIMMB (SPD)Digital PotG-SensorMINI

BAT_SCL/BAT_SDA

SMBus ADDRESSESHURON RIVER ORB

Address Hex Bus Ref Des

USB3.0

Dock

USB Table

13

EDP CAMERA

12

X

Mini Card1 (WLAN)

Fingerprint

X

New Card

USB Ext. port 210

0

11

USB Ext. port 1 (HS)

Pair

45

23

1

Device

6789

BLUETOOTH

Touch Panel / 3G SIM

CARD READER

USB Ext. port 4 / E-SATA /USB CHARGER

CAMERA

Mini Card2 (WWAN) BAT_SCL/BAT_SDABAT_SCL/BAT_SDA

SML1_CLK/SML1_DATASML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK

PCH_SMBDATA/PCH_SMBCLK

55

4

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3

3

2

2

1

1

D D

C C

B B

A A

PEG_C_TXN3

PEG_C_TXN15

PEG_C_TXN10

PEG_C_TXN5

PEG_C_TXN0

PEG_C_TXN12

PEG_C_TXN7

PEG_C_TXN2

PEG_C_TXN14

PEG_C_TXN9

PEG_C_TXN4

PEG_C_TXN11

PEG_C_TXN6

PEG_C_TXN1

PEG_C_TXN13

PEG_C_TXN8

PEG_RXN5PEG_RXN4PEG_RXN3PEG_RXN2PEG_RXN1

PEG_RXP5

PEG_RXN0

PEG_RXP4PEG_RXP3PEG_RXP2PEG_RXP1PEG_RXP0

PEG_RXP15

PEG_RXN15PEG_RXN14

PEG_RXP14PEG_RXP13PEG_RXP12

PEG_RXN13PEG_RXN12

PEG_RXP11

PEG_RXN11

PEG_RXP10

PEG_RXN10

PEG_RXP9

PEG_RXN9

PEG_RXP8

PEG_RXN8

PEG_RXP7PEG_RXP6

PEG_RXN7PEG_RXN6

PEG_IRCOMP_R

PEG_C_TXP3

PEG_C_TXP15

PEG_C_TXP10

PEG_C_TXP5

PEG_C_TXP0

PEG_C_TXP12

PEG_C_TXP7

PEG_C_TXP2

PEG_C_TXP14

PEG_C_TXP9

PEG_C_TXP4

PEG_C_TXP11

PEG_C_TXP6

PEG_C_TXP1

PEG_C_TXP13

PEG_C_TXP8

PEG_TXN0PEG_TXN1PEG_TXN2PEG_TXN3PEG_TXN4PEG_TXN5PEG_TXN6PEG_TXN7PEG_TXN8PEG_TXN9PEG_TXN10PEG_TXN11PEG_TXN12PEG_TXN13PEG_TXN14PEG_TXN15

PEG_TXP15PEG_TXP14PEG_TXP13PEG_TXP12PEG_TXP11PEG_TXP10PEG_TXP9PEG_TXP8PEG_TXP7PEG_TXP6PEG_TXP5PEG_TXP4PEG_TXP3PEG_TXP2PEG_TXP1PEG_TXP0

FDI_FSYNC0

FDI_LSYNC1FDI_INT

FDI_LSYNC0

FDI_FSYNC1

DP_COMP

eDP_HPD

FDI_TXP4FDI_TXP5

DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3

DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3

DMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3

DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3

FDI_TXP6FDI_TXP7

FDI_TXN0FDI_TXN1

FDI_TXN3FDI_TXN4FDI_TXN5FDI_TXN6FDI_TXN7

FDI_TXN2

FDI_TXP0FDI_TXP1FDI_TXP2FDI_TXP3

1D05V_VTT

1D05V_VTT PEG_TXP[0..15] 83

PEG_TXN[0..15] 83

PEG_RXP[0..15] 83

PEG_RXN[0..15] 83

DMI_RXN[3:0]19

DMI_RXP[3:0]19

DMI_TXN[3:0]19

DMI_TXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019FDI_FSYNC119

FDI_INT19

FDI_LSYNC019FDI_LSYNC119

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JE40-HR -1CPU (PCIE/DMI/FDI)

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HR UMA

SSID = CPU

Stuff to disable internal graphicsfunction for power saving. NOTE:

Select a Fast FET similar to 2N7002E whose rise/fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-k pull-Up resistor on the motherboard.

NOTE.If PEG is not implemented, the RX&TX pairs can be left as No Connect

NOTE.Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

PEG Static Lane Reversal

Signal Routing Guideline:PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

Note:Intel DMI supports both LaneReversal and polarity inversionbut only at PCH side. This isenabled via a soft strap.

Note:Lane reversal does not apply toFDI sideband signals.

Note:Intel FDI supports both LaneReversal and polarity inversionbut only at PCH side. This isenabled via a soft strap.

Signal Routing Guideline:EDP_ICOMPO keep W/S=12/15 mils and routinglength less than 500 mils.EDP_COMPIO keep W/S=4/15 mils and routinglength less than 500 mils.

20100614 V1.1

JE40 delete eDP function

C424 Do Not StuffDIS_PX_MuxlessC424 Do Not StuffDIS_PX_Muxless1 2





R402 24D9R2F-L-GPR402 24D9R2F-L-GP1 2


R403 10KR2J-3-GPR403 10KR2J-3-GP1 2

R40124D9R2F-L-GPR40124D9R2F-L-GP

1 2

RN401Do Not StuffDIS


1234

5 6 7 8



R404Do Not Stuff DISR404Do Not Stuff DIS

1

2










C413 Do Not StuffDIS_PX_MuxlessC413 Do Not StuffDIS_PX_Muxless1 2C412 Do Not StuffDIS_PX_MuxlessC412 Do Not StuffDIS_PX_Muxless1 2







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CPU1ASANDY62.10055.421Change:62.10053.6112nd = 62.10055.3213rd = 62.10040.821

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CPU1ASANDY62.10055.421Change:62.10053.6112nd = 62.10055.3213rd = 62.10040.821

DMI_RX#0B27DMI_RX#1B25DMI_RX#2A25DMI_RX#3B24

DMI_RX0B28DMI_RX1B26DMI_RX2A24DMI_RX3B23

DMI_TX#0G21DMI_TX#1E22DMI_TX#2F21DMI_TX#3D21

DMI_TX0G22DMI_TX1D22

DMI_TX3C21DMI_TX2F20

FDI0_TX#0A21FDI0_TX#1H19FDI0_TX#2E19FDI0_TX#3F18FDI1_TX#0B21FDI1_TX#1C20FDI1_TX#2D18FDI1_TX#3E17

FDI0_TX0A22FDI0_TX1G19FDI0_TX2E20FDI0_TX3G18FDI1_TX0B20FDI1_TX1C19FDI1_TX2D19FDI1_TX3F17

FDI0_FSYNCJ18FDI1_FSYNCJ17

FDI_INTH20

FDI0_LSYNCJ19FDI1_LSYNCH17

PEG_ICOMPI J22PEG_ICOMPO J21

PEG_RCOMPO H22

PEG_RX#0 K33PEG_RX#1 M35PEG_RX#2 L34PEG_RX#3 J35PEG_RX#4 J32PEG_RX#5 H34PEG_RX#6 H31PEG_RX#7 G33PEG_RX#8 G30PEG_RX#9 F35

PEG_RX#10 E34PEG_RX#11 E32PEG_RX#12 D33PEG_RX#13 D31PEG_RX#14 B33PEG_RX#15 C32

PEG_RX0 J33PEG_RX1 L35PEG_RX2 K34PEG_RX3 H35PEG_RX4 H32PEG_RX5 G34PEG_RX6 G31PEG_RX7 F33PEG_RX8 F30PEG_RX9 E35

PEG_RX10 E33PEG_RX11 F32PEG_RX12 D34PEG_RX13 E31PEG_RX14 C33PEG_RX15 B32

PEG_TX#0 M29PEG_TX#1 M32PEG_TX#2 M31PEG_TX#3 L32PEG_TX#4 L29PEG_TX#5 K31PEG_TX#6 K28PEG_TX#7 J30PEG_TX#8 J28PEG_TX#9 H29

PEG_TX#10 G27PEG_TX#11 E29PEG_TX#12 F27PEG_TX#13 D28PEG_TX#14 F26PEG_TX#15 E25

PEG_TX0 M28PEG_TX1 M33PEG_TX2 M30PEG_TX3 L31PEG_TX4 L28PEG_TX5 K30PEG_TX6 K27PEG_TX7 J29PEG_TX8 J27PEG_TX9 H28

PEG_TX10 G28PEG_TX11 E28PEG_TX12 F28PEG_TX13 D27PEG_TX14 E26PEG_TX15 D25

EDP_AUXC15EDP_AUX#D15

EDP_TX0C17EDP_TX1F16EDP_TX2C16EDP_TX3G15

EDP_TX#0C18EDP_TX#1E16EDP_TX#2D16EDP_TX#3F15

EDP_COMPIOA18

EDP_HPDB16EDP_ICOMPOA17








55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XDP_TRST#

XDP_DBRESET#

XDP_TDO

CLK_DP_P_RCLK_DP_N_R

BUF_CPU_RST#

H_PROCHOT#

H_PROCHOT#_R SM_RCOMP_0SM_RCOMP_1SM_RCOMP_2

XDP_DBRESET#

BUF_CPU_RST#

XDP_TRST#XDP_TDO

1D05V_VTT

1D05V_VTT

3D3V_S0

1D05V_VTT

H_SNB_IVB#18

H_PM_SYNC19

PM_DRAM_PWRGD19,37

H_PECI22,27

H_CPUPWRGD22,36,97

H_THERMTRIP#22,36

H_PROCHOT#27,42

VDDPWRGOOD37

CLK_EXP_P 20CLK_EXP_N 20

SM_DRAMRST# 37

PLT_RST#18,27,31,36,65,66,71,82,97

Title


Date: Sheet of


JE40-HR -1

CPU (THERMAL/CLOCK/PM )Custom


HR UMA

Title


Date: Sheet of


JE40-HR -1



HR UMA

Title


Date: Sheet of


JE40-HR -1



HR UMA

SSID = CPUDisabling Guidelines:If motherboard only supports external graphics:Connect DPLL_REF_SSCLK on Processor to GND through1K +/- 5% resistor.Connect DPLL_REF_SSCLK# on Processor to VCCPthrough 1K +/- 5% resistorpower (~15 mW) may bewasted.

CRB : 47pfCEKLT:43pf

Connect EC to PROCHOT# through inverting OD buffer. Signal Routing Guideline:SM_RCOMP keep routing length less than 500 mils.

JE40 modify

JE40 modify

JE40 modify

JE40 modify

JE40 modify

R506 140R2F-GPR506 140R2F-GP1 2R507 25D5R2F-GPR507 25D5R2F-GP1 2R508 200R2F-L-GPR508 200R2F-L-GP1 2

R50162R2J-GPR50162R2J-GP

1 2

R50310KR2J-3-GPR50310KR2J-3-GP

1 2

R5024K99R2F-L-GP

R5024K99R2F-L-GP1 2

RN503SRN1K5J-1-GPRN503SRN1K5J-1-GP1234 5

678

RN501SRN51J-GPRN501SRN51J-GP

12 3

4

C502SC47P50V2JN-3GPC502SC47P50V2JN-3GP

1

2

R505 Do Not StuffDY

R505 Do Not StuffDY1 2

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CPU1BSANDY

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CPU1BSANDY

SM_RCOMP1 A5SM_RCOMP2 A4

SM_DRAMRST# R8

SM_RCOMP0 AK1

BCLK# A27BCLK A28

DPLL_REF_SSCLK# A15DPLL_REF_SSCLK A16

CATERR#AL33

PECIAN33

PROCHOT#AL32

THERMTRIP#AN32

SM_DRAMPWROKV8

RESET#AR33

PRDY# AP29PREQ# AP27

TCK AR26TMS AR27

TRST# AP30

TDI AR28TDO AP26

DBR# AL35

BPM#0 AT28BPM#1 AR29BPM#2 AR30BPM#3 AT30BPM#4 AP32BPM#5 AR31BPM#6 AT31BPM#7 AR32

PM_SYNCAM34

SKTOCC#AN34

SNB_IVB#C26

UNCOREPWRGOODAP33


RN502Do Not StuffDIS1

2 34

R51356R2J-4-GPR51356R2J-4-GP

1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_A_DQS4M_A_DQS3

M_A_DQS5M_A_DQS6M_A_DQS7

M_A_DQS2M_A_DQS1M_A_DQS0

M_A_A7

M_A_A12

M_A_A14M_A_A13

M_A_A9

M_A_A15

M_A_A10

M_A_A0

M_A_A6

M_A_A8

M_A_A1M_A_A2M_A_A3M_A_A4M_A_A5

M_A_A11

M_A_DQS#4M_A_DQS#5M_A_DQS#6M_A_DQS#7

M_A_DQS#3M_A_DQS#2M_A_DQS#1M_A_DQS#0

M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_DQS#3M_B_DQS#2M_B_DQS#1M_B_DQS#0

M_B_DQS#7M_B_DQS#6M_B_DQS#5M_B_DQS#4

M_B_A5M_B_A6M_B_A7M_B_A8M_B_A9M_B_A10M_B_A11M_B_A12M_B_A13M_B_A14M_B_A15

M_B_A4M_B_A3M_B_A2M_B_A1M_B_A0

M_A_DQ[63:0]14 M_B_DQ[63:0]15

M_A_BS014M_A_BS114M_A_BS214

M_A_CAS#14M_A_RAS#14M_A_WE#14

M_B_BS015M_B_BS115M_B_BS215

M_B_CAS#15M_B_RAS#15M_B_WE#15

M_A_DQS#[7:0] 14

M_A_A[15:0] 14

M_A_DQS[7:0] 14

M_A_DIM0_CKE0 14

M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14M_A_DIM0_ODT1 14

M_A_DIM0_CLK_DDR0 14M_A_DIM0_CLK_DDR#0 14


M_B_A[15:0] 15

M_B_DQS[7:0] 15

M_B_DQS#[7:0] 15

M_B_DIM0_CKE0 15

M_B_DIM0_CKE1 15

M_B_DIM0_CS#0 15M_B_DIM0_CS#1 15

M_B_DIM0_ODT0 15M_B_DIM0_ODT1 15

M_B_DIM0_CLK_DDR0 15M_B_DIM0_CLK_DDR#0 15


Title


Date: Sheet of


JE40-HR -1CPU (DDR)

A3


HR UMA

Title


Date: Sheet of


JE40-HR -1CPU (DDR)

A3


HR UMA

Title


Date: Sheet of


JE40-HR -1CPU (DDR)

A3


HR UMA

SSID = CPU

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

4 OF 9

SANDY

CPU1D

SANDY

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

4 OF 9

SANDY

CPU1D

SANDY

SB_BS0AA9SB_BS1AA7SB_BS2R6

SB_CAS#AA10SB_RAS#AB8SB_WE#AB9

SB_CLK0 AE2

SB_CLK1 AE1

SB_CLK#0 AD2

SB_CLK#1 AD1

SB_CKE0 R9

SB_CKE1 R10

SB_ODT0 AE4SB_ODT1 AD4

SB_DQS4 AN6

SB_DQS#4 AN5

SB_DQS5 AP8

SB_DQS#5 AP9

SB_DQS6 AK11

SB_DQS#6 AK12

SB_DQS7 AP14

SB_DQS#7 AP15

SB_DQS0 C7

SB_DQS#0 D7

SB_DQS1 G3

SB_DQS#1 F3

SB_DQS2 J6

SB_DQS#2 K6

SB_DQS3 M3

SB_DQS#3 N3

SB_MA0 AA8SB_MA1 T7SB_MA2 R7SB_MA3 T6SB_MA4 T2SB_MA5 T4SB_MA6 T3SB_MA7 R2SB_MA8 T5SB_MA9 R3

SB_MA10 AB7SB_MA11 R1SB_MA12 T1SB_MA13 AB10SB_MA14 R5SB_MA15 R4

SB_DQ0C9SB_DQ1A7SB_DQ2D10SB_DQ3C8SB_DQ4A9SB_DQ5A8SB_DQ6D9SB_DQ7D8SB_DQ8G4SB_DQ9F4SB_DQ10F1SB_DQ11G1SB_DQ12G5SB_DQ13F5SB_DQ14F2SB_DQ15G2SB_DQ16J7SB_DQ17J8SB_DQ18K10SB_DQ19K9SB_DQ20J9SB_DQ21J10SB_DQ22K8SB_DQ23K7SB_DQ24M5SB_DQ25N4SB_DQ26N2SB_DQ27N1SB_DQ28M4SB_DQ29N5SB_DQ30M2SB_DQ31M1SB_DQ32AM5SB_DQ33AM6SB_DQ34AR3SB_DQ35AP3SB_DQ36AN3SB_DQ37AN2SB_DQ38AN1SB_DQ39AP2SB_DQ40AP5SB_DQ41AN9SB_DQ42AT5SB_DQ43AT6SB_DQ44AP6SB_DQ45AN8SB_DQ46AR6SB_DQ47AR5SB_DQ48AR9SB_DQ49AJ11SB_DQ50AT8SB_DQ51AT9SB_DQ52AH11SB_DQ53AR8SB_DQ54AJ12SB_DQ55AH12SB_DQ56AT11SB_DQ57AN14SB_DQ58AR14SB_DQ59AT14SB_DQ60AT12SB_DQ61AN15SB_DQ62AR15SB_DQ63AT15

SB_CLK2 AB2SB_CLK#2 AA2SB_CKE2 T9

SB_CLK3 AA1SB_CLK#3 AB1SB_CKE3 T10

SB_CS#0 AD3SB_CS#1 AE3SB_CS#2 AD6SB_CS#3 AE6

SB_ODT2 AD5SB_ODT3 AE5

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

A

3 OF 9

SANDYCPU1C

SANDY

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

A

3 OF 9

SANDYCPU1C

SANDY

SA_BS0AE10SA_BS1AF10SA_BS2V6

SA_CAS#AE8SA_RAS#AD9SA_WE#AF9

SA_CLK0 AB6

SA_CLK1 AA5

SA_CLK#0 AA6

SA_CLK#1 AB5

SA_CKE0 V9

SA_CKE1 V10

SA_CS#0 AK3SA_CS#1 AL3

SA_ODT0 AH3SA_ODT1 AG3

SA_DQS0 D4

SA_DQS#0 C4

SA_DQS1 F6

SA_DQS#1 G6

SA_DQS2 K3

SA_DQS#2 J3

SA_DQS3 N6

SA_DQS#3 M6

SA_DQS4 AL5

SA_DQS#4 AL6

SA_DQS5 AM9

SA_DQS#5 AM8

SA_DQS6 AR11

SA_DQS#6 AR12

SA_DQS7 AM14

SA_DQS#7 AM15

SA_MA0 AD10SA_MA1 W1SA_MA2 W2SA_MA3 W7SA_MA4 V3SA_MA5 V2SA_MA6 W3SA_MA7 W6SA_MA8 V1SA_MA9 W5

SA_MA10 AD8SA_MA11 V4SA_MA12 W4SA_MA13 AF8SA_MA14 V5SA_MA15 V7

SA_DQ0C5SA_DQ1D5SA_DQ2D3SA_DQ3D2SA_DQ4D6SA_DQ5C6SA_DQ6C2SA_DQ7C3SA_DQ8F10SA_DQ9F8SA_DQ10G10SA_DQ11G9SA_DQ12F9SA_DQ13F7SA_DQ14G8SA_DQ15G7SA_DQ16K4SA_DQ17K5SA_DQ18K1SA_DQ19J1SA_DQ20J5SA_DQ21J4SA_DQ22J2SA_DQ23K2SA_DQ24M8SA_DQ25N10SA_DQ26N8SA_DQ27N7SA_DQ28M10SA_DQ29M9SA_DQ30N9SA_DQ31M7SA_DQ32AG6SA_DQ33AG5SA_DQ34AK6SA_DQ35AK5SA_DQ36AH5SA_DQ37AH6SA_DQ38AJ5SA_DQ39AJ6SA_DQ40AJ8SA_DQ41AK8SA_DQ42AJ9SA_DQ43AK9SA_DQ44AH8SA_DQ45AH9SA_DQ46AL9SA_DQ47AL8SA_DQ48AP11SA_DQ49AN11SA_DQ50AL12SA_DQ51AM12SA_DQ52AM11SA_DQ53AL11SA_DQ54AP12SA_DQ55AN12SA_DQ56AJ14SA_DQ57AH14SA_DQ58AL15SA_DQ59AK15SA_DQ60AL14SA_DQ61AK14SA_DQ62AJ15SA_DQ63AH15

SA_CLK2 AB4SA_CLK#2 AA4

SA_CLK3 AB3SA_CLK#3 AA3

SA_CKE2 W9

SA_CKE3 W10

SA_CS#2 AG1SA_CS#3 AH1

SA_ODT2 AG2SA_ODT3 AH2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG2

M_VREF_DQ_DIMM0_CM_VREF_DQ_DIMM1_C

Title


Date: Sheet of


JE40-HR -1CPU (RESERVED)

A3


HR UMA

Title


Date: Sheet of



A3


HR UMA

Title


Date: Sheet of



A3


HR UMA

SSID = CPU

B4:VREF_DQ CHA

D1:VREF_DQ CHB

0:Lane Reversed

1: Normal Operation; Lane # definition matches socket pin map definition

PEG Static Lane Reversal

CFG2

RN701SRN1KJ-7-GPRN701SRN1KJ-7-GP

1 2

34

R

E

S

E

R

V

E

D

5 OF 9

SANDY

CPU1E

SANDY

R

E

S

E

R

V

E

D

5 OF 9

SANDY

CPU1E

SANDY

CFG0AK28CFG1AK29CFG2AL26CFG3AL27CFG4AK26CFG5AL29CFG6AL30CFG7AM31CFG8AM32CFG9AM30CFG10AM28CFG11AM26CFG12AN28CFG13AN31CFG14AN26CFG15AM27CFG16AK31CFG17AN29

RSVD#AM33 AM33RSVD#AJ27 AJ27

RSVD#J16 J16

RSVD#AT34 AT34

RSVD#H16 H16RSVD#G16 G16

RSVD#AR35 AR35

RSVD#AT33 AT33

RSVD#AR34 AR34

RSVD#AT2 AT2RSVD#AT1 AT1RSVD#AR1 AR1

RSVD#B34 B34RSVD#A33 A33RSVD#A34 A34RSVD#B35 B35RSVD#C35 C35

RSVD#AJ32 AJ32RSVD#AK32 AK32

RSVD#AE7 AE7RSVD#AK2 AK2

RSVD#L7 L7RSVD#AG7 AG7

RSVD#J15J15

RSVD#C30C30RSVD#D23D23

RSVD#A31A31RSVD#B30B30

RSVD#D30D30RSVD#B29B29

RSVD#A30A30RSVD#B31B31

RSVD#C29C29

RSVD#J20J20

RSVD#T8 T8

RSVD#B4B4RSVD#D1D1

RSVD#F25F25RSVD#F24F24

RSVD#D24D24RSVD#G25G25RSVD#G24G24RSVD#E23E23

RSVD#W8 W8

RSVD#AT26 AT26

RSVD#B18B18

RSVD#AP35 AP35

RSVD#F23F23

RSVD#AJ26AJ26

RSVD#AJ31AJ31RSVD#AH31AH31RSVD#AJ33AJ33RSVD#AH33AH33

RSVD#AH27 AH27

RSVD#A19A19

RSVD#AN35 AN35RSVD#AM35 AM35

R702Do Not Stuff

DIS_PX_Muxless R702Do Not Stuff

DIS_PX_Muxless

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_CPU_SVIDALRT#

H_CPU_SVIDDAT

VCC_CORE

VCC_CORE

1D05V_VTT

1D05V_VTT

VCC_CORE

1D05V_VTT

VCCIO_SENSE 45

H_CPU_SVIDDAT 42

VR_SVID_ALERT# 42H_CPU_SVIDCLK 42

VCCSENSE 42VSSSENSE 42

VSSIO_SENSE 45

Title


Date: Sheet of


JE40-HR -1CPU (VCC_CORE)

Custom


HR UMA

Title


Date: Sheet of



Custom


HR UMA

Title


Date: Sheet of



Custom


HR UMA

No-stuff sites outside the socket may be removed.No-stuff sites inside the socket cavity need to remain.

VCC Output Decoupling Recommendation:4 x 470 uF at Bottom Socket Edge8 x 22 uF at Top Socket Cavity8 x 22 uF at Top Socket Edge8 x 22 uF at Bottom Socket Cavity

VCCIO Output Decoupling Recommendation:2 x 330 uF (3 x 330 uF for 2012 capable designs)5 x 22 uF & 5 x 0805 no-stuff at Bottom7 x 22 uF & 2 x 0805 no-stuff at Top

R801,R802 close to CPU

SSID = CPU

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7For CRB VIDALERT# need to pull high 75 ohm close to CPU

53APROCESSOR CORE POWER

C

8

1

9

D

o

N

o

t

S

t

u

f

f

DY

C

8

1

9

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

8

3

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

3

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

2

1

D

o

N

o

t

S

t

u

f

f

DY

C

8

2

1

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

8

3

8

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

3

8

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

3

1

D

o

N

o

t

S

t

u

f

f

DY

C

8

3

1

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

8

3

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

3

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

0

2

D

o

N

o

t

S

t

u

f

f

DYC

8

0

2

D

o

N

o

t

S

t

u

f

f

DY1

2

R802100R2F-L1-GP-UR802100R2F-L1-GP-U

1

2

C

8

2

0

D

o

N

o

t

S

t

u

f

f

DY

C

8

2

0

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

8

3

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

3

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

2

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

2

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

2

9

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

2

9

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

4

1

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

4

1

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

0

3

D

o

N

o

t

S

t

u

f

f

DY

C

8

0

3

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

8

4

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

4

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

2

8

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

2

8

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

3

9

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

3

9

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

1

2

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

1

2

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

2

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

2

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

0

4

D

o

N

o

t

S

t

u

f

f

DY

C

8

0

4

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

8

4

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

4

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

2

5

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

2

5

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

1

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

1

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

3

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

3

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

8

1

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

1

0

S

C

1

0

U

6

D

3

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1

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1

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8

2

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1

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1

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0

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1

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1

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1

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1

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8

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1

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1

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1

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1

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1

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2

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4

3

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8

4

3

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R804 130R2F-1-GPR804 130R2F-1-GP1 2

R801100R2F-L1-GP-UR801100R2F-L1-GP-U

1

2

C

8

4

2

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8

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1

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1

7

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1

7

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1

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8

3

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C

8

3

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9

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1

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K

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8

0

9

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1

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1

2

C

8

2

7

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1

0

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6

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1

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C

8

2

7

S

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1

0

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6

D

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5

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1

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1

2

POWER

C

O

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L

Y

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E

G

A

N

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D

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R

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6 OF 9

SANDY

CPU1F

SANDY

POWER

C

O

R

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U

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L

Y

P

E

G

A

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D

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6 OF 9

SANDY

CPU1F

SANDY

VCC_SENSE AJ35VSS_SENSE AJ34

VIDALERT# AJ29VIDSCLK AJ30VIDSOUT AJ28

VSSIO_SENSE A10

VCCAG35VCCAG34VCCAG33VCCAG32VCCAG31VCCAG30VCCAG29VCCAG28VCCAG27VCCAG26VCCAF35VCCAF34VCCAF33VCCAF32VCCAF31VCCAF30VCCAF29VCCAF28VCCAF27VCCAF26VCCAD35VCCAD34VCCAD33VCCAD32VCCAD31VCCAD30VCCAD29VCCAD28VCCAD27VCCAD26VCCAC35VCCAC34VCCAC33VCCAC32VCCAC31VCCAC30VCCAC29VCCAC28VCCAC27VCCAC26VCCAA35VCCAA34VCCAA33VCCAA32VCCAA31VCCAA30VCCAA29VCCAA28VCCAA27VCCAA26VCCY35VCCY34VCCY33VCCY32VCCY31VCCY30VCCY29VCCY28VCCY27VCCY26VCCV35VCCV34VCCV33VCCV32VCCV31VCCV30VCCV29VCCV28VCCV27VCCV26VCCU35VCCU34VCCU33VCCU32VCCU31VCCU30VCCU29VCCU28VCCU27VCCU26VCCR35VCCR34VCCR33VCCR32VCCR31VCCR30VCCR29VCCR28VCCR27VCCR26VCCP35VCCP34VCCP33VCCP32VCCP31VCCP30VCCP29VCCP28VCCP27VCCP26

VCCIO AH13

VCCIO J11

VCCIO G12VCCIO F14VCCIO F13VCCIO F12VCCIO F11VCCIO E14VCCIO E12

VCCIO AH10VCCIO AG10VCCIO AC10VCCIO Y10VCCIO U10VCCIO P10VCCIO L10VCCIO J14VCCIO J13VCCIO J12

VCCIO H14VCCIO H12VCCIO H11VCCIO G14VCCIO G13

VCCIO E11

VCCIO C12VCCIO C11VCCIO B14VCCIO B12VCCIO A14VCCIO A13VCCIO A12VCCIO A11

VCCIO D14VCCIO D13VCCIO D12VCCIO D11VCCIO C14VCCIO C13

VCCIO_SENSE B10

VCCIO J23C8

3

7

S

C

1

0

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6

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3

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1

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1

2

C

8

1

8

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f

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DY

C

8

1

8

D

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N

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t

S

t

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f

f

DY

1

2

R80343R2J-GPR80343R2J-GP1 2

C

8

2

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

8

2

4

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1

0

U

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-

1

G

P

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSS_AXG_SENSEVCC_AXG_SENSE

H_FC_C22

VCCUSA_SENSE

VCC_GFXCORE

VCC_GFXCORE

1D8V_S0

VCC_GFXCORE

1D5V_S0

0D85V_S0

0D85V_S0

VCC_AXG_SENSE 42VSS_AXG_SENSE 42

+V_SM_VREF_CNT 37

VCCSA_SEL 48

Title


Date: Sheet of


JE40-HR -1CPU (VCC_GFXCORE)

A3


HR UMA

Title


Date: Sheet of



A3


HR UMA

Title


Date: Sheet of



A3


HR UMA

SSID = CPU VAXG Output Decoupling Recommendation:2 x 470 uF at Bottom Socket Edge2 x 22 uF at Top Socket Cavity4 x 22 uF at Top Socket Edge2 x 22 uF at Bottom Socket Cavity4 x 22 uF at Bottom Socket Edge

PROCESSOR VAXG: 24A

VCCPLL Output Decoupling Recommendation:1 x 330 uF2 x 1 uF1 x 10 uF

Disabling Guidelines for External Graphics Designs:Can connect to GND if motherboard only supports externalgraphics and if GFX VR is not stuffed.Can be left floating (Gfx VR keeps VAXG rail from floating)if the VR is stuffed

PROCESSOR VCCPLL: 1.2A

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.+V_SM_VREF_CNT should have 10 mil trace width

R906,R907 close to CPU

PROCESSOR VCCSA: 6A

VDDQ Output Decoupling Recommendation:1 x 330 uF6 x 10 uF

PROCESSOR VDDQ: 10A

VCCSA Output Decoupling Recommendation:1 x 330 uF2 x 10 uF at Bottom Socket Cavity1 x 10 uF at Bottom Socket Edge

Routing Guideline:Power from DDR_VREF_S3 and +V_SM_VREF_CNTshould have 10 mils trace width.

R902 need be close to pin H23.

C

9

1

4

D

o

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t

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f

f

DY

C

9

1

4

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o

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1

2

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9

1

5

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1

0

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3

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1

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1

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C

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1

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2

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5

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UMA_PX_Muxless

C

9

0

5

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1

0

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6

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3

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5

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1

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UMA_PX_Muxless

1

2

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2

1

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0

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UMA_PX_Muxless

C

9

2

1

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1

0

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6

D

3

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5

K

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1

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UMA_PX_Muxless

1

2

C

9

0

2

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C

1

0

U

6

D

3

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5

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1

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UMA_PX_Muxless

C

9

0

2

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1

0

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6

D

3

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5

K

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1

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UMA_PX_Muxless

1

2

C

9

1

2

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C

1

0

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UMA_PX_Muxless

C

9

2

0

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1

0

U

6

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3

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5

K

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1

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UMA_PX_Muxless

1

2

C

9

2

2

S

C

1

U

1

0

V

2

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1

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C

9

2

2

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C

1

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1

0

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2

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1

2

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0

9

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0

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1

2

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0

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f

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DY

C

9

0

7

D

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N

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t

S

t

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f

f

DY

1

2

R906100R2F-L1-GP-UR906100R2F-L1-GP-U

1

2

R90210R2J-2-GPR90210R2J-2-GP

1

2

C

9

1

9

S

C

1

0

U

6

D

3

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5

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-

1

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UMA_PX_Muxless

C

9

1

9

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C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

UMA_PX_Muxless

1

2

R907100R2F-L1-GP-UR907100R2F-L1-GP-U

1

2

C

9

0

8

S

C

1

0

U

6

D

3

V

5

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1

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UMA_PX_Muxless

C

9

0

8

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

UMA_PX_Muxless

1

2

R901Do Not Stuff

DIS

R901Do Not Stuff

DIS

1

2

C

9

0

6

D

o

N

o

t

S

t

u

f

f

DY

C

9

0

6

D

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N

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1

2

C

9

1

1

S

C

1

0

U

6

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3

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5

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1

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C

9

1

1

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1

0

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3

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1

2

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0

3

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6

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3

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5

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1

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UMA_PX_Muxless

C

9

0

3

S

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1

0

U

6

D

3

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5

K

X

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1

G

P

UMA_PX_Muxless

1

2

C

9

0

4

S

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1

0

U

6

D

3

V

5

K

X

-

1

G

P

UMA_PX_Muxless

C

9

0

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

UMA_PX_Muxless

1

2

R904Do Not Stuff

DIS

R904Do Not Stuff

DIS

1

2

RN901SRN1KJ-7-GPRN901SRN1KJ-7-GP

12

3 4

POWER

G

R

A

P

H

I

C

S

D

D

R

3

-

1

.

5

V

R

A

I

L

S

S

E

N

S

E

L

I

N

E

S

1

.

8

V

R

A

I

L

S

A

R

A

I

L

V

R

E

F

M

I

S

C

7 OF 9

SANDY

CPU1G

SANDY

POWER

G

R

A

P

H

I

C

S

D

D

R

3

-

1

.

5

V

R

A

I

L

S

S

E

N

S

E

L

I

N

E

S

1

.

8

V

R

A

I

L

S

A

R

A

I

L

V

R

E

F

M

I

S

C

7 OF 9

SANDY

CPU1G

SANDY

SM_VREF AL1

VSSAXG_SENSE AK34VAXG_SENSE AK35VAXGAT24

VAXGAT23VAXGAT21VAXGAT20VAXGAT18VAXGAT17VAXGAR24VAXGAR23VAXGAR21VAXGAR20VAXGAR18VAXGAR17VAXGAP24VAXGAP23VAXGAP21VAXGAP20VAXGAP18VAXGAP17VAXGAN24VAXGAN23VAXGAN21VAXGAN20VAXGAN18VAXGAN17VAXGAM24VAXGAM23VAXGAM21VAXGAM20VAXGAM18VAXGAM17VAXGAL24VAXGAL23VAXGAL21VAXGAL20VAXGAL18VAXGAL17VAXGAK24VAXGAK23VAXGAK21VAXGAK20VAXGAK18VAXGAK17VAXGAJ24VAXGAJ23VAXGAJ21VAXGAJ20VAXGAJ18VAXGAJ17VAXGAH24VAXGAH23VAXGAH21VAXGAH20VAXGAH18VAXGAH17

VDDQ U4VDDQ U1VDDQ P7VDDQ P4VDDQ P1

VDDQ AF7VDDQ AF4VDDQ AF1VDDQ AC7VDDQ AC4VDDQ AC1VDDQ Y7VDDQ Y4VDDQ Y1VDDQ U7

VCCPLLB6VCCPLLA6

VCCSA M27VCCSA M26VCCSA L26VCCSA J26VCCSA J25VCCSA J24VCCSA H26VCCSA H25

VCCSA_SENSE H23

VCCSA_VID1 C24

VCCPLLA2

FC_C22 C22

TP901 Do Not StuffTP901 Do Not Stuff1

C

9

1

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

9

1

0

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

R903Do Not Stuff

DIS

R903Do Not Stuff

DIS

1

2

C

9

1

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

9

1

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

R905Do Not Stuff

DIS

R905Do Not Stuff

DIS

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


JE40-HR -1CPU (VSS)

A3


HR UMA

Title


Date: Sheet of


JE40-HR -1CPU (VSS)

A3


HR UMA

Title


Date: Sheet of


JE40-HR -1CPU (VSS)

A3


HR UMA

SSID = CPU

VSS

8 OF 9

SANDY

CPU1H

SANDY

VSS

8 OF 9

SANDY

CPU1H

SANDY

VSSAT35VSSAT32VSSAT29VSSAT27VSSAT25VSSAT22VSSAT19VSSAT16VSSAT13VSSAT10VSSAT7VSSAT4VSSAT3VSSAR25VSSAR22VSSAR19VSSAR16VSSAR13VSSAR10VSSAR7VSSAR4VSSAR2VSSAP34VSSAP31VSSAP28VSSAP25VSSAP22VSSAP19VSSAP16VSSAP13VSSAP10VSSAP7VSSAP4VSSAP1VSSAN30VSSAN27VSSAN25VSSAN22VSSAN19VSSAN16VSSAN13VSSAN10VSSAN7VSSAN4VSSAM29VSSAM25VSSAM22VSSAM19VSSAM16VSSAM13VSSAM10VSSAM7VSSAM4VSSAM3VSSAM2VSSAM1VSSAL34VSSAL31VSSAL28VSSAL25VSSAL22VSSAL19VSSAL16VSSAL13VSSAL10VSSAL7VSSAL4VSSAL2VSSAK33VSSAK30VSSAK27VSSAK25VSSAK22VSSAK19VSSAK16VSSAK13VSSAK10VSSAK7VSSAK4VSSAJ25

VSS AJ22VSS AJ19VSS AJ16VSS AJ13VSS AJ10VSS AJ7VSS AJ4VSS AJ3VSS AJ2VSS AJ1VSS AH35VSS AH34VSS AH32VSS AH30VSS AH29VSS AH28VSS AH26VSS AH25VSS AH22VSS AH19VSS AH16VSS AH7VSS AH4VSS AG9VSS AG8VSS AG4VSS AF6VSS AF5VSS AF3VSS AF2VSS AE35VSS AE34VSS AE33VSS AE32VSS AE31VSS AE30VSS AE29VSS AE28VSS AE27VSS AE26VSS AE9VSS AD7VSS AC9VSS AC8VSS AC6VSS AC5VSS AC3VSS AC2VSS AB35VSS AB34VSS AB33VSS AB32VSS AB31VSS AB30VSS AB29VSS AB28VSS AB27VSS AB26VSS Y9VSS Y8VSS Y6VSS Y5VSS Y3VSS Y2VSS W35VSS W34VSS W33VSS W32VSS W31VSS W30VSS W29VSS W28VSS W27VSS W26VSS U9VSS U8VSS U6VSS U5VSS U3VSS U2

VSS

9 OF 9

SANDY

CPU1I

SANDY

VSS

9 OF 9

SANDY

CPU1I

SANDY

VSST35VSST34VSST33VSST32VSST31VSST30VSST29VSST28VSST27VSST26VSSP9VSSP8VSSP6VSSP5VSSP3VSSP2VSSN35VSSN34VSSN33VSSN32VSSN31VSSN30VSSN29VSSN28VSSN27VSSN26VSSM34VSSL33VSSL30VSSL27VSSL9VSSL8VSSL6VSSL5VSSL4VSSL3VSSL2VSSL1VSSK35VSSK32VSSK29VSSK26VSSJ34VSSJ31VSSH33VSSH30VSSH27VSSH24VSSH21VSSH18VSSH15VSSH13VSSH10VSSH9VSSH8VSSH7VSSH6VSSH5VSSH4VSSH3VSSH2VSSH1VSSG35VSSG32VSSG29VSSG26VSSG23VSSG20VSSG17VSSG11VSSF34VSSF31VSSF29

VSS F22VSS F19VSS E30VSS E27VSS E24VSS E21VSS E18VSS E15VSS E13VSS E10VSS E9VSS E8VSS E7VSS E6VSS E5VSS E4VSS E3VSS E2VSS E1VSS D35VSS D32VSS D29VSS D26VSS D20VSS D17VSS C34VSS C31VSS C28VSS C27VSS C25VSS C23VSS C10VSS C1VSS B22VSS B19VSS B17VSS B15VSS B13VSS B11VSS B9VSS B8VSS B7VSS B5VSS B3VSS B2VSS A35VSS A32VSS A29VSS A26VSS A23VSS A20VSS A3

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


JE40-HR -1XDP

A3


HR UMA

Title


Date: Sheet of


JE40-HR -1XDP

A3


HR UMA

Title


Date: Sheet of


JE40-HR -1XDP

A3


HR UMA

JE40 delete XDP function

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


JE40-HR -1Reserved

A4


HR UMA

Title


Date: Sheet of


JE40-HR -1Reserved

A4


HR UMA

Title


Date: Sheet of


JE40-HR -1Reserved

A4


HR UMA

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_A1

M_A_DQS#0



M_A_DQS3

M_A_DQ0

M_A_DQS#5

M_A_A2



M_A_DQS4

M_A_A3

M_A_DQS#6



M_A_DQ1

M_A_A4

M_A_DQS5

M_A_DQS#7



M_A_DQS#1

M_A_A5

M_A_DQ2

M_A_DQS6


M_A_DQS0


M_A_A7M_A_A8M_A_A9M_A_A10M_A_A11

M_A_A6

M_A_DQ3

M_A_DQS#2

M_A_DQS7



M_A_DQS1

M_A_A13M_A_A14M_A_A15

M_A_A12


M_A_DQS#3

M_A_A0



M_A_DQS2

M_A_DQS#4

TS#_DIMM0_1

1D5V_S3

3D3V_S0

0D75V_S0

DDR_VREF_S3

3D3V_S0

1D5V_S3

DDR_VREF_S3

0D75V_S0

DDR3_DRAMRST#15,37

M_A_DIM0_ODT06M_A_DIM0_ODT16

M_A_BS26

M_A_BS06M_A_BS16

M_A_DQ[63:0]6

TS#_DIMM0_1 15

PCH_SMBCLK 15,20PCH_SMBDATA 15,20

M_A_WE# 6

M_A_DIM0_CS#0 6

M_A_CAS# 6

M_A_DIM0_CKE0 6M_A_DIM0_CKE1 6

M_A_DIM0_CS#1 6



M_A_RAS# 6M_A_A[15:0] 6

M_A_DQS#[7:0] 6

M_A_DQS[7:0] 6

Title


Date: Sheet of


JE40-HR -1DDR3-SODIMM1

Custom


HR UMA

Title


Date: Sheet of



Custom


HR UMA

Title


Date: Sheet of



Custom


HR UMA

H =4mm

SSID = MEMORY

Note:If SA0 DIM0 = 0, SA1_DIM0 = 0SO-DIMMA SPD Address is 0xA0SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0SO-DIMMA SPD Address is 0xA2SO-DIMMA TS Address is 0x32

Thermal EVENT

SODIMM A DECOUPLINGLayout Note:Place these Caps nearSO-DIMMA.

PART NUMBER Height TYPE

Place these capsclose to VTT1 andVTT2.

-2

C

1

4

0

5

D

o

N

o

t

S

t

u

f

f

DY C1

4

0

5

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

1

4

1

6

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

1

6

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C

1

4

1

7

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

4

1

7

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C

1

4

0

9

S

C

D

1

U

5

0

V

3

K

X

-

G

P

3G_RF

C

1

4

0

9

S

C

D

1

U

5

0

V

3

K

X

-

G

P

3G_RF

1

2

R140310KR2J-3-GP

R140310KR2J-3-GP

1 2

C

1

4

0

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

4

0

4

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

4

0

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

4

0

3

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C1413

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C1413

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C

1

4

1

9

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

4

1

9

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1

2

C

1

4

2

1

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

4

2

1

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1

2

C1401

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C1401

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C

1

4

1

0

S

C

D

1

U

5

0

V

3

K

X

-

G

P

3G_RF

C

1

4

1

0

S

C

D

1

U

5

0

V

3

K

X

-

G

P

3G_RF

1

2

C

1

4

0

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

4

0

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

4

0

8

SC

56P50V

2JN-2G

P

3G_RF

C

1

4

0

8

SC

56P50V

2JN-2G

P

3G_RF

1

2

DM1DDR3-204P-122-GP62.10017.Z512nd = 62.10017.V513rd = 62.10017.M514th = 62.10017.X41

DM1DDR3-204P-122-GP62.10017.Z512nd = 62.10017.V513rd = 62.10017.M514th = 62.10017.X41

A098A197A296A395A492A591A690A786A889A985A10/AP107A1184A1283A13119A1480A1578A16/BA279

BA0109BA1108

DQ05DQ17DQ215DQ317DQ44DQ56DQ616DQ718DQ821DQ923DQ1033DQ1135DQ1222DQ1324DQ1434DQ1536DQ1639DQ1741DQ1851DQ1953DQ2040DQ2142DQ2250DQ2352DQ2457DQ2559DQ2667DQ2769DQ2856DQ2958DQ3068DQ3170DQ32129DQ33131DQ34141DQ35143DQ36130DQ37132DQ38140DQ39142DQ40147DQ41149DQ42157DQ43159DQ44146DQ45148DQ46158DQ47160DQ48163DQ49165DQ50175DQ51177DQ52164DQ53166DQ54174DQ55176DQ56181DQ57183DQ58191DQ59193DQ60180DQ61182DQ62192DQ63194

DQS0#10DQS1#27DQS2#45DQS3#62DQS4#135DQS5#152DQS6#169DQS7#186

DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188

ODT0116ODT1120

VREF_DQ1

VSS 2

NP1 NP1NP2 NP2

RAS# 110WE# 113

CAS# 115

CS0# 114CS1# 121

CKE0 73CKE1 74

CK0 101CK0# 103

CK1 102CK1# 104

DM0 11DM1 28DM2 46DM3 63DM4 136DM5 153DM6 170DM7 187

SDA 200SCL 202

VDDSPD 199

SA0 197SA1 201

VREF_CA126

VDD18 124

NC#1 77NC#2 122

NC#/TEST 125

VDD3 81VDD4 82VDD5 87VDD6 88VDD7 93VDD8 94VDD9 99

VDD10 100

VDD13 111VDD14 112VDD15 117VDD16 118

VSS 3VSS 8VSS 9VSS 13VSS 14VSS 19VSS 20VSS 25VSS 26VSS 31VSS 32VSS 37VSS 38VSS 43VSS 44VSS 48VSS 49VSS 54VSS 55VSS 60VSS 61

VDD1 75

VSS 65VSS 66VSS 71VSS 72

VDD2 76

VDD11 105VDD12 106

VDD17 123

VSS 127VSS 128

VSS 134VSS 133


VSS 151VSS 150

VSS 155VSS 156VSS 161VSS 162VSS 167VSS 168

VSS 173VSS 172

VSS 179VSS 178

VSS 185VSS 184


RESET#30

EVENT# 198

VSS 205VSS 206

VTT1203VTT2204

C

1

4

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

4

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C1411

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C1411

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_B_A1

M_B_DQ42M_B_DQ41M_B_DQ40

M_B_DQS#0

M_B_DQ43


M_B_DQ15

M_B_DQS3

M_B_DQ0

M_B_A2

M_B_DQS#5


M_B_DQ47


M_B_DQS4

M_B_A3

M_B_DQS#6



SA1_DIM1

M_B_DQ1

M_B_A4

M_B_DQS5

M_B_DQS#7

M_B_DQ53M_B_DQ52

M_B_DQ24

M_B_DQ55M_B_DQ54


M_B_DQS#1

M_B_DQ2

M_B_A5

M_B_DQS6

M_B_DQ57M_B_DQ56

M_B_DQS0

M_B_DQ59M_B_DQ58


M_B_A7M_B_A6

M_B_A11M_B_A10M_B_A9M_B_A8

M_B_DQ3

M_B_DQS#2

M_B_DQS7


M_B_DQ33M_B_DQ32

M_B_DQ35M_B_DQ34

M_B_DQS1

M_B_A12

M_B_A15M_B_A14M_B_A13

M_B_DQ5M_B_DQ4

M_B_DQ7M_B_DQ6

M_B_DQS#3

M_B_A0


M_B_DQ8


M_B_DQS2

M_B_DQS#4

1D5V_S3

3D3V_S0

0D75V_S0

1D5V_S3

DDR_VREF_S3

DDR_VREF_S3

0D75V_S0

DDR3_DRAMRST#14,37

M_B_BS06

M_B_BS26

M_B_BS16M_B_DQ[63:0]6

TS#_DIMM0_1 14

PCH_SMBCLK 14,20PCH_SMBDATA 14,20

M_B_A[15:0] 6

M_B_DQS[7:0] 6

M_B_DQS#[7:0] 6

M_B_DIM0_ODT06M_B_DIM0_ODT16

M_B_WE# 6

M_B_DIM0_CS#0 6

M_B_CAS# 6

M_B_DIM0_CKE0 6M_B_DIM0_CKE1 6

M_B_DIM0_CS#1 6



M_B_RAS# 6

Title


Date: Sheet of



Custom


HR UMA

Title


Date: Sheet of



Custom


HR UMA

Title


Date: Sheet of



Custom


HR UMA

Note:SO-DIMMB SPD Address is 0xA4SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther fromthe Processor than SO-DIMMA

H = 8mm

SSID = MEMORY

SODIMM B DECOUPLING

Layout Note:Place these Caps nearSO-DIMMB.

Place these capsclose to VTT1 andVTT2.

-2

C

1

5

0

9

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

5

0

9

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

5

0

4

S

C

5

6

P

5

0

V

2

J

N

-

2

G

P

3G_RF

C

1

5

0

4

S

C

5

6

P

5

0

V

2

J

N

-

2

G

P

3G_RF

1

2

DM2DDR3-204P-126-GP62.10024.D41

2nd = 62.10017.R913rd = 62.10017.V614th = 62.10017.X51

DM2DDR3-204P-126-GP62.10024.D41

2nd = 62.10017.R913rd = 62.10017.V614th = 62.10017.X51

A098A197A296A395A492A591A690A786A889A985A10/AP107A1184A1283A13119A1480A1578A16/BA279

BA0109BA1108

DQ05DQ17DQ215DQ317DQ44DQ56DQ616DQ718DQ821DQ923DQ1033DQ1135DQ1222DQ1324DQ1434DQ1536DQ1639DQ1741DQ1851DQ1953DQ2040DQ2142DQ2250DQ2352DQ2457DQ2559DQ2667DQ2769DQ2856DQ2958DQ3068DQ3170DQ32129DQ33131DQ34141DQ35143DQ36130DQ37132DQ38140DQ39142DQ40147DQ41149DQ42157DQ43159DQ44146DQ45148DQ46158DQ47160DQ48163DQ49165DQ50175DQ51177DQ52164DQ53166DQ54174DQ55176DQ56181DQ57183DQ58191DQ59193DQ60180DQ61182DQ62192DQ63194

DQS0#10DQS1#27DQS2#45DQS3#62DQS4#135DQS5#152DQS6#169DQS7#186

DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188

ODT0116ODT1120

VREF_DQ1

VSS 2

NP1 NP1NP2 NP2

RAS# 110WE# 113

CAS# 115

CS0# 114CS1# 121

CKE0 73CKE1 74

CK0 101CK0# 103

CK1 102CK1# 104

DM0 11DM1 28DM2 46DM3 63DM4 136DM5 153DM6 170DM7 187

SDA 200SCL 202

VDDSPD 199

SA0 197SA1 201

VREF_CA126

VDD18 124

NC#1 77NC#2 122

NC#/TEST 125

VDD3 81VDD4 82VDD5 87VDD6 88VDD7 93VDD8 94VDD9 99

VDD10 100

VDD13 111VDD14 112VDD15 117VDD16 118

VSS 3VSS 8VSS 9VSS 13VSS 14VSS 19VSS 20VSS 25VSS 26VSS 31VSS 32VSS 37VSS 38VSS 43VSS 44VSS 48VSS 49VSS 54VSS 55VSS 60VSS 61

VDD1 75


VDD2 76

VDD11 105VDD12 106

VDD17 123

VSS 127VSS 128

VSS 134VSS 133


VSS 151VSS 150

VSS 155VSS 156VSS 161VSS 162VSS 167VSS 168

VSS 173VSS 172

VSS 179VSS 178

VSS 185VSS 184


RESET#30

EVENT# 198

VSS 205VSS 206

VTT1203VTT2204

R150110KR2J-3-GPR150110KR2J-3-GP

12

C

1

5

1

4

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

5

1

4

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C

1

5

1

0

SC

D1U

50V3K

X-G

P

3G_RF

C

1

5

1

0

SC

D1U

50V3K

X-G

P

3G_RF

1

2

C1503SC

5D6P

50V2C

N-1G

P

3G_RF

C1503SC

5D6P

50V2C

N-1G

P

3G_RF

1

2

C1501SC

D1U

10V2K

X-5G

P

C1501SC

D1U

10V2K

X-5G

P

1

2

C

1

5

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

5

0

7

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

5

1

3

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

C

1

5

1

3

S

C

D

1

U

1

0

V

2

K

X

-

5

G

P

1

2

C1517

SC

D1U

10V2K

X-5G

P

C1517

SC

D1U

10V2K

X-5G

P

1

2

C

1

5

0

8

S

C

D

1

U

5

0

V

3

K

X

-

G

P

3G_RF

C

1

5

0

8

S

C

D

1

U

5

0

V

3

K

X

-

G

P

3G_RF

1

2

C1515

SC

D1U

10V2K

X-5G

P

C1515

SC

D1U

10V2K

X-5G

P

1

2

C

1

5

0

5

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

5

0

5

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

C

1

5

1

9

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

5

1

9

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1

2

C

1

5

2

1

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

1

5

2

1

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1

2

C

1

5

0

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

C

1

5

0

6

S

C

1

0

U

6

D

3

V

5

K

X

-

1

G

P

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of



A4


HR UMA

Title


Date: Sheet of



A4


HR UMA

Title


Date: Sheet of



A4


HR UMA

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LVDS_IBG

DAC_IREF_R

LVDS_VREFHLVDS_VREFL

L_CTRL_DATAL_CTRL_CLK

LVDS_VDD_EN

CRT_RED

L_CTRL_DATA

CRT_BLUE

L_BKLT_EN

CRT_GREEN

L_CTRL_CLK

DDBP_DATA0DDBP_DATA0#

DDBP_DATA2#DDBP_DATA2

DDBP_CLK#

DDBP_DATA1#

DDBP_CLK

DDBP_DATA1

3D3V_S03D3V_S0

CRT_HSYNC95CRT_VSYNC95

LVDS_DDC_CLK_R94LVDS_DDC_DATA_R94

LVDSA_DATA094LVDSA_DATA194LVDSA_DATA294

LVDSA_DATA0#94LVDSA_DATA1#94LVDSA_DATA2#94

LVDSA_CLK#94LVDSA_CLK94

L_BKLT_CTRL94

LVD

acer aspire 4750g je40-hr rev -1

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