active high power conversion efficiency rectifier with built-in dual

184 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 2, NO. 3, SEPTEMBER 2008

Active High Power Conversion Efficiency RectifierWith Built-In Dual-Mode Back Telemetry in

Standard CMOS TechnologyGaurav Bawa, Student Member, IEEE, and Maysam Ghovanloo, Member, IEEE

Abstract—In this paper, we present an active rectifier with highpower conversion efficiency (PCE) implemented in a 0.5- m 5V standard CMOS technology with two modes of built-in backtelemetry; short- and open-circuit. As a rectifier, it ensures a�� , taking advantage of active synchronous recti-fication technique in the frequency range of 0.125–1 MHz. Thebuilt-in complementary back telemetry feature can be utilized inimplantable microelectronic devices (IMD), wireless sensors, andradio frequency identification (RFID) applications to reduce thesilicon area, increase the data rate, and improve the reading rangeand robustness in load shift keying (LSK).

Index Terms—Back telemetry, CMOS, full-wave rectifier, im-plantable microelectronic devices, inductive link, radio frequencyidentification (RFID), wireless.

I. INTRODUCTION

S IZE-CONSTRAINED high power implantable microelec-tronic devices (IMD) such as retinal and cochlear implants,

low-cost passive radio frequency identification (RFID) tags, andmany wireless sensors cannot accommodate any internal energysources in the form of batteries due to their low energy density,high cost, and limited lifetime [1]–[5]. There is also a need fordata to be transferred from such systems to the outside worldwhich may include the status of the implant, a feedback loop, orother stored or collected information [4], [5]–[12]. In applica-tions where high data rates are not necessary, wireless power andbidirectional data transmission can occur by modulating a singlecarrier at 20 MHz and using load-shift keying (LSK)through an inductive link, as shown in Fig. 1. LSK requires ei-ther a good coupling between the transponder and reader coilsor large variations in the impedance seen across the transpondercoil [5], [13].

With the size of the transponder being limited, the small cou-pling, , between the coils forms a bottleneck in power and

Manuscript received November 07, 2007; revised February 11, 2008 andApril 04, 2008. Current version published October 24, 2008. This work wassupported in part by the College of Engineering at North Carolina State Uni-versity (NCSU), Raleigh. This paper was recommended by Associate EditorM. Sawan.

G. Bawa is with the NC-Bionics Laboratory, Department of Electrical andComputer Engineering North Carolina State University, Raleigh, NC 27695,USA (e-mail: [email protected]).

M. Ghovanloo is with the GT-Bionics Laboratory, School of Electrical andComputer Engineering, Georgia Institute of Technology, Atlanta, GA 30308USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TBCAS.2008.924444

Fig. 1. Block diagram of a generic system for wireless power and data trans-mission across an inductive link. Our focus, here, is on the gray box.

data transmission. On the power front, it is imperative for therectifier to be extremely efficient to convert the small receivedac power to dc and present it to the load with minimum dissi-pation. A more efficient rectifier can deliver a given amount ofpower for a lesser voltage induced across the secondary coil.Thus, it requires a smaller coupling coefficient, , and allowsfor a greater relative distance between the coils. Active recti-fiers have been proven to be more efficient compared to theirdiode-connected passive counterparts in several prior designs[14]–[17]. They also generate less heat for the same amount ofpower being delivered to the load, keeping the IMD and its sur-rounding tissue cooler [18].

On the data front, it is important to maximize the changes intransponder impedance variations to compensate for the smallcoupling coefficient and overcome noise and interference on thereader [5]. Most traditional LSK methods rely on the nominalloading of the transponder to induce the impedance change. Ifthe loading varies over time, which is the case especially in morecomplex systems, the reading range will be adversely affectedbecause one should always consider the worst-case loading indesigning the back telemetry link.

We hereby present a high power conversion efficiency (PCE)active back telemetry rectifier (ABTR), which has built-in dual-mode LSK capability, both open- and short-circuit, enablingtransfer of data back to the reader at higher rates or over fur-ther distances, while accommodating varying load conditions.This is an improvement over an earlier diode-connected versionof this rectifier described in [19].

II. CIRCUIT DESCRIPTION

The complete circuit schematic of the ABTR is shown inFig. 2, and simulated waveforms at some of the important nodes

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BAWA AND GHOVANLOO: ACTIVE HIGH PCE RECTIFIER 185

Fig. 2. Complete active back-telemetry rectifier (ABTR) schematic for forward power and reverse data transmission over an inductive link.

Fig. 3. Simulation results showing the coil voltages (� and � ), divided� voltage �� , gate and bulk voltages for � (� and � , respec-tively), and the dc output voltage �� . � � � MHz.

are shown in Fig. 3. The rectifier has three modes of operationnamely, Rectifier, short-coil (SC) , and open-coil (OC), whichare summarized in Table I. When the two ABTR logic inputsare low , the circuit operates as a full-waverectifier providing an unregulated dc supply to the load. Thebasic architecture of the rectifier is similar to [19], wherein themain rectifying elements are the pMOS pair, , while thenMOS pair, provide the current path back to the coil. In

TABLE IACTIVE BACK TELEMETRY RECTIFIER MODES OF OPERATION

the positive half-cycle when , as a result of rec-tifier switch activation, current flows from to via

, from to Ground (i.e., p-type substrate) via ,and from Ground to via . Therefore, during rectifierconduction, and V by the load cur-rent times the channel resistance of the switching elements orthe voltage across drain-substrate parasitic diode, whichever issmaller. These effects are visible in Fig. 3.

The bulk potential of is given by , which is dy-namically controlled to be connected to the higher of and

, at all times. This helps minimizing latch-up, body effect,and substrate leakage problems as explained in [20]. However,



instead of diode-connecting for rectification, as we did in[19], leading to dropout voltages across each pMOS above thethreshold voltage, , here we actively drive the gates ofvia a pair of high speed comparators, , to bias in thedeep triode region during conduction. This would result in asignificant reduction in the MOS channel resistance and con-sequently the rectifier dropout voltage [21], [22].

compare the coil voltages and the output dcvoltage . If , the gates of are pulledto ground, pushing them deep into the triode region. If

, the gates of are connected to their dynamically con-trolled body potential, , forcing them to cut off. Since atsteady state the switching occurs almost at the peak of the inputcoil voltage, depending on the output ripple, the cross-connected

also stay in deep triode while conduction takes place, thusproviding maximum conductance to the current path and mini-mizing the ABTR dropout voltage.

To ensure proper rectifier operation as described above, wehave employed a pair of comparators with hysteresis, shownin box-2 of Fig. 2 [21]. Each comparator has a folded cascodeinput stage to perform signal comparison even above the railwith some power dissipation overhead (see Table III). It is fol-lowed by an output stage to ensure rail-to-rail swing. The middlestage is essentially a high-speed latch, which provides noise re-jection and immunity to dips in during the conductionphase. This dip, which can be seen in Fig. 3, is due to the cur-rent passing through the rectifying elements and , when

, causing to become slightly negative and hencelowering .

The comparators delay at the onset of , whenswitches are expected to be open, can lead to flow of cur-

rent from the ripple rejection capacitor, , back to the coil.This reverse current can cause coil voltage distortions, increasedpower dissipation in the switches, and decrease due toloss of charge from . To account for the comparators delay, alossless capacitive divider is employed whichgenerates a reduced version of the coil voltage, , at thecomparator inputs. This would expedite comparators’ toggling,and has a phase lead effect, which reduces the reverse currents.A side effect of the capacitive divider is, however, an additionaldelay in firing to close when (seeFig. 3). At nominal loading conditions with F and

k , the dip in was observed to be 101 mV in sim-ulations and correspondingly lowered by 94 mV for aninput division ratio set to 93%. The hysteresis window was,therefore, set to be 100 mV, as a safe margin.

At startup, the output voltage, , is too low and the com-parator outputs are unpredictable. Thus, we employed a smalldiode-connected startup rectifier , similar to [19], in par-allel to the main rectifier to generate a temporary stable supply,

, just for the comparators and the bias-generation cir-cuitry. Once stabilizes by charging up to a certainlevel ( 3.5 V), a voltage monitor circuit, shown in box-5 ofFig. 2, connects and together via , turning thestartup rectifier off due to its larger dropout. The voltage mon-itor has no static power dissipation.

In the SC mode of operation , the secondarytank is shorted by pulling the gates of up to the

Fig. 4. Die photo of the active back telemetry rectifier chip fabricated in AMI0.5-�m standard CMOS process �� mm �.

highest on-chip voltage, . This is accomplished througha pair of on-chip level-shifting multiplexers, (box-3,Fig. 2), which can convert any on-chip logic level to -Ground. The small resistance presented across reducesits quality factor, , thereby decreasing the voltage acrossand the current through it. Since in this mode,

pull the gates of high and keep them off. This wouldeliminate from being discharged through .

In the OC mode of operation ,is opened by connecting the gates of in the mainand startup rectifiers to their respective bulk potentials using

. This would increase of tank, increasingthe voltage across and the current through .

Drastic changes in during SC and OC modes with re-spect to its nominal value in the rectifier mode, which is de-pendant on , result in similar changes in and currentsdue to their mutual inductance, [5]. These changes whencaptured by a small resistor or a current-sense transformer onthe primary side, as shown in Fig. 1, can be used to demodu-late the power carrier amplitude variations and recover the backtelemetry data. Dual-mode back telemetry feature of the pro-posed rectifier can, therefore, provide more variations in andenhance the reading range especially in complex systems where

is variable.

III. MEASUREMENT RESULTS

We have developed a prototype chip for the proposed ABTRarchitecture in the AMI 0.5- m 3M/2P n-well 5-V standardCMOS process. The die photo is shown in Fig. 4, which activearea, excluding the pad frame, is 0.4 mm . The rectifier waspowered by an HP-8111A function generator through a pair ofplanar spiral coils fabricated on PCB [23].

The values for the primary and secondary coils were mea-sured , , 2.24 ; and , ,1.56 , using a high precision LCR meter (Instek-LCR819).and were adjusted to resonate at each desired carrier fre-quency in 2 MHz range, while the rectifier wasloaded with k and F. The current flowinginto the rectifier was differentially measured across a 10 re-sistor connected in series between and the ABTR input.The connection between and Ground was passed through acurrent sense transformer ( , ),as shown in Fig. 1, and the transformer isolated output voltage,



Fig. 5. Measured rectifier PCE and output dc voltage versus (a) carrier fre-quency when and � � � k�, and (b) loading �� when � � �� MHz.� �� V, � � � �F.

called , was directly connected to one of the oscilloscopechannels to monitor the changes in current.

Fig. 5(a) shows the measured performance of the ABTR atdifferent frequencies in terms of the PCE and when it isin the Rectifier mode and is adjusted at 5 V. Weobserved that there exists a fine balance between the input ca-pacitive voltage divider ratio, delay, and hysteresis voltage ofthe comparators (see Section IV). In the present design, we ob-tained the peak and V around

MHz, while was measured in the fre-quency range of –1 MHz. Fig. 5(b) illustrates the ef-fects of on the PCE and for the present ABTR archi-tecture, which also depend on the size of the rectifying elements.For k , PCE decreases due to the increased voltagedrop across and , while the switching duty cycle alsoincreases. For k , the output power becomes compa-rable to the ABTR losses, hence decreasing the PCE.

Fig. 6 shows the measured transient waveforms when theABTR is operated at MHz and switched between OC,rectification, and SC modes, consecutively, by changing its dig-ital inputs at 33 kHz. Even though the SC input is not shown,the effect of each rectifier operating mode and changes inare quite obvious on and . It can also be seen, from

, that exponentially discharges in during OC andSC, and recharges during the normal rectifier operation.

Another observation was that the changes in andduring OC were smaller than those during SC. This was be-cause of the presence of electrostatic discharge protection cir-

Fig. 6. Measured ABTR waveforms showing consecutive OC , Rectifier, andSC modes of operation at � � � MHz, � � �� and � � � k�.

cuitry, shown in box-1 of Fig. 2, as part of the pad-framestructure. These circuits are off during SC mode and normal rec-tifier operation. However during OC mode, when increasesand go beyond the supply rail, turn on and form aleakage path across the rectifier to the rail and eventuallyto the load, . This leakage path clamps at a diode-dropabove and does not allow to increase as much as itshould.

In order to demonstrate the ABTR back telemetry operationthrough SC and OC inputs, and evaluate the effect of dual-mode operation on the reading range and bit-error rate (BER),we generated a 200 kb/s Manchester-encoded serial data bitstream using a digital I/O card. A sample segment of the orig-inal data stream at 100 kb/s and its Manchester-encoded ver-sion are shown on traces 1 and 2 of Fig. 7, respectively. In thisexperiment, the nominal coils separation, loading, and carrierfrequency were mm, k , and MHz,respectively. Data recovery on the primary side involved digi-tization of (trace-3 in Fig. 7) at 250 MHz using a digitaloscilloscope (Tektronix DPO4034) and processing it offline inMATLAB. Zero crossings of were detected to indicate thecarrier signal period and reconstruct the received carrier enve-lope.

There were two types of amplitude variations at the primary;one at high frequency (200 kb/s) due to the rectifier LSK, and theother at low frequency due to fluctuations in the power ampli-fier output voltage, coils separation, and other sources of inter-ference. The undesirable low frequency interference was elimi-nated by running a moving average on , and subtracting itfrom the carrier envelope information. Thereafter, binarizationwas performed by checking the peaks of that were aboveor below the moving threshold. Comparing the resulting wave-form, which is shown on trace-4 of Fig. 7, with trace-2 demon-strates the accuracy of the demodulated serial data bits. Finally,the original symbols were recovered by Manchester decodingtrace-4 via edge detection and retrieval of pulsewidth informa-tion (trace 5).

With this setup in place, the BER was measured by comparingthe back scattered and received data bit streams for a total of



Fig. 7. Waveforms showing (from top) the original and Manchester-encoded data bit streams, primary sensed current, carrier envelope, and recovered backtelemetry data, which was sent through the ABTR OC input at 200 kHz with � � � MHz, � � � k� and � � �� mm.

2048 bits (256-bit frames in 8 trials). However, no errors weredetected. Considering the facts that a dedicated reader was notutilized and the coil dimensions were not optimized, we simplydefined the maximum coil separation, , that could main-tain as the reading range in our test setup. For

k , was 28 and 25 mm for SC and OC modes, re-spectively. When we reduced to 300 , for SC was re-duced to 23 mm, while for OC was increased to 26 mm, de-spite its subdued operation due to the ESD circuitry. This resultwas expected because as mentioned in Section I, maximizingthe transponder impedance variations can improve the readingrange in inductively powered devices. Thus, we could concludethat when was variable, a combination of SC and OC modesincreased the reading range in our experimental setup by 12%compared to using only one of these modes similar to the tradi-tional LSK scheme.

IV. DISCUSSION

In this section we take a closer look at some of the specificcharacteristics of the proposed ABTR, which can potentiallyaffect its PCE and performance in back telemetry.

A. Variations in Loaded in Different Modes of Operation

We talked about variations in the secondary -factor whenthe ABTR changes the tank loading in its 3 modes ofoperation. Here we would like to understand how (loaded

) changes and in what range. This in turn depends on the lin-earized equivalent resistance, , seen through the rectifierinput port. Direct measurement of and during ABTRoperation is not feasible. Therefore, we calculated them indi-rectly from other measurable parameters in the setup shown inFigs. 1 and 2. A straight forward set of measurable values couldbe the voltages across and , which are named and ,respectively, when other variable parameters such as , , and

are held constant. Obviously, needs to be

measured differentially in order not to disturb the transponderisolation from the reader.

To find the relationship between and ,we have further simplified the schematic diagram of Fig. 2 to theequivalent circuit model in Fig. 8. Here is how is defined

(1)

(2)

(3)

where is the load -factor and is the unloaded -factorof . It is also possible to find the voltage transfer functionacross the inductive link, , whichderivation is given in the appendix, assuming [24]

(4)If we calculate from measured or simulated , thenthe above equation can be solved for to give

(5)

We combined the realistic off-chip component and parasiticvalues from the test setup described in Section III with post-layout extracted ABTR model in SPICE to simulate at

and MHz. Table II summarizes the andvariations in different modes of ABTR operation.

It can be seen that changes in a wide range andassumption holds true with k in the Rectifier and OCmodes, where (4) and (5) will be valid, but not the SC mode.With this setup, we have also simulated and when theESD protection circuits are not present and there are no unde-sired leakage currents to in the OC mode (in a high voltage



Fig. 8. Simplified and linearized equivalent circuit description for the inductivewireless link shown in Fig. 2.

TABLE II� AND � VARIATIONS IN VARIOUS MODES OF RECTIFIER OPERATION

FOR � � ��

process for example). It can be seen that in this case is in-creased and extended with respect to the Rectifier modeeven further. This would results in easier back telemetry data de-modulation and extended reading range. It should also be notedthat with heavier loading, i.e., lower , tends to decreasein the Rectifier mode, while it stays the same in the OC mode,thereby increasing .

for the SC or the Rectifier modes with small cannotbe computed using (4) and (5) since . In this case Fig. 8should be analyzed or simulated without the simplifications dis-cussed in the Appendix. According to the simulations using thetypical model in the AMI 0.5- m CMOS process, the effectiveresistance of across is 3 for a gate voltage of3 V. Hence, the resulting is 0.03 for this mode of opera-tion, which results in a larger if k compared tothe OC mode.

B. Reflected Impedance in Back Telemetry

The reflected impedance on to the primary side, , is the keyparameter in back telemetry and a function of the impedance atthe secondary, in Fig. 8. It is given by

(6)

(7)

(8)

Using (1), in (7) can be converted to a more useful form

(9)Fig. 9 shows how the imaginary and real parts of change

as varies from short to 1 k in our setup at MHz.Fig. 9 also shows how and change with . It can beobserved that when , which correspondsto , the imaginary part of will be negligibleat resonance. In this region, which includes the Rectifier and

Fig. 9. Imaginary, real, and magnitude of the transponder impedance, � , andits loaded quality factor, � , versus the linearized resistance seen throughABTR input port � in Fig. 8.

Fig. 10. Reflected impedance �� at the primary shown in the complex planeas a function of equivalent loading at the secondary �� , with � as-cending from left to right in the range � �� k� [5].

OC modes of operation according to Table II, an increase in(e.g., when switching from Rectifier to OC) results in a

reduction in , an increase in , and a reduction in . This isevident in Fig. 6 waveforms. On the other hand, when(e.g., switching from Rectifier to SC), is highly inductive andlargely contributed by the inductance of . Similarly, willbe highly reactive and therefore, results in both amplitude andphase modulation on the primary side.

It can also be inferred from Fig. 9 that for very small valuesof there is a complete dominance of and any changesin would produce little change in . The real part ofpeaks at , which corresponds to . There-fore, for heavily loaded transponders that result in

, the existence of the OC mode in the proposed ABTRseems to be an effective way in extending the reading range.

It is also instructive to look at the locus curve of the reflectedimpedance in different ABTR modes of operation, which areshown in Fig. 10 for our experimental setup. Reducing



Fig. 11. Pie-chart showing the simulation results of the ABTR distribution ofinput power in the Rectifier mode at maximum efficiency (90.4%) and nominalloading of � � � k�. � � � V, � � �� MHz, and � � � �F.

TABLE IIIACTIVE BACK TELEMETRY RECTIFIER SPECIFICATIONS

reduces the resistive component of (moving from right toleft), resulting in load modulation [5].

C. Power Distribution in Rectifier Mode

A post-layout simulation of the ABTR circuit in Fig. 2 wasperformed to analyze the power distribution in various powerdissipating elements in the Rectifier mode when it provides themaximum PCE based on Section III measurements ( V,

MHz, F, and k ). Fig. 11 showsthe result of this simulation in a pie-chart. The rectifier PCE,obtained by dividing the power delivered to the load by the totalinput power, was 90.4%, which is 5.6% higher than the mea-sured value in Fig. 4. We believe that this discrepancy was re-sulted from the additional parasitic components, which were notincluded in the rectifier model, especially those from intercon-nects and measurement instrumentation. In a real application,such as in Interestim-2B [2], since the rectifier block is going tobe part of a system-on-a-chip (SoC), its efficiency is likely to becloser to the higher simulated value.

The static dissipation in drivercircuitry ( comparators) and bias generator is the quiescentcurrent supplied from (see Table III). The dynamic powerdissipation in the rectifier is cal-culated by subtracting the static power from the total dissipa-tion in the driver circuitry when operating the rectifier. This is

Fig. 12. Simulated rectifier PCE and output dc voltage versus � when idealcomparators �� are used in the ABTR of Fig. 2 (compare with Fig. (5b).Operating conditions: � �� V, � � �� MHz, � � � �F.

consumed mainly in the buffers employed after the comparatorblocks to drive large switches (see Fig. 2). The dissipa-tion in the main rectifying elements and ON-resistance(P_SWITCHES) is 7.4%, i.e., the bottleneck to a highest achiev-able PCE. This is despite operating these switches in deep trioderegion. Even though it is possible to reduce P_SWITCHES byincreasing the size of the rectifying elements, it comes at the ex-pense of silicon area and increased parasitic capacitance of theseswitches. Hence, there needs to be a compromise between therectifier size, comparator drive capability, and carrier frequency,which is out of the scope of this paper. A detailed theoreticalanalysis and optimization of the active integrated CMOS recti-fiers can be found in [25].

D. Limits to Rectifier Output Voltage

As mentioned in Section II, we have introduced a phase-leadwhen is being switched OFF to account for the comparatordelay and eliminate reverse currents [15], [19]. On the otherhand, the loss-less capacitive divider also introduces a phase-lagwhen is being switched ON. The comparator delay also addsto this lag and results in a notable reduction in the switching dutycycle. In the present design, for example, the input capacitive di-vider has a ratio of 0.93, which corresponds to a 350 mV dropoutvoltage at 5-V input. Thus, a lower dropout can be achieved inthis architecture by employing a faster comparator and reducingthe phase-lead accordingly.

E. Limits to Rectifier Efficiency

In active rectifiers the comparator characteristics such asdelay, power consumption, and output drive capability have asignificant effect on the maximum achievable efficiency. Toobserve the effect of comparator delay on efficiency, we ransimulations on the ABTR post-layout extraction in the sameconditions as in Section IV-C, while replacing with idealcomparators that had zero delay, unlimited drive capability, andno power dissipation. was swept in Fig. 12 from 10 to100 k similar to the measured results described in Fig. 5. Thesame trend can be observed with the PCE reaching 96.2% for

10 k . This shows that there is only 3.8% powerdissipation in the rectifying elements, which is almost half of



the amount shown in Fig. 11 with realistic comparators thathave 33 ns delay.

The reduced power dissipation in the rectifying elements canbe attributed to the increased rectifier switching duty cycle, ,as a result of eliminating the phase-lead capacitive voltage di-vider ( and in Fig. 2). This in turn reduces theaverage current passing through and to replenish thecharge in that is delivered to in every carrier cycle.also depends on the and affects the ripple.Hence, the RC load can also affect the amount of power that isdissipated in the switching elements as can be seen in Fig. 12.

V. CONCLUSION

An integrated active full-wave rectifier with dual-mode backtelemetry has been implemented in a 0.5- m 5-V standardCMOS process and successfully tested. Being able to bothshort- and open-circuit the transponder LC tank, results inchanging the secondary loaded -factor in a wide range, andpotentially improves the system reading range. It can alsoimprove the back telemetry data bandwidth in inductivelypowered devices such as biomedical implants and RFID tagsby adding more symbols. The rectifier employs dynamicbody voltage regulation, synchronous gate control, and activeswitches to minimize the dropout voltage across the rectifyingelements and increase the ac–dc PCE. Wide-range high speedhysteresis comparators are used with phase-lead to block thereverse current from load to LC-tank, and improve the rectifierefficiency. Most of the rectifier internal power is dissipated inthe ON resistance of the switching elements. Faster comparatorscan potentially reduce the dropout voltage and improve theABTR efficiency. Table III summarizes some of the ABTRspecifications.

APPENDIX

In this section, we have derived the voltage transfer func-tion across the inductive link, , in Fig. 9 which was used inSection IV. We can write the KVL equations for the currents in

and , shown as and , respectively

(10)

(11)

where is the reflected impedance on to the primary [24]

(12)

(13)

The secondary coil voltage is related to its current by

(14)

Assuming and that the primary and secondary tanksare often tuned at the carrier frequency, we can substitute (8) in(14) and reach at

(15)

Using this in (10) and (11) leads to

(16)

(17)

Using (14)–(17), we can write the voltage transfer function as

(18)

(19)

Taking the magnitude of the above equation

(20)Substituting (8) and rearranging (20),

(21)Since , (21) can be simplified further to give

(22)

ACKNOWLEDGMENT

The authors would like to thank U.-M. Jow from GT-BionicsLab for helping with the test setup. They also appreciate thefree fabrication opportunity provided to them by the MOSISeducational program (MEP).

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[18] G. Lazzi, “Thermal effects of bioimplants,” IEEE Eng. Med. Biol.Mag., vol. 24, no. 5, pp. 75–81, Sep. 2005.

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Gaurav Bawa (S’07) was born in Punjab, India, in1981. He received the B.Tech. degree in electricalengineering from the Indian Institute of Technology,Delhi, India, in 2003. He is currently workingtowards the M.S. degree in electrical engineering atNorth Carolina State University, Raleigh.

In the summer of 2002, he was an Intern in the Mi-croelectronics Group at University of Udine, Italy,and in fall 2003, at National Instruments, India, inthe Motion Control Group. From 2003 to 2006, heworked as a Design Engineer at ST Microelectronics,

India. During this period, he was involved in the design and validation of FlashMemory test vehicles in submicron NVM technology, for which he receivedcorporate recognition, and subsequently in the design of analog-to-digital con-verters for the product division. His current research interests include low-powerRF, analog and digital circuit design for biomedical applications.

Mr. Bawa is a member of Phi Kappa Phi and Tau Beta Pi.

Maysam Ghovanloo (S’00–M’04) was born in1973. He received the B.S. degree in electricalengineering from the University of Tehran, Tehran,Iran, in 1994, the M.S. (hons.) degree in biomedicalengineering from the Amirkabir University ofTechnology, Tehran, Iran, in 1997, and the M.S. andPh.D. degrees in electrical engineering from the Uni-versity of Michigan, Ann Arbor, in 2003 and 2004,respectively. His Ph.D. research was on developinga wireless microsystem for Micromachined neuralstimulating microprobes.

From 1994 to 1998, he worked part-time at IDEA Inc., Tehran, Iran, where heparticipated in the developing a modular patient care monitoring system. In De-cember 1998, he founded Sabz-Negar Rayaneh Co. Ltd., Tehran, Iran, to man-ufacture physiology and pharmacology research laboratory instruments. In thesummer of 2002, he was with the Advanced Bionics Inc., Sylmar, CA, workingon the design of spinal-cord stimulators. From 2004 to 2007, he was an As-sistant Professor at the Department of Electrical and Computer Engineering,North Carolina State University, Raleigh, where he founded and directed theNC Bionics Laboratory. In June 2007, he joined the faculty of Georgia Instituteof Technology, Atlanta, where he is currently an Assistant Professor in the De-partment of Electrical and Computer Engineering.

Dr. Ghovanloo is an Associate Editor for the IEEE TRANSACTIONS ON

CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS. He has been a member of thetechnical program committee for the IEEE Midwest Circuits and Systems(MWSCAS), International Symposium on Circuits and Systems (ISCAS), andBiomedical Circuits and Systems (BioCAS) conferences. He has receivedawards in the operational category of the 40th and 41st DAC/ISSCC studentdesign contest in 2003 and 2004, respectively. He has served as a TechnicalReviewer for major IEEE and IoP journals in the areas of circuits, systems,and biomedical engineering. He is a member of Tau Beta Pi, Sigma Xi, andIEEE Solid-State Circuits, IEEE Circuits and Systems, and IEEE Engineeringin Medicine and Biology Societies.


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