Active inrush current limiter based on SCRs for 3.6kW bridgeless totem pole PFC

• ST AC-DC inrush current limiter solutions

• PFC totem pole topology using SiC MOSFETs and thyristors

• Evaluation board performance

• Takeaways

Agenda

2

ST AC-DC inrush current limiter solutions

3

RLIM

S1

S2

• Programmable soft power up control

• Controlled multiple peak current

limitation

• Zero-current Switch

• No Contact Bounce: no spark, no EMI

• Faster line-drop recovery

• Increase switching life expectancy

Low profile design, smaller height thanks

to D²PAK package

SM

AR

TS

AF

ET

YC

OM

PA

CT

IHT008V1 ISF003V1

power500W 7kW2kW

SCR001V1

Latest topology trends

STEVAL-SCR001V1

TN5015H-6G

TN2010H-6G

DPSTPFC1

MCU

+

SCR

TRIAC

+

MCU SCR

+

SCR

Bridgeless PFC

• ST AC-DC inrush current limiter solutions

• PFC totem pole topology using SiC MOSFETs and thyristors

• Evaluation board performance

• Takeaways

Agenda

4

PFC totem pole topology (1/5)Traditional PFC totem pole

5

• A conventional PFC circuit:

• Consists of a full bridge rectifier and a boost pre-regulator

• A large portion of system losses are in the diode bridge

D1 D2

D4D3

L

SC

vIN(t)

iIN (t) Inrushcurrentlimiter

D1

S4

L1

S3

GND

D2

C

IIN

VIN

S2

S1

Inrush

current

limiter

SiC MOSFETs(High Frequency)

Diodes or

MOSFETs(Low Frequency)

• In a traditional totem pole PFC:

• The diode losses are eliminated

• Low frequency switches are diodes or MOSFETs

• Needs an Inrush current limiter (NTC + relays)

PFC totem pole topology (2/5)Operation

6

𝐝𝐢𝐀𝐂𝐝𝐭

> 𝟎𝐝𝐢𝐀𝐂𝐝𝐭

< 𝟎

VAC > 0

VAC < 0

L

A

O

D

S2

VAC IACVDC

D1

D2

S1

L

A

O

D

S2

VAC IACVDC

D1

D2

S1

L

A

O

D

S2

VAC IAC

VDC

D1

D2

S1

L

A

O

D

S2

VAC IACVDC

D1

D2

S1

𝐝𝐢𝐀𝐂𝐝𝐭

< 𝟎𝐝𝐢𝐀𝐂𝐝𝐭

> 𝟎

• D1 /D2 diodes (can be replaced by MOSFETs) works at AC line frequency

• Needs an Inrush current limiter (NTC and Relay)SCRs solution

PFC totem pole topology (3/5)SCRs phase control

7

SCR1

VACHVDC

SCR2

T T T

T_OFF_1 T_OFF_2 T_OFF_3

T T TT

T_OFF_Max

2x∆t 3x∆t 4x∆t∆t 5x∆t

T_OFF_Min

• Bulk capacitor is charged according to time-depending pulse train driving SCR1

and SCR2

• SCR1 and SCR2 are synchronized according to the zero crossing (ZVS) of the

AC line

• SCR1 and SCR2 are alternatively controlled according to the AC line polarity by

reducing the turn-on delay (“T_OFF”) by a constant ∆t at each half AC line cycle

• SCR1 and SCR2 are controlled by phase angle up to the turn-on delay

(“T_OFF”) is lower than “T_OFF_Min”

• Control the inrush-current to charge a DC bus capacitor

• Disconnect the DC bus capacitor from the AC mains when it does not have to operate

LAOD

S2

VAC

IACSCR1

SCR2

S1

HVDC

As low frequency switching, only the conduction losses are

considered

Pd_MOSFET =RDS(ON)ILINE(RMS)

2

2Pd_SCR =VTOILINE(RMS) 2

π+ Rd

ILINE(RMS)2

2

RDS(ON) =2 2VTO

πILINE(RMS)+ Rd

Equilibrium for Pd_SCR = Pd_MOSFET:

SCR MOSFET

Note: losses are calculated for single half-wave conduction (so for each device).

Multiply by 2 to calculated the total losses (for the 2 SCR or the 2 MOS).

PFC totem pole topology (4/5)MOSFET vs SCR comparison

8√2 x ILINE(RMS)

ISCR

orIMOSFET

PFC totem pole topology (5/5)MOSFET vs SCR comparison

9

• SCR have the same efficiency as MOSFET

but with a silicon area more optimized

• With the traditional NTC / Relay solution,

the contact resistance relay is needed to be

into account

• SCRs surge current capabilities makes the

SCR the ideal candidate for bridge

applications where the devices can be

submitted to voltage surges

• ST AC-DC inrush current limiter solutions

• PFC totem pole topology using SiC MOSFETs and Thyristors

• Evaluation board performance

• Takeaways

Agenda

10

Evaluation board performanceDesign content

11

Reference Name Description

STEVAL-DPSTPFC0 AC - DC power boardBridgeless Totem Pole boost with auxiliary

supply

STEVAL-DPS334M1 PFC control board 32-bit MCU control board

STEVAL-DPSADP01 Adapter BoardInterface for MCU debugging and USART

communication

Evaluation board performanceFirmware overview

12

• Control loop:

• Average current-mode control method I

• Continuous and discontinuous conduction mode

• Outer voltage loop performed at 72 kHz

• Outer voltage loop performed at 2 times of AC line

frequency

• DFF is used to pre-calculate a duty ratio and to

improve the transient response

• Digital average current mode control in CCM and

DCM including:

• Bus voltage and AC line currents sampling

• Voltage error calculation

• Voltage PI regulation

• Reference current calculation

• Current error calculation

• Duty cycle feed-forward generation

• Final duty cycle computation

ICL on

INIT

PFC Totem Pole

demoboard supplied

STANDBY

MODE

PFC RUN

ICL RUNFAULT

ICL off DC Capacitor ChargedFault

detection

Faultrecovery

Faultdetection

Faultdetection

No Faultdetection

Drop AC line voltage

PFC SOFT

START

HVDC target reachedFault

detection

Evaluation board performancePFC totem pole start-up

13

To ensure a smooth PFC start-up a soft start routines has

been implemented on the MCU firmware:

1) Inrush current limiter: SCRs are controlled with a

progressive phase control and the output capacitor can be

smoothly up to the AC line peak voltage.

2) PFC soft start: The output voltage reference is controlled

from AC line peak voltage to 400 Vdc with a smoothly

voltage ramp.

HVDCVAC

IAC

Inrush current limiter Steady StatePFC soft startPFC OFF

LAOD

S2

VAC

IACSCR1

SCR2

S1

HVDC

Evaluation board performancePFC efficiency / THD measurement

14

VAC = 230 VRMS @ 50 Hz

0

2

4

6

8

10

12

14

16

18

90

91

92

93

94

95

96

97

98

99

500 1000 1500 2000 2500 3000 3500

THD

(%

)

Effi

ien

y (%

)

POUT (W)

Evaluation board performanceSiC MOSFET control

15

• SiC MOSFETs are operating in synchronous conduction mode to improve efficiency

• Current spike is generated at each AC line zero cross

HVDC (100 V/div)

MOS1 (2 V/div)

MOS2 (2 V/div)

IL (2 A/div)

VAC

IAC

Without Soft ZVS SiC MOSFET control

• Duty ratio of switch changes abruptly from zero to almost 100% after each AC line zero cross

• High voltage is applied to the inductor (HVDC). A high positive current spike is generated

• Same phenomenon with diode or MOSFET

LAOD

S2

VAC

IACSCR1

SCR2

S1

HVDC

Evaluation board performanceSiC MOSFET control

16

S1_CNTRL

S2_CNTRL

VAC

IAC

• SiC MOSFETs are controlled with a smart Duty Cycle control at each AC line zero cross

• To reduce peak current through boost inductor at the AC line zero crossing

• To improve common mode noise

LA

OD

S2

VAC

IACSCR1

SCR2

S1

HVDC

Evaluation board performance Common mode noise measurement (load = 800 W / 230 VRMS / 50 Hz)

17

5

25

45

65

85

105

0,15 1,5 15

dB

uV

Freq (MHz)

QP Limite EN55022

Average limit EN55022

Peak Measure

Average Measure

5

15

25

35

45

55

65

0,15 1,5 15

dB

uV

Freq (MHz)

QP Limite EN55022

Average limit EN55022

Peak Measure

Average Measure

With smart Duty cycle controlWithout smart Duty cycle control

Evaluation board performanceDrop AC line voltage

18

HVDC

VAC

IAC

HVDC

VAC

IAC

AC line voltage interrupt lasts less than 30ms

SCRs and SiC MOSFETS are kept “ON”, criteria A

AC line voltage interrupt lasts more than 30ms

SCRs are controlled back in soft-start when the VAC is reapplied, criteria B

With SCRs, AC line voltage interrupt is managed more effectively than NTC + relays solution

Evaluation board performanceMain figures

19

• Input AC voltage: 85VAC up to 264VAC

• Input AC frequency: 45Hz up to 65Hz

• DC output voltage: 400VDC

• Switching frequency: 72 kHz

• Maximum input curent: 16 A RMS (POUT = 3.6KW)

• A high efficiency: > 97,5%

• A low THD distortion lower than 5 % of maximum

• Compliant to :

• EN 55022 and IEC 61000-4-11 and IEC 61000-3-3

• IEC 61000-4-5 surge: 4kV

• IEC 61000-4-4 EFTY burst : criteria A @ 4kV

• Cooling: forced air cooling with active fan

• Design for operation with DC/DC converter

• Peak inrush current tuning

• Remove two bulky relays and an NTC resistor thanks to SCRs progressive start-up

U

tBurst duration

Burst period300ms

Burst

Vp/2

10%

Vp

50 ns

5 ns

90%

Pulse

U

tBurst duration

Burst period300ms

Burst

0,75ms

U

tBurst duration

Burst period300ms

Burst

Vp/2

10%

Vp

50 ns

5 ns

90%

Pulse

Vp/2

10%

Vp

50 ns

5 ns

90%

Pulse

Vp/2

10% 90%

Vp

50 µs

1.2 µs

• ST AC-DC inrush current limiter solutions

• PFC totem pole topology using SiC MOSFETs and thyristors

• Evaluation board performance

• Takeaways

Agenda

20

• This presentation described a 3,6kW bridgeless totem pole PFC evaluation board for telecom and industrial

applications with an digital Inrush current limiter using SiC MOSFETs and Thyristors.

• The Evaluation board design includes

• A power board bridgeless totem pole boost with an inrush limiter circuit, SiC MOSFET and SCRs switch drivers and an auxiliary power supply

• A control board with its MCU, a PFC/ICL control firmware

• An adapter board for software debug

• Evaluate a full ST solution

• SCRs: To control the inrush-current to charge a DC bus capacitor and to fulfill with the IEC 61000-3-3 standard

• SiC MOSFETs: To reduce passive components size and to provide a PFC with a very high efficiency thanks to low reverse recovery diode body

• STGAP2S driver: Dedicated and optimized to control SiC MOSFETs

• STM32 microcontroller: Embedded the PFC control algorithm

Takeaways

21

DC/DC or motor inverter can

be connected to this

evaluation board

L

A

O

D

S2

VAC

IACSCR1

SCR2

S1

HVDC

• Check the stand-by losses • Reduce drastically the stand-by losses of the traditional NTC/PTC Inrush-current limitation

• Disconnect the DC bus capacitor from the AC mains when it does not have to operate

• Without requiring a relay to be added to open the circuit during stand-by

• Check EMC• Immunity to fast transient and surge voltages

• Common mode noise

• This reference design offering:• A high efficiency: > 97,5%

• A low THD distortion lower than 5 % of maximum load

• A high switching lifetime with reduced EMI emissions

• A robust circuit that meets EMC standards up to 4 kV

• SCR allows achieving a smart inrush current limitation at power up or line drop recovery compare to the traditional NTC and relays solution

Takeaways

22

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