Active Packaging: Active Packaging: Power Management Power Management for Nanoprocessorsfor Nanoprocessors

Raj Nair, Raj Nair, ComLSIComLSI Inc. Inc. Presented to the First AZ Presented to the First AZ

Nanotechnology SymposiumNanotechnology SymposiumMarch 16, 2006March 16, 2006

ProloguePrologue

With a “billion connected pc’s,” With a “billion connected pc’s,” cutting nanoprocessor power by cutting nanoprocessor power by ½½ reduces energy consumption by reduces energy consumption by 50 50 Giga wattsGiga watts!!

Advanced power management is Advanced power management is innovation leading to energy efficiency innovation leading to energy efficiency

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Scaling of DimensionsScaling of Dimensions

Smaller, faster & cheaper…Or so it was!

Power Related Prediction Power Related Prediction in 2001 in 2001

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Processor power doubles every ~36 months…

References:Raj Nair2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’2002 Intel Technology Journal paper “Emerging Directions for Packaging…”

ConsequencesConsequences

Leakage in Nanometer Leakage in Nanometer CMOS…CMOS…

Drain induced barrier lowering in short channel devices make leakage increase with Vds (Vdd)

Sub-threshold channel leakage dominates the Vdd dependent leakage.

Source:S. Narendra & A. ChandrakasanLeakage in Nanometer Technologies, Springer Publications, 2005

Leakage power now equals active power!And both are exponential with Vdd…

Supply Voltage Is KeySupply Voltage Is Key

Lower supply voltage = much lower powerLower supply voltage = much lower powerActive power is quadratically related ( Active power is quadratically related ( V V22))

Leakage power is similarly dependent upon VLeakage power is similarly dependent upon Vnn, n > , n > 22

For a Nanoprocessor (or SoC), this is For a Nanoprocessor (or SoC), this is multiple supplies on chip & independent multiple supplies on chip & independent dynamic controldynamic control

And fine, high-bandwidth control of noise…And fine, high-bandwidth control of noise…

Active Noise RegulatorsActive Noise Regulators

Active Noise Regulators (ANR’s) Active Noise Regulators (ANR’s) sense/regulate noise in a nanoprocessors’s sense/regulate noise in a nanoprocessors’s voltage islands voltage islands

ANR’s enhance (not replace) nanoprocessor ANR’s enhance (not replace) nanoprocessor power delivery infrastructurepower delivery infrastructure

Reference:Raj Nair & Donald BennettPower Management Designline article http://www.powermanagementdesignline.com/howto/175800373

Active Noise RegulationActive Noise Regulation

Chip power grid noise

ANR attached to top left corner of grid

Prediction & ValidationPrediction & Validation 2001 iATTJ [1]2001 iATTJ [1] “The Silicon Sandwich integrates all the “The Silicon Sandwich integrates all the

components for power conversion into a multi–component components for power conversion into a multi–component active interposer that is bonded to the CPU and ‘sandwiched’ active interposer that is bonded to the CPU and ‘sandwiched’ between two heat sinks. The name derives from the structure between two heat sinks. The name derives from the structure and the many technologies integrated.” and the many technologies integrated.”

$ 2006 EETimes [3]2006 EETimes [3] “A second ISSCC paper discusses a “A second ISSCC paper discusses a prototype method for supporting multiple power supply rails on prototype method for supporting multiple power supply rails on chip by using a new all-CMOS, fast voltage regulator. … The chip by using a new all-CMOS, fast voltage regulator. … The technique would be especially useful for running different technique would be especially useful for running different cores at different supply voltages on multicore CPUs, Rattner cores at different supply voltages on multicore CPUs, Rattner said. "This is a very important technology for which we have said. "This is a very important technology for which we have high hopes," he added. … Bringing the new thin films into high high hopes," he added. … Bringing the new thin films into high volume fabs and getting the inductors on chip are major volume fabs and getting the inductors on chip are major challenges toward commercializing the technology over the challenges toward commercializing the technology over the next three to four years, he added.”next three to four years, he added.”

References:[1], [2] Raj Nair, [3] EETimes article2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ / US pat. pub.20030081389 February 06, 2006 EETimes Intel CTO calls for better chip-design tools to beat process variance

ComLSIComLSI

Products / Service offeringProducts / Service offeringPowerESLPowerESL: Tools and expertise for IC power : Tools and expertise for IC power integrityintegrity

Analog / Mixed-Signal Analog / Mixed-Signal IPIP in development for DVI / in development for DVI / HDMI / Power Management applicationsHDMI / Power Management applications

Analog / Custom design servicesAnalog / Custom design services

Patents: 5 pending in ANR / AVP Patents: 5 pending in ANR / AVP technologytechnology

40+ authored, 34 issued40+ authored, 34 issued

Team: 50+ years of technology mgmnt. & Team: 50+ years of technology mgmnt. & mktg. mktg. Contact: Raj Nair, President, raj@comlsi.com

www.comlsi.com (480) 694-5984