ad-clink-conv - alpha data user manual.pdf · ad-clink-conv (v1.1 - 27th march 2012) 1 introduction...

AD-CLINK-CONVRevision: 1.1

Date: 27th March 2012

AD-CLINK-CONV(v1.1 - 27th March 2012)

©2012 Copyright Alpha Data Parallel Systems Ltd.All rights reserved.

This publication is protected by Copyright Law, with all rights reserved. Nopart of this publication may be reproduced, in any shape or form, without

prior written consent from Alpha Data Parallel Systems Limited.

Head Office US Office

Address 4 West Silvermills Lane,Edinburgh, EH3 5BD, UK

3507 Ringsby Court Suite 105 Denver, CO 80216

Telephone +44 131 558 2600 (303) 954 8768Fax +44 131 558 2700 (866) 820 9956 - toll freeemail [email protected] [email protected] http://www.alpha-data.com http://www.alpha-data.com


Table Of Contents1 Introduction ......................................................................................................................................................... 1 1.1 Key Features .................................................................................................................................................... 12 Functional Description ....................................................................................................................................... 2 2.1 Overview .......................................................................................................................................................... 2 2.2 Virtex 6 FPGA .................................................................................................................................................. 2 2.2.1 Part Number .............................................................................................................................................. 2 2.2.2 IO/MGT Bank Allocation............................................................................................................................ 2 2.3 Switch Definitions ............................................................................................................................................. 2 2.4 LED Definitions................................................................................................................................................. 3 2.5 JTAG Connection ............................................................................................................................................. 3 2.6 Clocks............................................................................................................................................................... 4 2.7 Non-Volatile Memory........................................................................................................................................ 4 2.8 DDR3-SDRAM ................................................................................................................................................. 4 2.9 Power ............................................................................................................................................................... 4 2.10 Spare LVDS.................................................................................................................................................... 43 Mechanical Assembly ......................................................................................................................................... 5A Connector Layout ............................................................................................................................................... 7B CameraLink Pin Assignment (J1, J2) ................................................................................................................ 8C Micro-D 15 Serial Connector (J4)....................................................................................................................... 9D Auxilary Connectors (CN1/CN2) ........................................................................................................................ 10E SNAP12 Optical Modules (U1, U2)..................................................................................................................... 11F Configuration (Switches, LEDs, Clocks)........................................................................................................... 12

TablesTable 1: IO/MGT Banks ....................................................................................................................................... 2Table 2: LED Definitions ...................................................................................................................................... 3Table 3: LED Definitions ...................................................................................................................................... 3Table B1: J1 ........................................................................................................................................................... 8Table B2: J2 ........................................................................................................................................................... 8Table C1: J1 ........................................................................................................................................................... 9Table C2: LTC2854 to FPGA Pin Mappings........................................................................................................... 9Table E1: U1, AFBR-775 (TX)................................................................................................................................ 11Table E2: U1, AFBR-785 (RX) ............................................................................................................................... 11Table F1: Switch Inputs ......................................................................................................................................... 12Table F2: LED Outputs .......................................................................................................................................... 12Table F3: Clocks .................................................................................................................................................... 12


FiguresFigure 1: AD-CLINK-CONV Block Diagram .......................................................................................................... 1Figure 2: AD-CLINK-CONV Block Diagram .......................................................................................................... 2Figure 3: AD-CLINK-CONV Block Diagram .......................................................................................................... 3Figure A1: AD-CLINK-CONV Block Diagram .......................................................................................................... 7


1 IntroductionThe AD-CLINK-CONV is a compact assembly with a single PCB containing a Virtex 6 FPGA. This module is designedto either emulate a CameraLink Interface for test purposes or convert two CameraLink connections to high speedoptical signals which are output on fiber SNAP 12 compatible modules. The module operates as a stand alone devicewith a single 5V power supply.

1.1 Key FeaturesKey Features

2 CameraLink/HiSPi SDR connectors for Base, Medium, and Full Cameralink interfaces•Capable of CameraLink emulation with Alpha Data CamerLink SDK•2 optical SNAP 12 transmitter/receiver modules for high-speed long distance optical communication.•Alpha Data CameraLink SDK provides designers with a powerful starting point for CameraLink designs.•Spare internal Samtec connector for access to additional LVDS pairs on the FPGA.•5mm industry standard power jack providing 5V powers entire system.•4 serial connections, 2 of RS232 and 2 of RS422 available for camera control.•512MB of DDR3 SDRAM•

Figure 1: AD-CLINK-CONV Block Diagram

Page 1IntroductionAD-UG-1236 Alpha Data Parallel Systems Ltd.


2 Functional Description2.1 Overview

ADC-CLINK-CONV

SDRConnector

SDRConnector

FGPA

V6LX75T,V6LX130T,V6LX195T,

or V6LX240TFF/FFG784

PWRConversion

5V to 3.3V, 2.5V, 1.8V1.5V, 1.2V, 1.0V

SNAP 12RX

SNAP 12TX

ClockingFLASHJTAG

SamtecConnector

PWRConnector

x12

x12

2x RS422

2x RS232

SamtecConnector

DRAM


2.2 Virtex 6 FPGA2.2.1 Part Number

This design can utilizes the following FPGA part numbers: XC6VLX75T-1FFG784C, XC6VLX75T-1FFG784C,XC6VLX130T-1FFG784C, XC6VLX195T-1FFG784C, or XC6VLX240T-1FFG784C.

2.2.2 IO/MGT Bank AllocationSee Appendix for pin assignments.

IO/MGT Banks Voltage Purpose0, 24 2.5V Configuration, JTAG

25, 26 2.5V CameraLink, Serial Protocol14, 15, 16 2.5V Spare Samtec Connectors24, 35, 36 1.5V Reserved for Future Use

114, 115, 116 1.2V High-Speed MGT for Optical Interface

Table 1: IO/MGT Banks

2.3 Switch DefinitionsThere is a single 8 position Dip switch. All signals are user defined and fed directly into the FPGA. The "ON" positionwill result in a logical 0, while the "OFF" position will result in a logical 1. Please refer to Appendix for pin assignments.

Page 2 Functional DescriptionAD-UG-1236Alpha Data Parallel Systems Ltd.


2.4 LED DefinitionsFive LEDs display power, configuration, and user status according to the following table. A logical 1 lights user definedLEDs, see Appendix for pin assignments.

LED SignalD1 Power OK StatusD3 User DefinedD4 User DefinedD5 User DefinedD6 FPGA Configured

Table 2: LED Definitions


2.5 JTAG ConnectionThe target FPGA and onboard configuration flash memory are configured through the Xilinx JTAG interface.

The on-board JTAG scan chain uses 2.5V. The Vcc supply provided on J5 to the JTAG cable is +2.5V and is protectedby a poly fuse rated at 350mA. 3.3V signals must not be used at header J5.

The JTAG header (J5) lines up with the flying leads of the Xilinx JTAG cable. Connect the Cable as follows, with Pin 1on the SDR CameraLink connector side of the box:

Page 3Functional DescriptionAD-UG-1236 Alpha Data Parallel Systems Ltd.


Pin Signal1 TMS2 NC3 TDI4 TDO5 NC6 TCK7 NC (FBS)8 GND9 VREF

Table 3: LED Definitions

2.6 ClocksA 200MHz LVDS oscillator is connected to the FPGA Global clock inputs.

A 156.25MHz LVDS oscillator is connected to the FPGA MGT REFCLK0 pins in MGT bank 115 for use with theSNAP12 link.

2.7 Non-Volatile MemoryA flash memory from the Xilinx XCF series is utilized to configure the FPGA on power up. This memory is 32Mbit in sizeand configurable over the JTAG chain.

2.8 DDR3-SDRAMA single bank of DDR3-800 SDRAM is included within the module. The size of this memory bank is 512MB. Thismemmory is accessed using the Xilinx Memory Interface Generator (MIG).

2.9 PowerAn external power supply is provided with the module that will provide all necessary power. The power draw is highlydependent on user configuration and will not exceed 20W. Contact Alpha Data with questions regarding more accurateestimation of power usage.

WARNING: The power supply is negative polarity, do not connect with a positive polarity supply or the board could bedamaged.

2.10 Spare LVDSA spare samtec QTH connector is available for accessing spare LVDS/GPIO connections to the FPGA. The connectionwas designed to fit with cables designed using a right angle TE connectivity Blue Ribbon Coax Assemblies: http://www.precisionint.com/highspeeddata/blueribbon/

Page 4 Functional DescriptionAD-UG-1236Alpha Data Parallel Systems Ltd.


3 Mechanical AssemblyIt is essential to open the case in order to access the JTAG connector and configure the FPGA. Follow the instructionbelow to open the case correctly.

Key Features

Remove the four screws on the front panel (the panel with the power jack and SDR connectors)1.Remove the front panel2.Remove the top two screws on the back panel3.Slide off the top cover with the fan4.With the top open the user switches can be switched and the JTAG cable connected or removed.5.Before applying power to the unit, slide the top cover back on so the fan cool the board adequately. The JTAGcable can fit through the slit on front panel.

6.

Page 5Mechanical AssemblyAD-UG-1236 Alpha Data Parallel Systems Ltd.


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Page 6 Mechanical AssemblyAD-UG-1236Alpha Data Parallel Systems Ltd.


Appendix A: Connector Layout


Page 7Connector LayoutAD-UG-1236 Alpha Data Parallel Systems Ltd.


Appendix B: CameraLink Pin Assignment (J1, J2)

Connector Pin FPGA Pin Signal Name Connector Pin FPGA Pin Signal Name1 N/A GND 14 N/A GND2 G19 CC4_N 15 H19 CC4_P3 A20 CC3_P 16 A19 CC3_N4 F19 CC2_N 17 E18 CC2_P5 D17 CC1_P 18 E17 CC1_N6 B18 SER_RX_A_P 19 B19 SER_RX_A_N7 H18 SER_TX_A_N 20 G18 SER_TX_A_P8 C18 X3_P 21 D18 X3_N9 D20 X_CLK_P 12 E19 X_CLK_N10 J17 X2_P 23 J18 X2_N11 G17 X1_P 24 F17 X1_N12 K17 X0_P 25 K18 X0_N13 N/A GND 26 N/A GND

Table B1: J1

Connector Pin FPGA Pin Signal Name Connector Pin FPGA Pin Signal Name1 N/A GND 14 N/A GND2 J15 Z3_P 15 K15 Z3_N3 F16 Z_CLK_P 16 F15 ZCLK_N4 C14 Z2_P 17 B13 Z2_N5 D13 Z1_P 18 D12 Z1_N6 B11 Z0_P 19 C11 Z0_N7 J16 SER_TX_B_N 20 H15 SER_TX_B_P8 G14 Y3_P 21 F14 Y3_N9 B14 Y_CLK_P 12 A14 Y_CLK_N10 H16 Y2_P 23 G16 Y2_N11 E13 Y1_P 24 E14 Y1_N12 E12 Y0_P 25 D11 Y0_N13 N/A GND 26 N/A GND

Table B2: J2

Page 8 CameraLink Pin Assignment (J1, J2)AD-UG-1236Alpha Data Parallel Systems Ltd.


Appendix C: Micro-D 15 Serial Connector (J4)

The four RS422 Controllers are user configurable. Transceiver part number LTC2854 is used to accomplish this. Pleasereference the LTC2854 datasheet for operation.

Connector Pin FPGA Pin Signal Name1 E20 RS232_TX12 D21 RS232_RX13 N/A GND4 B22 RS232_TX25 B23 RS232_RX26 N/A GND7 Variable RS422_1_P8 Variable RS422_1_N9 Variable RS422_2_P10 Variable RS422_2_N11 N/A GND12 Variable RS422_3_P13 Variable RS422_3_N14 Variable RS422_4_P15 Variable RS422_4_N

Table C1: J1

RS422Controller DI RO RE DE TE

1 A11 E15 B12 D16 H202 A12 D15 C13 C16 G213 C15 A15 H14 A17 F204 B16 A16 G13 B17 F21

Table C2: LTC2854 to FPGA Pin Mappings

Page 9Micro-D 15 Serial Connector (J4)AD-UG-1236 Alpha Data Parallel Systems Ltd.


Appendix D: Auxilary Connectors (CN1/CN2)

Please contact alpha data for the pin assignments for the auxilary connectors.

Page 10 Auxilary Connectors (CN1/CN2)AD-UG-1236Alpha Data Parallel Systems Ltd.


Appendix E: SNAP12 Optical Modules (U1, U2)

Module Pin FPGA Pin Signal Name Module Pin FPGA Pin Signal NameD2 AF1 MGT_TX_P0_P E2 AF2 MGT_TX_P0_NB3 AD1 MGT_TX_P1_P C3 AD2 MGT_TX_P1_NF3 AB1 MGT_TX_P2_P G3 AB2 MGT_TX_P2_ND4 Y1 MGT_TX_P3_P E4 Y2 MGT_TX_P3_NB5 V1 MGT_TX_P4_P C5 V2 MGT_TX_P4_NG5 T1 MGT_TX_P5_P F5 T2 MGT_TX_P5_NE6 P1 MGT_TX_P6_P D6 P2 MGT_TX_P6_NG7 M1 MGT_TX_P7_P F7 M2 MGT_TX_P7_NC7 K1 MGT_TX_P8_P B7 K2 MGT_TX_P8_NF9 H1 MGT_TX_P9_P G9 H2 MGT_TX_P9_NE8 F1 MGT_TX_P10_P D8 F2 MGT_TX_P10_NC9 D1 MGT_TX_P11_P B9 D2 MGT_TX_P11_N

Table E1: U1, AFBR-775 (TX)

Module Pin FPGA Pin Signal Name Module Pin FPGA Pin Signal NameG9 AH1 MGT_RX_P0_P F9 AH2 MGT_RX_P0_NJ8 AG3 MGT_RX_P1_P H8 AG4 MGT_RX_P1_NE8 AE3 MGT_RX_P2_P D8 AE4 MGT_RX_P2_NG7 AC3 MGT_RX_P3_P F7 AC4 MGT_RX_P3_NJ6 U3 MGT_RX_P4_P H6 U4 MGT_RX_P4_ND6 R3 MGT_RX_P5_P E6 R4 MGT_RX_P5_NF5 N3 MGT_RX_P6_P G5 N4 MGT_RX_P6_ND4 L3 MGT_RX_P7_P E4 L4 MGT_RX_P7_NH4 E3 MGT_RX_P8_P J4 E4 MGT_RX_P8_NE2 C3 MGT_RX_P9_P D2 C4 MGT_RX_P9_NF3 B1 MGT_RX_P10_P G3 B2 MGT_RX_P10_NH2 A3 MGT_RX_P11_P J2 A4 MGT_RX_P11_N

Table E2: U1, AFBR-785 (RX)

Page 11SNAP12 Optical Modules (U1, U2)AD-UG-1236 Alpha Data Parallel Systems Ltd.


Appendix F: Configuration (Switches, LEDs, Clocks)

Switch Position FPGA Pin1 AB232 AC233 AE244 AF245 AG246 AH247 AC248 AB24

Table F1: Switch Inputs

D Number FPGA PinD3 AG26D4 AE25D5 AF25

Table F2: LED Outputs

Clock Signal FPGA Pin200MHz_P AA26200MHz_N AA27

156.25MHz_P T6156.25MHz_N T5

Table F3: Clocks

Page 12 Configuration (Switches, LEDs, Clocks)AD-UG-1236Alpha Data Parallel Systems Ltd.


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Page 13Configuration (Switches, LEDs, Clocks)AD-UG-1236 Alpha Data Parallel Systems Ltd.


Revision History:

Revision Date Description of Change1.0 March 19th 2012 Initial Release

1.1 March 27th 2012 Added comments about CameraLink emulation and additional FPGAdie sizes

©2012 Alpha Data Parallel Systems Ltd. All rights reserved. All other trademarks and registered trademarks are theproperty of their respective owners.

Address: 4 West Silvermills Lane, Edinburgh, EH3 5BD, UKTelephone: +44 131 558 2600Fax: +44 131 558 2700email: [email protected]: http://www.alpha-data.com

Address: 3507 Ringsby Court Suite 105 Denver, CO 80216Telephone: (303) 954 8768Fax: (866) 820 9956 - toll freeemail: [email protected]: http://www.alpha-data.com

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