a/d converter control discussion d8.6 rev. b – 3/14/2006
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![Page 1: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/1.jpg)
A/D ConverterControl
Discussion D8.6
Rev. B – 3/14/2006
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Analog-to-Digital Converters
• Converts analog signals to digital signals– 8-bit: 0 – 255– 10-bit: 0 – 1023– 12-bit: 0 – 4095
• Successive Approximation
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Method of Successive Approximation
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
![Page 4: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/4.jpg)
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
Control
D/A Converter
V
V
in
DA
Binary OutputC+
-
Implementing Successive Approximation
![Page 5: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/5.jpg)
Control
D/A Converter
V
V
in
DA
Binary OutputC+
-
Implementing Successive Approximation
2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
![Page 6: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/6.jpg)
2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
A/D CPLD Control
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
msel
adflg
![Page 7: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/7.jpg)
Use Mealy Machine
Inputs to C1:adstart, gt, done
Outputs from C2:sarald, sh, adld, msel, adflg
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
msel
adflg
![Page 8: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/8.jpg)
2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
A/D Control Unit
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
Why won't this work?
sarReg
adReg
Done
clk
msel
resetsarld maskR
clk
resetsh
clk
resetadld
ADR
mux1
sarin
sarmask
A B
0 1
![Page 9: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/9.jpg)
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
sarReg
adReg
Done
clk
msel
resetsarld maskR
clk
resetsh
clk
resetadld
ADR
mux1
sarin
sar
mask
A B
0 1
Note: sar must be1000 on reset so that gt can be set properly.
Now we don't need the mux or the AND gates!
![Page 10: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/10.jpg)
sarReg
adReg
Done
clk
resetsarld maskR
clk
resetsh
clk
resetadld
ADR
sar
sar
mask
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
sarld sarReg maskR sar gt 0 0000 1000 1000 1 1 1000 0100 1100 0 0 1000 0010 1010 1 1 1010 0001 1011 0 0 1010 0000 1010
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A Mealy state machine
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
![Page 12: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/12.jpg)
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
ADctl
sarReg
adReg
Done
clk
resetsarld maskR
clk
resetsh
clk
resetadld
ADR
sar
sar
mask
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
adflg
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A Mealy state machine
Use one-hot encoding: one flip-flop per state
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
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module DFF (D, clk, clr, Q);
input clk, clr ;wire clk, clr ;input D ;wire D ;
output Q ;reg Q ;
always @(posedge clk or posedge clr)if(clr == 1)
Q <= 0;else
Q <= D;endmodule
CLK
D Q
~Qclk
D Q
clr
DFF
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module DFF1 (D, clk, reset, Q);
input clk, reset;wire clk, reset ;input D ;wire D ;
output Q ;reg Q ;
always @(posedge clk or posedge reset)if(reset == 1)
Q <= 1;else
Q <= D;endmodule
CLK
D Q
~Qclk
D Q
reset
DFF1
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clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
// adconv controlmodule ADctrl(Clk, Clear, gt, adstart, done, sarld, sh, adld, adflg); input Clk, Clear, gt, adstart, done;
output sarld, sh, adld, adflg;wire msel, sarld, sh, adld, adflg;
wire start, keep, remove; wire startD, keepD, removeD;
assign startD = start & ~adstart | keep & done | remove & done;assign keepD = start & adstart & gt | keep & gt & ~done
| remove & gt & ~done;assign removeD = start & adstart & ~gt | keep & ~gt & ~done
| remove & ~gt & ~done;
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
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DFF1 startFF(.D(startD), .clk(Clk), .reset(Clear), .Q(start));DFF keepFF(.D(keepD), .clk(Clk), .clr(Clear), .Q(keep));DFF removeFF(.D(removeD), .clk(Clk), .clr(Clear), .Q(remove));
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)S
tate
Reg
iste
r
C1
C2
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// C2 Outputsassign adflg = done;assign adld = done;assign sarld = gt & keep | gt & remove | gt & adstart & start;assign sh = ~done & keep | ~done & remove | adstart & start;
endmodule
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
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// Title : A/D convertermodule adconv(clock, clear, adstart, gt, adflg, sar, adreg); input clock, clear, adstart, gt; output adflg; output [3:0] sar, adreg; wire adflg, sarld, adld, sh, done; wire [3:0] sar, adreg;
ADpath adc1(.clk(clock),.reset(clear),.sh(sh),.sarld(sarld),.adld(adld),.sar(sar),.ADR(adreg),.done(done));
ADctrladc2(.Clk(clock),.Clear(clear),.gt(gt),.adstart(adstart),.done(done),.sarld(sarld),.sh(sh),.adld(adld), .adflg(adflg));
endmodule
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
adflg
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A Mealy state machine
Use binary encoding: two flip-flops
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
egis
ter
C1
C2
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// adconv controlmodule ADctrl(Clk, Clear, gt, adstart, zero, msel, sarld, sh, adld, adflg); input Clk, Clear, gt, adstart, zero; output sarld, sh, adld, adflg; reg msel, sarld, sh, adld, adflg; reg[2:0] present_state, next_state; parameter start = 2'b00, keep = 2'b01, remove = 2'b11;
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
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always @(posedge Clk or posedge Clear) begin if (Clear == 1) present_state <= start; else present_state <= next_state; end
clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)S
tate
Re
gis
ter
C1
C2
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always @(present_state or adstart or gt or done)begin case(present_state) start: if(adstart == 1)
next_state <= load; else if(gt == 1)
next_state <= keep; else next_state <= remove;
keep: if(done == 1) next_state <= start; else if(gt == 1)
next_state <= keep; else next_state <= remove;
remove: if(done == 1) next_state <= start; else if(gt == 1)
next_state <= keep; else next_state <= remove;
default next_state <= start; endcaseend
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
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clear
clk
Presentstate
Nextstate
Presentinput Present
output
x(t)
s(t)
s(t+1)
z(t)
Sta
te R
eg
iste
r
C1
C2
// C2 Outputsassign adflg = done;assign adld = done;assign sarld = gt & keep | gt & remove | gt & adstart & start;assign sh = ~done & keep | ~done & remove | adstart & start;
endmodule
sarReg
adReg
Done
clk
resetsarld maskR
clk
resetsh
clk
resetadld
ADR
sar
sar
mask
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2R
2R
2R
2R
2R
R
R
R
VB3
B2
B1
B0
ControlUnit Datapath
sarCPLD
Vin
gt
adstart
adflg adreg
Analog in
Digital out
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V
5V
2.5V
3.75V
3.125V3.4375V Vin = 3.5V
step 1 step 2 step 3 step 4
voltage
A/D Control Unit
start
removekeep
~adstart
adstart & ~gt
adstart & gt done
done
~done & ~gt~done & gt
~done & ~gt
~done & gt
sarReg
adReg
Done
clk
resetsarld maskR
clk
resetsh
clk
resetadld
ADR
sar
sar
mask
![Page 26: A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006](https://reader034.vdocument.in/reader034/viewer/2022051619/56649d485503460f94a2324d/html5/thumbnails/26.jpg)
// Title : A/D convertermodule adconv(clock, clear, adstart, gt, adflg, sar, adreg); input clock, clear, adstart, gt; output adflg; output [3:0] sar, adreg; wire adflg, msel, sarld, adld, sh, done; wire [3:0] sar, adreg;
ADpath adc1(.clk(clock),.reset(clear),.sh(sh),.sarld(sarld),.adld(adld),.sar(sar),.ADR(adreg),.done(done));
ADctrl adc2(.Clk(clock),.Clear(clear),.gt(gt),.adstart(adstart),
.done(done),.sarld(sarld),.sh(sh),
.adld(adld), .adflg(adflg));
endmodule
DatapathControl Unit
done
clr clk reset clk
sarld
adreg[3:0]
sar[3:0]
adld
sh
adstart
gt
adflg
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binbcd4 hex7seg AtoG[6:0]
AAtoGG segmentsb,c
LEDR[3:0]
P[3:0]
P[4]
adconvadreg
sar gt
To D/Aconverter
18-bit counter4 MHzclock S2
clk clr
Q[7]15.625 KHzclock
adstart
adflg
Lab 9