a/d converter figures of merit and performance trends

A/D Converter Figures of Merit and Performance Trends

Boris Murmann Stanford University

Definition

2

FIGURE OF MERIT

A numerical quantity based on one or

more characteristics of a system or

device that represents a measure of

efficiency or effectiveness

First Known Use of FIGURE OF MERIT

Circa 1865

A/D Converter Characteristics

3

Resolution Conversion Rate

Power Dissipation

Input Impedance

Supply Rejection

Yield

Common-Mode Rejection

Die Area

Aperture Bandwidth

Metastability Rate

Process Feature Size

Practical ADC FoMs Must Be Simple

4


Power Dissipation

Input Impedance

Supply Rejection

Yield

Common-Mode Rejection

Die Area

Aperture Bandwidth

Metastability Rate

Process Feature Size

FoM

Typical FoM Usage

An FoM is just one entry in larger comparison table that intends to tell the whole story

5

[Miyahara, ISSCC 2014]

FoM Construction

The FoM should reflect the design tradeoffs in a fair and realistic manner

Conversion Rate ↔ Power Dissipation

Resolution ↔ Power Dissipation

6


Power Dissipation

? ?

Conversion Rate ↔ Power Dissipation

In an ideal world, the power dissipation is directly proportional to the conversion rate

Physics: Power = Energy/Time

To first order, this is also a reasonable baseline assumption for ADCs

ADCs: Power = Energy Conversion Rate

To second order, ADC power scales superlinear with conversion rate

Hard to capture analytically in a simple FoM

Deal with this in practice by comparing only ADCs with similar conversion rates

7

Resolution ↔ Power Dissipation

This tradeoff is much harder to quantify and depends on what limits the underlying circuits

First order results for different limiting mechanisms

Matching: Power grows 8x per added bit

Thermal noise: Power grows 4x per added bit

Process CV2: Power grows 2x per added bit

Which trade-offs should be used in an ADC FoM?

Looking at experimental data gives clues

Typically use peak Signal-to-Noise-and-Distortion Ratio (SNDR) as a proxy for resolution

8

10 20 30 40 50 60 70 80 90 100 11010

-14

10-12

10-10

10-8

10-6

SNDR [dB]

AD

C E

nerg

y =

P/f

s [J]

Experimental Data (1997-2004)

B. Murmann, "ADC Performance Survey 1997-2014," [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html

2x per 6dB

9



10

10 20 30 40 50 60 70 80 90 100 11010

-14

10-12

10-10

10-8

10-6

SNDR [dB]

AD

C E

nerg

y =

P/f

s [J]

10 20 30 40 50 60 70 80 90 100 11010

-14

10-12

10-10

10-8

10-6

SNDR [dB]

AD

C E

nerg

y =

P/f

s [J]


4x per 6dB

“Thermal Slope”

11


Observations

In 2004, the leading edge across all SNDR showed a 2x per bit tradeoff

A FoM that encapsulates this slope was justifiable at that time

In 2014, the situation is different

Leading edge designs with SNDR > 50dB show a 4x per bit tradeoff

Suggests that a larger fraction of recent designs is truly limited by noise, not process technology

Need to consider carefully which FoM is appropriate

12

R. H. Walden, “Analog-to-digital converter survey and analysis”, IEEE J. Select. Areas Commun., April 1999

Popular FoMs

Walden FoM1

2x per bit

Schreier FoM2 (DR)

4x per bit

Ignores distortion

Schreier FoM3 (SNDR)

4x per bit

Includes distortion

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1 R. H. Walden, “Analog-to-digital converter survey and analysis”, IEEE J. Select. Areas Commun., Apr. 1999 2 R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Wiley, 2005 3 A.M.A. Ali, et al., "A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration," JSSC, Dec. 2010

𝑭𝒐𝑴𝑺,𝑫𝑹 = 𝑫𝑹 + 𝟏𝟎𝒍𝒐𝒈𝑩𝑾

𝑷

𝑭𝒐𝑴𝑺 = 𝑺𝑵𝑫𝑹 + 𝟏𝟎𝒍𝒐𝒈𝒇𝒔/𝟐

𝑷

𝑭𝒐𝑴𝑾 =𝑷

𝒇𝒔 ⋅ 𝟐𝑬𝑵𝑶𝑩 𝑬𝑵𝑶𝑩 =

𝑺𝑵𝑫𝑹 − 𝟏𝟕𝟔

𝟔. 𝟎𝟐

State-of-the-Art FoM Lines

14


10 20 30 40 50 60 70 80 90 100 11010

-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

SNDR [dB]

AD

C E

nerg

y =

P/f

s [J]

ISSCC & VLSI 1997-2014

FoMS = 173dB

FoMW

= 5fJ/conv-step

104

105

106

107

108

109

1010

1011

130

135

140

145

150

155

160

165

170

175

180

185

fs [Hz]

FoM

S [dB

]FoMS vs. Conversion Rate (2014)

–10dB per

decade

15


FOMS computed

for fin near fs/2

FoMS vs. Conversion Rate (2009)

16


104

105

106

107

108

109

1010

1011

130

135

140

145

150

155

160

165

170

175

180

185

fs [Hz]

FoM

S [dB

]

FoMS vs. Conversion Rate (2004)

17


104

105

106

107

108

109

1010

1011

130

135

140

145

150

155

160

165

170

175

180

185

fs [Hz]

FoM

S [dB

]

13 dB

60x

Limits?

We have seen spectacular FoM improvements over the past decade – when will this come to an end?

High frequency asymptote of FOMS (60x improvement)

Process fT has scaled roughly 10x over last decade

The rest must have come from better design

Asymptote shift will continue as long as technology improves, and we find ways to improve design

Low frequency asymptote of FOMS (13dB improvement)

Much has been written about limits of ADC energy

A reasonably well-accepted limit is given by the energy of a class-B switched capacitor circuit

18

𝑷

𝒇𝒔 𝒎𝒊𝒏

= 𝟖𝒌𝑻 ⋅ 𝑺𝑵𝑹 ⇒ 𝑭𝑶𝑴𝑺 = 𝟏𝟗𝟐𝒅𝑩

104

105

106

107

108

109

1010

1011

130

140

150

160

170

180

190

200

fs [Hz]

FoM

S [dB

]FOMS Limits?

19


192 dB Close to impossible

186 dB Realistic bound?

Summary

FoMs must be simple to be useful

Consequences

FoMs do not tell the whole story, one must consider all relevant aspects of a design (table)

The tradeoffs hardcoded into a FoM are based on assumptions that may not always apply

FoM usage

Compare only designs with similar conversion rates and resolutions

FoMS is preferred for designs with SNDR > 50dB

FoMW still has its place for low-resolution designs

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a/d converter figures of merit and performance trends

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