adderessing mode and data transfer schemas 8085.rtf

8/14/2019 adderessing mode and data transfer schemas 8085.rtf

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Microprocessors and Microcontrollers/Architecture of Microprocessors Lecture Notes

Module 1 learning unit 1

1 A Computeris a programmable machine.

2 The two principal characteristics of a computer are:

!t responds to a specific set of instructions in a well"defined manner.# !t can

e$ecute a

prerecorded list of instructions %a program &.

' Modern computers are electronic and digital.

( Theactual machiner) wires* transistors* and circuits is called hardware. the

instructions and data are called software.


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1 All general"purpose computers re+uire the following hardware components:

2 Memory: ,nables a computer to store* at least temporaril)* data and programs. Mass storage device: Allows a computer to permanentl) retain large amounts of

data. -ommon mass storage deices include dis dries and tape dries.# Input device: 0suall) a e)board and mouse are the input deice through which

data and instructions enter a computer.

' Output device: A displa) screen* printer* or other deice that lets )ou see whatthe computer has accomplished.

( Central processing unit (CPU): The heart of the computer* this is the component

that actuall) e$ecutes instructions.

!n addition to these components* man) others mae it possible for the basiccomponents to wor together efficientl).

3or e$ample* eer) computer re+uires a bus that transmits data from one part

of the computer to another.

M. 4rishna 4umar/!!5c. 6angalore

M1/71/8une 9#/1


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1 -omputers can be generall)

classified b) sie and power as

follows* though there is

considerable oerlap:

2 Personal computer: A small* single"

user computer based on amicroprocessor.

!n addition to themicroprocessor* a personal

computer has a e)board for

entering data* a monitor for

displa)ing information* and astorage deice for saing data.

# Working station: A powerful*

single"user computer. Aworstation is lie apersonal

computer* but it has a morepowerful microprocessor and ahigher"+ualit) monitor.

' Minicomputer: A multi"

user computer capable ofsupporting from 19 to

hundreds of users

simultaneousl).

( Mainframe: A powerfulmulti"user computer capable

of supporting man)hundreds

or thousands of userssimultaneousl).

upercomputer: An

e$tremel) fast computer thatcan perform hundreds of

millions of instructions per

second.

Minicomputer:1 A midsied computer. !n sie and

power* minicomputers lie between

worstations and mainframes.

2 A minicomputer* a term no longermuch used* is a computer of a sie

intermediate between amicrocomputer and a mainframe.

T)picall)* minicomputers hae

been stand"alone computers%computer s)stems with attached

terminals and other deices& soldto small and mid"sie businesses

for general business applications

and to large enterprises fordepartment"leel operations.

# !n recent )ears* the minicomputerhas eoled into the ;mid"range

serer; and is part of a networ.!6M


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1 Most worstations also hae a mass

storage deice such as a dis drie* but

a special t)pe of worstation* called a

disless worstation* comes without a

dis drie.

2 The most common operating s)stemsfor worstations are 0N!B and

=indows NT.

!n terms of computing power*worstations lie between personal

computers and minicomputers*

although the line is fu) on both ends.# Cigh"end personal computers are

e+uialent to low"end worstations.

And high"end worstations are

e+uialent to minicomputers.

' Lie personal computers* mostworstations are single"user computers.

Coweer* worstations are t)picall)lined together to form a local"area

networ* although the) can also be used

as stand"alone s)stems.2& !n networing* workstation refers

to an) computer connected to a local"

area networ. !t could be a

worstation or a personal computer.( Mainframe: A er) large and e$pensie

computer capable of supportinghundreds* or een thousands* of userssimultaneousl). !n the hierarch) that

starts with a simple microprocessors %in

watches* for e$ample& at the bottom andmoes to supercomputer at the top*

mainframes are Dust below

supercomputers. !n some wa)s* mainframes are more

powerful than supercomputers because

the) support more simultaneous

programs. 6ut supercomputers can e$ecute a

single program faster than a

mainframe. The distinction betweensmall mainframes and minicomputers

is ague* depending reall) on how the

manufacturer wants to maret itsmachines.

E Microcomputer: The termmicrocomputer is generall)

s)non)mous with personal

computer* or a computer thatdepends on a microprocessor.

19 Microcomputers are designed to beused b) indiiduals* whether in the

form of >-s* worstations ornoteboo computers.

11 A microcomputer contains a ->0 on amicrochip %the microprocessor&* a

memor) s)stem %t)picall) ?M and

AM&* a bus s)stem and !/? ports*t)picall) housed in a motherboard.

12 Microprocessor: A silicon chip thatcontains a ->0. !n the world of

personal computers* the terms

microprocessor and ->0 are used

interchangeabl).1 A microprocessor %sometimes

abbreiated !P& is a digital electronic

component with miniaturied transistors

on a single semiconductor integrated

circuit %!-&.

1# ?ne or more microprocessors t)picall)

sere as a central processing unit %->0&

in a computer s)stem or handheld

deice.1'Microprocessors made possible the

adent of the microcomputer.1(At the heart of all personal

computers and most

woring stations sits a

microprocessor.1Microprocessors also control the

logic of almost all digital deices*

from cloc radios to fuel"inDections)stems for automobiles.

1 Three basic characteristics differentiate

microprocessors:

1E Instruction set: The set of instructionsthat the microprocessor can e$ecute.

29 "and#idt$: The number of bits

processed in a single instruction.21 Clock speed: Fien in megahert

%MC&* the cloc speed determines

how man)instructions per second the

processor can e$ecute.

M. 4rishna 4umar/!!5c.

6angalore M1/71/8une9#/


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1 !n both cases* the higher the alue* the

more powerful the ->0. 3or e$ample* a

2 bit microprocessor that runs at '9MC

is more powerful than a 1("bit

microprocessor that runs at 2'MC.

2 !n addition to bandwidth and clocspeed* microprocessors are classified as

being either !5- %reduced instruction

set computer& or -!5- %comple$instruction set computer&.

upercomputer: A supercomputer

is a computer that performs at ornear the currentl) highest

operational rate for computers.

# A supercomputer is t)picall) used for

scientific and engineering applications

that must handle er) large databases ordo a great amount of computation %or

both&.' At an) gien time* there are usuall) a

few well"publicied supercomputers

that operate at the er) latest andalwa)s incredible speeds.

( The term is also sometimes applied

to far slower %but still impressiel)

fast& computers. Most supercomputers are reall)

multiple computers that performparallel processing. !n general* there are two

parallel processing

approaches: s)mmetric

multiprocessing %5M>& and

massiel) parallel

processing %M>>&.

E Microcontroller: A highl)

integrated chip that contains all thecomponents comprising a

controller.19T)picall) this includes a ->0* AM*some form of ?M* !/? ports* and

timers.

11 0nlie a general"purpose computer*

which also includes all of these

components* a microcontroller isdesigned for a er) specific tas " to

control a particular s)stem.

12 A microcontroller differs from amicroprocessor* which is a general"purpose chip that is used to create amulti"function computer or deice and

re+uires multiple chips to handlearious tass.

1 A microcontroller is meant to be

more self"contained and

independent* and functions as atin)* dedicated computer.

1# The great adantage of

microcontrollers* as opposed tousing larger microprocessors* is

that the parts"count and design

costs of the item being

controlled can be ept to aminimum.

1' The) are t)picall) designed using

-M?5 %complementar) metal o$idesemiconductor& technolog)* an efficient

fabrication techni+ue that uses less

power and is more immune to powerspies than other techni+ues.

1( Microcontrollers are sometimes called

embedded microcontrollers,which Dustmeans that the) are part of an

embedded s)stem that is* one part of alarger deice or s)stem.

1 Controller: A deice that

controls the transfer of data from

a computer to aperipheral deice

and ice ersa.1 3or e$ample* dis dries* displa)

screens* e)boards and printers

all re+uire controllers.1E !n personal computers* the controllers

are often single chips.

29 =hen )ou purchase a computer* itcomes with all the necessar)

controllers for standard components*

such as the displa) screen* e)board*

and dis dries.


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1 !f )ou attach additional deices*

howeer* )ou ma) need to insert new

controllers that come on e$pansion

boards.

2 -ontrollers must be designed to

communicate with the computer-s " the AT bus* >-!

%>eripheral -omponent !nterconnect &

and 5-5!.

# =hen )ou purchase a controller*therefore* )ou must ensure that it

conforms to the bus architecture that

)our computer uses.' 5hort for Peripheral Component

Interconnect, a local bus standarddeeloped b) !ntel -orporation.

( Most modern >-s include a >-! bus in

addition to a more general !A5

e$pansion bus. >-! is also used on newer ersions of the

Macintosh computer.

>-! is a (#"bit bus* though it is usuall)

implemented as a 2 bit bus. !t can runat cloc speeds of or (( MC.

E At 2 bits and MC* it )ields a

throughput rate of 1 M6ps.19 5hort for smallcomputersystem

interface* a parallel interface standard

used b) Apple Macintosh computers*>-s* and man) 0N!B s)stems for

attaching peripheral deices to

computers.

11 Nearl) all Apple Macintosh computers*e$cluding onl) the earliest Macs and the

recent iMac* come with a 5-5! port for

attaching deices such as dis dries

and printers.12 5-5! interfaces proide for faster data

transmission rates %up to 9 megab)tes

per second& than standard serial andparallel ports. !n addition* )ou can

attach man) deices to a single 5-5!

port* so that 5-5! is reall) an !/? busrather than simpl) an interface

1Although 5-5! is an AN5! standard*there are man) ariations of it* so two

5-5! interfaces ma) be incompatible.1#3or e$ample* 5-5! supports seeral

t)pes of connectors.1' =hile 5-5! has been the standard

interface for Macintoshes* the iMac

comes withIDE* a less e$pensie

interface* in which the controller isintegrated into the disor -@"?M

drie.

1(The following arieties of 5-5! arecurrentl) implemented:

15-5!"1:0ses an "bit bus* and supportsdata rates of # M6ps.

15-5!"2:5ame as 5-5!"1* but uses a

'9"pin connector instead of a 2'"pin

connector* and supports multiple

deices. This is what most peoplemean when the) refer to plain SCSI.

1E=ide 5-5!: 0ses a wider cable

%1( cable lines to ( pins& tosupport 1("bit transfers.

293ast 5-5!: 0ses an "bit bus* but

doubles the cloc rate to support datarates of 19 M6ps.

21 3ast =ide 5-5!:0ses a 1("bit bus and

supports data rates of 29 M6ps.22 0ltra 5-5!: 0ses an "bit bus* and

supports data rates of 29 M6ps.

2 =ide 0ltra2 5-5!:0ses a 1("bit bus

and supports data rates of 9 M6ps.2#5-5!": 0ses a 1("bit bus and

supports data rates of #9 M6ps. Also

called UltraWide SCSI.

2'0ltra2 5-5!: 0ses an "bit bus andsupports data rates of #9 M6ps.


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1 %m&edded system: A specialied computer s)stem that is part of a larger s)stem

or machine.

2 T)picall)* an embedded s)stem is housed on a single microprocessor board with

the programs stored in ?M.

7irtuall) all appliances that hae a digital !nterface" watches* microwaes* 7-s*

cars "utilie embedded s)stems.# 5ome embedded s)stems include an operating s)stem* but man) are so

specialied that the entire logic can be implemented as a single program.

MIC'O CO'O**%'MIC'O P'OC%%'

!t is a single chip !t is a ->0

-onsists Memor)* Memor)* !/? >orts to be

!/o ports connected e$ternall)

CP

CPUM%MO'

+

M%MO'+

I,O PO'

I,O

PO'

Definitions:

1 A -igital ignal Processoris a special"purpose ->0 %-entral >rocessing 0nit&that proides ultra"fast instruction se+uences* such as shift and add* and multipl)

and add* which are commonl) used in math"intensie signal processing

applications.

2 A digital signal processor%-P& is a specialied microprocessor designedspecificall) for digital signal processing* generall) in real time.

Digital

G operating by the use of discrete signals to represent data in the form of


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numbers.

Signal

G a ariable parameter by which information is coneyed through an

electronic circuit.

Processing

G to perform operations on data according to programmed instructions.

-igital ignal processingG changing or anal)sing information which is measured as discrete

se+uences of numbers.1 -igital signal processing %@5>& is the stud) of signals in a digital representation

and the processing methods of these signals.

2 @5> and analog signal processing are subfields of signal processing.M. 4rishna 4umar/!!5c. 6angalore

M1/71/8une 9#/(


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@5> has three maDor subfields:

1 Audio signal processing* @igital image processing and 5peech processing.

2 5ince the goal of @5> is usuall) to measure or filter continuous real"world analogsignals* the first step is usuall) to conert the signal from an analog to a digital

form* b) using an analog to digital conerter.

?ften* the re+uired output signal is another analog output signal* which re+uires adigital to analog conerter.

C$aracteristics of -igital ignal Processors:

1 5eparate program and data memories %Carard architecture&.

2 5pecial !nstructions for 5!M@ %5ingle !nstruction* Multiple @ata& operations. ?nl) parallel processing* no multitasing.

# The abilit) to act as a direct memor) access deice if in a host enironment.

' Taes digital data from A@- %Analog"@igital -onerter& and passes out data

which is finall) output b) conerting into analog b) @A- %@igital"Analog-onerter&.

( analog input""HA@-""H@5>""H@A-""H analog output.

.nalog front end.nalo

g .ntialiasing

signal

in filter/ ,0/ .,-

converter


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-P.nalog &ack end .na

log-,. converter/

Processor reconstruction

sign

al

filter

out

put

@A>5)stem

Multiply-accumulate

hardware:

1 Multipl)accumulate is

the most

fre+uentl) usedoperation in

digital signal

p

ro

ces

s

in

g

.

2 !

n

orderto

implement this

effici

entl)*the

@5>

hasan

hard

ware

multiplier* an

accumulator with anade+uate number of

bits to hold the sumof products and ate$plicit multipl)"

accumulate

instructions. Harvard architecture:

in this memor)

architecture* there are

two memor) spaces.

>rogram memor) and

data memor).M. 4rishna4umar/!!5c. 6angalore

M1/71/8une

9#/


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+

n n

Multiplier

Product register

2n

.-- ,

U"

.ccumulator

2n

A

MA-


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+

13 13

Multiplier

42

56

.-- , U"

56

7uard &its

8 42

A MA- unit with

accumulator guard bits1 The processor core connects to these

memor) spaces b) two separate bus

sets* allowing two simultaneous


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access to memor). This arrangement

doubles the processor memor) bandwidth.

1 Zero-overhead looping: one commoncharacteristics of @5> algorithms is thatmost of the processing time is split on

e$ecuting instructions contained with

relatiel) small loops.

2 The term ero oerhead looping

means that the processor can

e$ecute loops without consuming

c)cles to test the alue of the loop

counter* perform a conditional

branch to the top of the loop* and

decrement the loop counter.

M. 4rishna 4umar/!!5c.6angalore M1/71/8une9#/E


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Processi

ng 'esult -ata &us

unit

Operands

tatus

Opco

de

Instructions

-ata , Instructions

-ata programControl unit

memory

7on Neuman Architecture

Processi

ng 'esult , operands-ataunit

memory

.ddress

tatus Opcode


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Control unit Program

memoryInstructions

.ddress

Carard Architecture


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Processi

ng 'esult , operands

-ataunit

memory

.ddress

tatus

Opco

de

Control unitprogram memory

Instructions

.ddress

Modified Carard Architecture-ata &us


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M%MO'+

Program -ata ,

'OM program-ata ,

.'.Mprogram

-.'.M

Program &us

Memo

ry Program controller Memory C.*Ucontrol

Program counter mapped

Multiplier

Multip

roc

.ccumulat

ortatus,control registers

essing registers .CC &uffer

Interr

upt

0ard#are

stack

.u9iliary s$ifters

'esisters arit$metic

Initialisat

ion

7eneration

logic .rit$metic logic unit

Oscillato

r,

Instruction

register

Unit

(.'.U) (.*U)

timer

-ata &us

!nternal Architecture of

the TM529-'B @5>

Perip$eral

erial

port 1

erial

port 2

-M

erial port

"uffered

serial port

imer

0ost

port

interface

est ,

emulation


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1 The adantages of

@5> are:

ersatility:2 digital s)stems

can be

reprogrammedfor other

applications %at

least where

program

mable@5>

chips are

used& digital s)stems

can be ported to

different

hardware %for

e

$a

m

pl

e

a

different @5> chip or

board leel product&

'epeata&ility:

1 digital s)stems can beeasil) duplicated

2 digital s)stem

responses do not driftwith temperature

M.

4r

ishna 4umar/!!5c.

6angaloreM1/71/8une

9#/11


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digital s)stems do not depend on strict component tolerances.

implicity:

1 some things can be done more easil) digitall) than with analogue s)stems2 @5> is used in a er) wide ariet) of applications but most share some common

features: the) use a lot of multipl)ing and adding signals.# the) deal with signals that come from the real world.

' the) re+uire a response in a certain time.

3igure: A bloc diagram %or dataflow graph&1 =hat is the difference between a @5> and a microprocessor I

2 The essential difference between a @5> and a microprocessor is that a @5>

processor has features designed to support high"performance* repetitie*numericall) intensie tass.

!n contrast* general"purpose processors or microcontrollers %F>>s / M-0s forshort& are either not specialied for a specific ind of applications %in the caseof general"purpose processors&* or the) are designed for control"orientedapplications %in the case of microcontrollers&.

# 3eatures that accelerate performance in @5> applications include:

' 5ingle"c)cle multipl)"accumulate capabilit)J high"performance @5>s often hae


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two multipliers that enable two multipl)"accumulate operations per instruction

c)cleJ some @5> hae four or more multipliers.

1 5pecialied addressing modes* for e$ample* pre" and post"modification of address

pointers* circular addressing* and bit"reersed addressing.2 Most @5>s proide arious configurations of on"chip memor) and peripherals

tailored for @5> applications. @5>s generall) feature multiple"access memor)

architectures that enable @5>s to complete seeral accesses to memor) in a single

instruction c)cle.


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1 5pecialied e$ecution control. 0suall)* @5> processors proide a loop instruction

that allows tight loops to be repeated without spending an) instruction c)cles for

updating and testing the loop counter or for Dumping bac to the top of the loop

2 @5> processors are nown for their irregular instruction sets* which generall)

allow seeral operations to be encoded in a single instruction.

3or e$ample* a processor that uses 2"bit instructions ma) encode two additions*two multiplications* and four 1("bit data moes into a single instruction.

# !n general* @5> processor instruction sets allow a data moe to be performed in

parallel with an arithmetic operation. F>>s / M-0s* in contrast* usuall) specif) asingle operation per instruction.

' =hat is reall) important is to choose the processor that is best suited for

)our application.

( !f a F>>/M-0 is better suited for )our @5> application than a @5> processor* theprocessor of choice is the F>>/M-0.

!t is also worth noting that the difference between @5>s and F>>s/M-0s is

fading: man) F>>s/M-0s now include @5> features* and @5>s are increasingl)

adding microcontroller features.Module 1: learning unit 2

868; Microprocessor

ContentsFeneral definitions1 ?eriew of 9' microprocessor

2 ?eriew of 9( microprocessor

5ignals and pins of 9( microprocessor

The salient features of 9' Kp are:

# !t is a bit microprocessor.

' !t is manufactured with N"M?5 technolog).

( !t has 1("bit address bus and hence can address up to 21( (''( b)tes %(#46&

memor) locations through A9"A1'. The first lines of address bus and lines of data bus are multiple$ed A@9G A@.

@ata bus is a group of lines @9G @.E !t supports e$ternal interrupt re+uest.

19 A 1( bit program counter %>-&

11 A 1( bit stac pointer %5>&

12 5i$ "bit general purpose register arranged in pairs: 6-* @,* CL.1 !t re+uires a signal '7 power suppl) and operates at .2 MC single phase

cloc.

1# !t is enclosed with #9 pins @!> %@ual in line pacage&.

Overvie# of 868; microprocessor

9' Architecture

1 >in @iagram

2 3unctional 6loc @iagram


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Memory

1 >rogram* data and stac memories occup) the same memor) space. The total

addressable memor) sie is (# 46.2 Program memory " program can be located an)where in memor). 8ump* branch

and call instructions use 1("bit addresses* i.e. the) can be used to Dump/branch

an)where within (# 46. All Dump/branch instructions use absolute addressing. -ata memory " the processor alwa)s uses 1("bit addresses so that data can

beplaced an)where.# tack memory is limited onl) b) the sie of memor). 5tac grows downward.' 3irst (# b)tes in a ero memor) page should be resered for ectors used b) 5T

instructions.

Interrupts

1 The processor has ' interrupts. The) are presented below in the order of theirpriorit) %from lowest to highest&:

1 I' is masable 99A compatible interrupt. =hen the interrupt occurs the

processor fetches from the bus one instruction* usuall) one of these instructions:2 ?ne of the 5T instructions %5T9" 5T&. The processor saes current

program counter into stac and branches to memor) location N O %where N is a"bit number from 9 to supplied with the 5T instruction&.

C.** instruction % b)te instruction&. The processor calls the subroutine* addressof which is specified in the second and third b)tes of the instruction.

# ';?; is a masable interrupt. =hen this interrupt is receied the processor

saes the contents of the >- register into stac and branches to 2-C%he$adecimal& address.

' '3?; is a masable interrupt. =hen this interrupt is receied the processorsaes the contents of the >- register into stac and branches to #C%he$adecimal& address.

( '=?; is a masable interrupt. =hen this interrupt is receied the processor

saes the contents of the >- register into stac and branches to -C%he$adecimal& address.

'.P is a non"masable interrupt. =hen this interrupt is receied the processor

saes the contents of the >- register into stac and branches to 2#C

%he$adecimal& address. All masable interrupts can be enabled or disabled using ,! and @!

instructions. 5T '.'* 5T(.' and 5T.' interrupts can be enabled or

disabled indiiduall) using 5!M instruction.

'eset ignals

1 '%% I: =hen this signal goes low* the program counter %>-& is set to ero*

Kp is reset and resets the interrupt enable and CL@A flip"flops.2 The data and address buses and the control lines are "stated during ,5,T and

because of as)nchronous nature of ,5,T* the processor internal registers and

flags ma) be altered b) ,5,T with unpredictable results. ,5,T !N is a 5chmitt"triggered input* allowing connection to an "- networ

for power"on ,5,T dela).


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1 0pon power"up* ,5,T !N must

remain low for at least 19 ms after

minimum 7cc has been reached.

2 3or proper reset operation after the

power G up duration* ,5,T !N

should be ept low a minimum ofthree cloc periods.

The ->0 is held in the reset conditionas long as ,5,T !N is applied.T)pical >ower"on ,5,T - alues1 '4* -1 1K3.

# '%% OU: This signal indicates thatKp is being reset. This signal can be used

to reset other deices. The signal is

s)nchronied to the processor cloc andlasts an integral number of cloc periods.

erial communication ignal

1 I- B erial Input -ata *ine: The dataon this line is loaded into accumulator bit

wheneer a !M instruction is

e$ecuted.2 O- F erial Output -ata *ine: The

5!M instruction loads the alue of bit

ofthe accumulator into 5?@ latch if bit

( %5?,& of the accumulator is 1.

-M. ignals

1 0O*-: !ndicates that another master is

re+uesting the use of the address and data

buses. The ->0* upon receiing the holdre+uest* will relin+uish the use of the bus

as soon as the completion of the current

bus transfer.2 !nternal processing can continue. The

processor can regain the bus onl) after

the C?L@ is remoed. =hen the C?L@ is acnowledged* the

Address* @ata @* = and !?/M lines

are "stated.

# 0*-.: 0old .ckno#ledge:

!ndicates that the ->0 has receied

the C?L@re+uest and that it willrelin+uish the bus in the ne$t

cloc c)cle.

' CL@A goes low after the Coldre+uest is remoed. The ->0 taesthe bus one half"cloc c)cle afterCL@A goes low.

( '%.-+: This signal5)nchronies the fast ->0

and the slow memor)*peripherals.

!f ,A@P is high during a read or

write c)cle* it indicates that thememor) or peripheral is read) to

send or receie data.

!f ,A@P is low* the ->0 willwait an integral number of

cloc c)cle for ,A@P to go

high before completing the reador write c)cle.

E ,A@P must conform to specified

setup and hold times.

'egisters

1 .ccumulator or A register is an "bit

register used for arithmetic* logic* !/?

andload/store operations.2 lag 'egister has fie 1"bit flags. ign " set if the most significant bit of

the result is set.

# Dero " set if the result is ero.' .u9iliary carry " set if there was a

carr) out from bit to bit # of the

result.( Parity " set if the parit) %the number of

set bits in the result& is een.

Carry " set if there

was a carr) during

addition* or borrow

during

subtraction/compariso

n/rotation.M. 4rishna 4umar/!!5c.


9#/1


30/68


7eneral 'egisters

1 "bit 6 and "bit - registers can be used as one 1("bit 6- register pair. =hen

used as a pair the - register contains low"order b)te. 5ome instructions ma)use 6- register as a data pointer.

2 "bit @ and "bit , registers can be used as one 1("bit @, register pair. =hen

used as a pair the , register contains low"order b)te. 5ome instructions ma) use@, register as a data pointer.

"bit C and "bit L registers can be used as one 1("bit CL register pair. =hen

used as a pair the L register contains low"order b)te. CL register usuall) containsa data pointer used to reference memor) addresses.

# tack pointer is a 1( bit register. This register is alwa)s

decremented/incremented b) 2 during push and pop.

' Program counter is a 1("bit register.

Instruction et

1 9' instruction set consists of the following instructions:

2 @ata moing instructions.

Arithmetic " add* subtract* increment and decrement.# Logic " AN@* ?* B? and rotate.

' -ontrol transfer " conditional* unconditional* call subroutine* returnfrom subroutine and restarts.

( !nput/?utput instructions.

?ther " setting/clearing flag bits* enabling/disabling interrupts* stac operations*

etc.

.ddressing mode

1 'egister " references the data in a register or in a register pair.'egister indirect " instruction specifies register pair containing address* wherethe data is located.

-irect/ Immediate " or 1("bit data.Module 1: learning unit

8683 Microprocessor

!t is a 1("bit Kp.

9( has a 29 bit address bus can access up to 229

memor) locations %1 M6&.!t can support up to (#4 !/? ports.!t proides 1#* 1( "bit registers.

!t has multiple$ed address and data bus A@9" A@1' and A1( G A1E.

!t re+uires single phase cloc with Q dut) c)cle to proide internal

timing. 9( is designed to operate in two modes* Minimum and Ma$imum.

!t can prefetches upto ( instruction b)tes from memor) and +ueues them in order

to speed up instruction e$ecution.!t re+uires '7 power suppl).

A #9 pin dual in line pacage

Minimum and Ma9imum Modes:

The minimum mode is selected b) appl)ing logic 1 to the MN / MBinput pin. This is a

single microprocessor configuration.

The ma$imum mode is selected b) appl)ing logic 9 to the MN / MBinput pin. This is a

multi micro processors configuration.


M1/71/8une 9#/1


31/68


7- 1 .-15 2

.-14 4 .-125 .-

11

; .-163

.- register.The 6!0 is also responsible for generating bus control signals such as those for memor)

read or write and !/? read or write.

%%CUIO UIThe ,$ecution unit is responsible for decoding and e$ecuting all instructions. The

,0 e$tracts instructions from the top of the +ueue in the 6!0* decodes them*

generates operands if necessar)* passes them to the 6!0 and re+uests it to perform theread or write b)s c)cles to memor) or !/? and perform the operation specified b) the

instruction on the operands.@uring the e$ecution of the instruction* the ,0 tests the status and control flags and

updates them based on the results of e$ecuting the instruction.

!f the +ueue is empt)* the ,0 waits for the ne$t instruction b)te to be fetched and shiftedto top of the +ueue.

=hen the ,0 e$ecutes a branch or Dump instruction* it transfers control to a

location corresponding to another set of se+uential instructions.

=heneer this happens* the 6!0 automaticall) resets the +ueue and then begins tofetch instructions from this new location to refill the +ueue.

Module 1 and learning unit #:

ignal -escription of 8683The Microprocessor 9( is a 1("bit ->0 aailable indifferent cloc rates and pacaged in a #9 pin -,@!> or plastic pacage.The 9( operates in single processor or multiprocessor configuration to achiee high

performance. The pins sere a particular function in minimum mode %single processor

mode& and other function in ma$imum mode configuration %multiprocessor mode &.

The 9( signals can be categorised in three groups. The first are the signal haing

common functions in minimum as well as ma$imum mode.

The second are the signals which hae special functions for minimum mode and

third are the signals haing special functions for ma$imum mode.M. 4rishna 4umar/!!5c. 6angalore

M1/71/8une 9#/22


38/68


$e follo#ing signal descriptions are common for &ot$ modes?

.-1;B.-6: These are the time multiple$ed memor) !/? address and data lines.

Address remains on the lines during T1 state* while the data is aailable on the data bus

during T2* T* Tw and T#.

These lines are actie high and float to a tristate during interrupt acnowledge and

local bus hold acnowledge c)cles..1


39/68


'%.-+: This is the acnowledgement from the slow deice or memor) that the) hae

completed the data transfer. The signal made aailable b) the deices is s)nchronied b)

the 2#A cloc generator to proide read) input to the 9(. the signal is actie high.I'BInterrupt 'eHuest: This is a triggered input. This is sampled during the last

cloc c)cles of each instruction to determine the aailabilit) of the re+uest. !f an)

interrupt re+uest is pending* the processor enters the interrupt acnowledge c)cle.This can be internall) mased b) resulting the interrupt enable flag. This signal is actie

high and internall) s)nchronied.

%This input is e$amined b) a R=A!TS instruction. !f the T,5T pin goes low*

e$ecution will continue* else the processor remains in an idle state. The input is

s)nchronied internall) during each cloc c)cle on leading edge of cloc.

C*>" -loc !nput: The cloc input proides the basic timing for processor operation

and bus control actiit). !ts an as)mmetric s+uare wae with Q dut) c)cle.

M,M: The logic leel at this pin decides whether the processor is to operate in

either minimum or ma$imum mode.

$e follo#ing pin functions are for t$e minimum mode operation of 8683?

M,IOF Memory,IO: This is a status line logicall) e+uialent to 52 in ma$imum mode.

=hen it is low* it indicates the ->0 is haing an !/? operation* and when it is high* it

indicates that the ->0 is haing a memor) operation. This line becomes actie high in the

preious T# and remains actie till final T# of the current c)cle. !t is tristated during

local bus hold acnowledge .

I.Interrupt .ckno#ledge: This signal is used as a read strobe for interrupt

acnowledge c)cles. i.e. when it goes low* the processor has accepted the interrupt.

.*% F .ddress *atc$ %na&le: This output signal indicates the aailabilit) of the alid

address on the address/data lines* and is connected to latch enable input of latches. This

signal is actie high and is neer tristated.

-,'F -ata ransmit,'eceive: This output is used to decide the direction of dataflow through the transreceiers %bidirectional buffers&. =hen the processor sends out

data* this signal is high and when the processor is receiing data* this signal is low.

-% F -ata %na&le: This signal indicates the aailabilit) of alid data oer the

address/data lines. !t is used to enable the transreceiers % bidirectional buffers & to

separate the data from the multiple$ed address/data signal. !t is actie from the middle

of T2 until the middle of T#. This is tristated during R hold acnowledgeS c)cle.

0O*-/ 0*-.B .ckno#ledge: =hen the C?L@ line goes high* it indicates to theprocessor that another master is re+uesting the bus access.

The processor* after receiing the C?L@ re+uest* issues the hold acnowledge signal on

CL@A pin* in the middle of the ne$t cloc c)cle after completing the current bus

c)cle.At the same time* the processor floats the local bus and control lines. =hen theprocessor detects the C?L@ line low* it lowers the CL@A signal. C?L@ is an

as)nchronous input* and is should be e$ternall) s)nchronied.

!f the @MA re+uest is made while the ->0 is performing a memor) or !/? c)cle* it will

release the local bus during T# proided:

1.The re+uest occurs on or before T2 state of the current c)cle.

2.The current c)cle is not operating oer the lower b)te of a word.

.The current c)cle is not the first acnowledge of an interrupt acnowledge se+uence.M. 4rishna 4umar/!!5c. 6angalore

M1/71/8une 9#/2#


40/68


#. A Loc instruction is not being e$ecuted.

he following pin function are applica!le for ma"imum mode operation of #$#%.

2/ 1/ 6 F tatus *ines: These are the status lines which reflect the t)pe of operation*

being carried out b) the processor. These become actiit) during T# of the preious c)cle

and actie during T1 and T2 of the current bus c)cles.

2

1 6 Indication

6 6 6Interrupt.ckno#ledge

6 6 1 'ead I,O port

6 1 6 Write I,O port6 1 1 0alt1 6 6 Code .ccess

1 6 1 'ead memory1 1 6 Write memory1 1 1 Passive

*OC>This output pin indicates that other s)stem bus master will be preented from

gaining the s)stem bus* while the L?-4 signal is low.

The L?-4 signal is actiated b) the RL?-4S prefi$ instruction and remains actie until

the completion of the ne$t instruction. =hen the ->0 is e$ecuting a critical instructionwhich re+uires the s)stem bus* the L?-4 prefi$ instruction ensures that other

processors connected in the s)stem will not gain the control of the bus.

The 9(* while e$ecuting the prefi$ed instruction* asserts the bus loc signal

output* which ma) be connected to an e$ternal bus controller.

G1/ G6F Gueue tatus: These lines gie information about the status of the code"prefetch +ueue. These are actie during the -L4 c)cle after while the +ueue operation is

performed.This modification in a simple fetch and e$ecute architecture of a conentional

microprocessor offers an added adantage of pipelined processing of the instructions.

The 9( architecture has ("b)te instruction prefetch +ueue. Thus een the largest %(

"b)tes& instruction can be prefetched from the memor) and stored in the prefetch.

This results in a faster e$ecution of the instructions.

!n 9' an instruction is fetched* decoded and e$ecuted and onl) after the e$ecutionofthis instruction* the ne$t one is fetched.

6) prefetching the instruction* there is a considerable speeding up ininstruction e$ecution in 9(. This is nown as instruction pipelining.At the starting the -5:!> is loaded with the re+uired address from which the e$ecution isto be started. !nitiall)* the +ueue will be empt) an the microprocessor starts a fetchoperation to bring one b)te %the first b)te& of instruction code* if the -5:!> address is oddor two b)tes at a time* if the -5:!> address is een.The first b)te is a complete opcode in case of some instruction %one b)te opcode

instruction& and is a part of opcode* in case of some instructions % two b)te opcode

instructions&* the remaining part of code lie in second b)te.The second b)te is then decoded in continuation with the first b)te to decide the

instruction length and the number of subse+uent b)tes to be treated as instruction data.


41/68

M. 4rishna 4umar/!!5c. 6angalore M1/71/8une 9#/2'


42/68


The +ueue is updated after eer) b)te is read from the +ueue but the fetch c)cle is

initiated b) 6!0 onl) if at least two b)tes of the +ueue are empt) and the ,0 ma) be

concurrentl) e$ecuting the fetched instructions.

The ne$t b)te after the instruction is completed is again the first opcode b)te of the ne$t

instruction. A similar procedure is repeated till the complete e$ecution of the

program.The fetch operation of the ne$t instruction is oerlapped with the e$ecution ofthe current instruction. As in the architecture* there are two separate units* namel)

,$ecution unit and 6us interface unit.

=hile the e$ecution unit is bus) in e$ecuting an instruction* after it is completel)

decoded* the bus interface unit ma) be fetching the b)tes of the ne$t instruction

from memor)* depending upon the +ueue status.

G1 G6 Indication

6 6 o operation

6 1irst &yte of t$e opcode from t$e Hueue

6 %mpty Hueue1

1 1 u&seHuent &yte from t$e Hueue

'G,76/'G,71F 'eHuest,7rant:These pins are used b) the other local bus master

in ma$imum mode* to force the processor to release the local bus at the end of the

processor current bus c)cle.

,ach of the pin is bidirectional with U/FT9 haing higher priorit) than U/FT1.

U/FT pins hae internal pull"up resistors and ma) be left unconnected.

'eHuest,7rant seHuence is as follo#s:1.A pulse of one cloc wide from another bus master re+uests the bus access to 9(.

2.@uring T#%current& or T1%ne$t& cloc c)cle* a pulse one cloc wide from 9( to the

re+uesting master* indicates that the 9( has allowed the local bus to float and that it

will enter the Rhold acnowledgeS state at ne$t c)cle. The ->0 bus interface unit is liel)to be disconnected from the local bus of the s)stem.

.A one cloc wide pulse from the another master indicates to the 9( that the hold

re+uest is about to end and the 9( ma) regain control of the local bus at the ne$t

cloc c)cle. Thus each master to master e$change of the local bus is a se+uence of pulses. There must be at least one dead cloc c)cle after each bus e$change.

The re+uest and grant pulses are actie low.

3or the bus re+uest those are receied while 9( is performing memor) or !/?c)cle* the granting of the bus is goerned b) the rules as in case of C?L@ and CL@A

in minimum mode.

7eneral "us Operation:

The 9( has a combined address and data bus commonl) referred as a time multiple$edaddress and data bus.

The main reason behind multiple$ing address and data oer the same pins is the

ma$imum utilisation of processor pins and it facilitates the use of #9 pin standard @!>

pacage.


M1/71/8une 9#/2(


43/68


The bus can be demultiple$ed using a few latches and transreceiers* when

eer re+uired.

6asicall)* all the processor bus c)cles consist of at least four cloc c)cles. These are

referred to as T1* T2* T* T#. The address is transmitted b) the processor during T1. !t is

present on the bus onl) for one c)cle.

The negatie edge of this AL, pulse is used to separate the address and the data or statusinformation. !n ma$imum mode* the status lines 59* 51 and 52 are used to indicate the

t)pe of operation.

5tatus bits 5 to 5 are multiple$ed with higher order address bits and the 6C, signal.

Address is alid during T1 while status bits 5 to 5 are alid during T2 through T#.

Memory read

cycle

Memory #rite

cycle

C*>

1

2

)

4

#

5

1

2

)

4

#

5

.*%

2F

6

.dd,s

tat

.1


44/68

!n this mode* all the control signals are gien out b) the microprocessor chipitself. There is a single microprocessor in the minimum mode s)stem.The remaining components in the s)stem are latches* transreceiers* cloc generator*

memor) and !/? deices. 5ome t)pe of chip selection logic ma) be re+uired for

selecting memor) or !/? deices* depending upon the address map of the s)stem.

Latches are generall) buffered output @"t)pe flip"flops lie #L5 or 22. The) are

used for separating the alid address from the multiple$ed address/data signals and are

controlled b) the AL, signal generated b) 9(.


M1/71/8une 9#/2


45/68


Transreceiers are the bidirectional buffers and some times the) are called as data

amplifiers. The) are re+uired to separate the alid data from the time multiple$ed

address/data signals.

The) are controlled b) two signals namel)* @,N and @T/.

The @,N signal indicates the direction of data* i.e. from or to the processor. The s)stem

contains memor) for the monitor and users program storage.0suall)* ,>?M are used for monitor storage* while AM for users program storage. A

s)stem ma) contain !/? deices.

The woring of the minimum mode configuration s)stem can be better describedin terms of the timing diagrams rather than +ualitatiel) describing the operations.

The opcode fetch and read c)cles are similar. Cence the timing diagram can be

categoried in two parts* the first is the timing diagram for read c)cle and the second

is the timing diagram for write c)cle.

The read c)cle begins in T1 with the assertion of address latch enable %AL,& signal and

also M / !? signal. @uring the negatie going edge of this signal* the alid address islatched on the local bus.

The 6C, and A9 signals address low* high or both b)tes. 3rom T1 to T# * the M/!?signal indicates a memor) or !/? operation.

At T2* the address is remoed from the local bus and is sent to the output. The bus is

then tristated. The read %@& control signal is also actiated in T2.

The read %@& signal causes the address deice to enable its data bus driers. After @goes low* the alid data is aailable on the data bus.

The addressed deice will drie the ,A@P line high. =hen the processor returns the

read signal to high leel* the addressed deice will again tristate its bus driers.A write c)cle also begins with the assertion of AL, and the emission of the address. The

M/!? signal is again asserted to indicate a memor) or !/? operation. !n T2* after sending

the address in T1* the processor sends the data to be written to the addressed location.

The data remains on the bus until middle of T# state. The = becomes actie at the

beginning of T2 %unlie @ is somewhat dela)ed in T2 to proide time for floating&.

The 6C, and A9 signals are used to select the proper b)te or b)tes of memor) or !/?

word to be read or write.

The M/!?* @ and = signals indicate the t)pe of data transfer as specified in table

below.


M1/71/8une 9#/2


46/68

Microprocessors and Microcontrollers/Architecture of

MicroprocessorsLecture

Notes

1 )2

)

4 W 5 1

Clk

.*%

.-- , .U

"0% F

.13

=F

4.1@,N output depends upon the status of the !?6 pin.

!f !?6 is grounded* it acts as master cascade enable to control cascade 2'EA* else itacts as peripheral data enable used in the multiple bus configurations.!NTA pin used to issue two interrupt acnowledge pulses to the interrupt controller or to

an interrupting deice.

!?-* !?=- are !/? read command and !/? write command signals respectiel). Thesesignals enable an !? interface to read or write the data from or to the address port.

The M@-* M=T- are memor) read command and memor) write command signals

respectiel) and ma) be used as memor) read or write signals.All these command signals instructs the memor) to accept or send data from or to

the bus.

3or both of these write command signals* the adanced signals namel) A!?=- and

AM=T- are aailable.Cere the onl) difference between in timing diagram between minimum mode and

ma$imum mode is the status signals used and the aailable control and adanced

command signals.


M1/71/8une 9#/9


49/68


Cl

k -%

1

6 -, '

Control

&us

828

8 IO'C

2

IOW

MWC

'eset 'eset

6

.

%

Clk

Clk

1

IO"

.

* M'-C7enerator

C%

2

'-+

828

5 'eady

@

;

8683C

*

>.-3B.-1; .,- *atc$e

s

.ddress &us

.13B.1"us

"P'C'G*C

>

C*

>

'%" "'%G

cc 7-

+",'%

" C*

> "C*>.+'%G .% IO"

I' *OC>C*>

.

%

( IO"

6

M'-C

%

C*>

.% IO"

MWC

1MI

6

.MWC

8288 "us

I

O

'C

2

'%% controller

IO

W

C

2

-

%

(

.I

O

W

C

-,

I().'

8683 MPU

.

*

%

MC% ,P-%

-%


60/68

- ,

'

.*%

.6B.1;/

.13,4B

.1


61/68

Microprocessors and Microcontrollers/Architecture of

Microprocessors

Lecture

Notes

tatus Inputs

CPU Cycles 8288

2 1 6 Command

6

Interrupt.ckno#ledge

6 6 I.

6 6 1 'ead I,O Port

IO

'C

6 1 6 Write I,O Port

IOW

C/

.IO

WC

6 1 1 0alt

o

ne

1 6 6 Instruction etc$M'-C

1 6 1 'ead Memory

M'

-C

1 Write Memory1 6

MW

)C/

.M

WC

1 11

Passive

on

e

"us tatus Codes

The 2 produces one or two of these eight command signals for each bus c)cles. 3or

instance* when the 9( outputs the code 525159 e+uals 991* it indicates that an I()

read

cycle is to be performed.!n the code 111 is output b) the 9(* it is signaling that no bus actiit) is to tae place.

The control outputs produced b) the 2 are @,N* @T/ and AL,. These signals

proide the same functions as those described for the minimum s)stem mode. This setof bus commands and control signals is compatible with the Multibus and industr)

standard for interfacing microprocessor s)stems.

he output of #*#+ are !us ar!itration signals:

!us busy %605P&*common bus re"uest %-6U&*bus priority out %6>?&*buspriority in %6>N&*bus re"uest %6,U& andbus clock %6-L4&.

The) correspond to the bus e$change signals of the Multibus and are used to loc

other processor off the s)stem bus during the e$ecution of an instruction b) the 9(.!n this wa) the processor can be assured of uninterrupted access to common

s)stem resources such asglo!al memory.

Gueue tatus ignals: Two new signals that are produced b) the 9( in the ma$imum"


62/68

mode s)stem are +ueue status outputs U59 and U51. Together the) form a 2"bit +ueue

status code* U51U59.

3ollowing table shows the four different +ueue status.


M1/71/8une 9#/


63/68

Microprocessors and Microcontrollers/Architecture of MicroprocessorsLecture

Notes

G1

G

6 Gueue tatus

6

(lo#) 6

o Operation? -uring t$e last clock cycle/ not$ing #as

taken from t$e Hueue?

6 1

irst "yte? $e &yte taken from t$e Hueue #as t$e first

&yte

of t$e instruction?

1

($ig$)6

Gueue %mpty? $e Hueue $as &een reinitialiJed as a result

of t$e e9ecution of a transfer instruction?

1 1u&seHuent "yte? $e &yte taken from t$e Hueue #as a

su&seHuent &yte of t$e instruction?

Uueue status codes*ocal "us Control ignal F 'eHuest , 7rant ignals: !n a ma$imum mode configuration*

the minimum mode C?L@* CL@A interface is also changed. These two are replaced b)

re+uest/grant lines U/ FT9 and U/ FT1* respectiel). The) proide a

prioritied bus access mechanism for accessing the local bus.

Internal 'egisters of 8683The 9( has four groups of the user accessible internal registers. The) are theinstruction pointer* four data registers* four pointer and inde$ register* four segment

registers.

The 9( has a total of fourteen 1("bit registers including a 1( bit register called

the status register* with E of bits implemented for status and control flags.Most of the registers contain data/instruction offsets within (# 46 memor) segment.

There are four different (# 46 segments for instructions* stac* data and e$tra data. To

specif) where in 1 M6 of processor memor) these # segments are located theprocessor uses four segment registers:

Code segment%-5& is a 1("bit register containing address of (# 46 segment with

processor instructions. The processor uses -5 segment for all accesses to instructionsreferenced b) instruction pointer %!>& register. -5 register cannot be changed directl).

The -5 register is automaticall) updated during far Dump* far call and far return

instructions.

tack segment%55& is a 1("bit register containing address of (#46 segment withprogram stac. 6) default* the processor assumes that all data referenced b) the stac

pointer %5>& and base pointer %6>& registers is located in the stac segment. 55

register can be changed directl) using >?> instruction.-ata segment%@5& is a 1("bit register containing address of (#46 segment with

program data. 6) default* the processor assumes that all data referenced b) general

registers %AB* 6B* -B* @B& and inde$ register %5!* @!& is located in the data

segment. @5 register can be changed directl) using >?> and L@5 instructions.


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.ccumulatorregister consists of two "bit registers AL and AC* which can be

combined together and used as a 1("bit register AB. AL in this case contains the low"order b)te of the word* and AC contains the high"order b)te. Accumulator can be

used for !/? operations and string manipulation.M. 4rishna 4umar/!!5c. 6angalore

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"aseregister consists of two "bit registers 6L and 6C* which can be combined together

and used as a 1(" bit register 6B. 6L in this case contains the low"order b)te of the word*

and 6C contains the high"order b)te. 6B register usuall) contains a data pointer used for

based* based inde$ed or register indirect addressing.

Countregister consists of two "bit registers -L and -C* which can be combined

together and used as a 1("bit register -B. =hen combined* -L register contains the low" order b)te of the word* and -C contains the high "order b)te. -ount register can be

used in Loop* shift/rotate instructions and as a counter in string manipulation*.

-ataregister consists of two "bit registers @L and @C* which can be combined

together and used as a 1("bit register @B. =hen combined* @L register contains the low"order b)te of the word* and @C contains the high "order b)te. @ata register can be used

as a port number in !/? operations. !n integer 2" bit multipl) and diide instruction the

@B register contains high"order word of the initial or resulting number.

$e follo#ing registers are &ot$ general and inde9 registers:

tack Pointer%5>& is a 1("bit register pointing to program stac.

"ase Pointer%6>& is a 1("bit register pointing to data in stac segment. 6> register is

usuall) used for based* based inde$ed or register indirect addressing.ource Inde9%5!& is a 1(" bit register. 5! is used for inde$ed* based inde$ed and register

indirect addressing* as well as a source data address in string manipulation instructions.

-estination Inde9%@!& is a 1("bit register. @! is used for inde$ed* based inde$ed andregister indirect addressing* as well as a destination data address in string manipulation

instructions.

Ot$er registers:

Instruction Pointer%!>& is a 1("bit register.

lagsis a 1("bit register containing E one bit flags.

Overflo# lag%?3& " set if the result is too large positie number* or is too smallnegatie number to fit into destination operand.

-irection lag%@3& " if set then string manipulation instructions will auto"decrement inde$ registers. !f cleared then the inde$ registers will be auto"

incremented.InterruptBena&le lag%!3& " setting this bit enables masable interrupts.

ingleBstep lag%T3& " if set then single"step interrupt will occur after the ne$t

instruction.ign lag%53& " set if the most significant bit of the result is set.

Dero lag%3& " set if the result is ero.

.u9iliary carry lag%A3& " set if there was a carr) from or borrow to bits 9" in the ALregister.

Parity lag%>3& " set if parit) %the number of ;1; bits& in the low"order b)te of the

result is een.Carry lag%-3& " set if there was a carr) from or borrow to the most significant bit

during last result calculation.

.ddressing Modes

Implied" the data alue/data address is implicitl) associated with the instruction.

'egister" references the data in a register or in a register pair.Immediate" the data is proided in the instruction.

-irect" the instruction operand specifies the memor) address where data is located.


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'egister indirect" instruction specifies a register containing an address* where data is

located. This addressing mode wors with 5!* @!* 6B and 6> registers.

"ased:" "bit or 1("bit instruction operand is added to the contents of a base

register %6B or 6>&* the resulting alue is a pointer to location where data resides.

Inde9ed:" "bit or 1("bit instruction operand is added to the contents of an inde$ register

%5! or @!&* the resulting alue is a pointer to location where data resides"ased Inde9ed: " the contents of a base register %6B or 6>& is added to the contents of

an inde$ register %5! or @!&* the resulting alue is a pointer to location where data resides."ased Inde9ed #it$ displacement:" "bit or 1("bit instruction operand is added to the

contents of a base register %6B or 6>& and inde$ register %5! or @!&* the resulting alue is

a pointer to location where data resides.

Memory >rogram* data and stac memories occup) the same memor) space. As the

most of the processor instructions use 1("bit pointers the processor can effectiel)

address onl) (# 46 of memor).

To access memor) outside of (# 46 the ->0 uses special segment registers to specif)where the code* stac and data (# 46 segments are positioned within 1 M6 of memor)

%see the ;egisters; section below&.1("bit pointers and data are storedas: address: low"order b)te

address1: high"order b)te

Program memory" program can be located an)where in memor). 8ump and callinstructions can be used for short Dumps within currentl) selected (# 46 code

segment* as well as for far Dumps an)where within 1 M6 of memor).

All conditional Dump instructions can be used to Dump within appro$imatel) 12 to" 12 b)tes from current instruction.

-ata memory" the processor can access data in an) one out of # aailable segments*which limits the sie of accessible memor) to 2'( 46 %if all four segments point to

different (# 46 blocs&.Accessing data from the @ata* -ode* 5tac or ,$tra segments can be usuall) done b)

prefi$ing instructions with the @5:* -5:* 55: or ,5: %some registers and instructions b)default ma) use the ,5 or 55 segments instead of @5 segment&.

=ord data can be located at odd or een b)te boundaries. The processor uses two

memor) accesses to read 1("bit word located at odd b)te boundaries. eading worddata from een b)te boundaries re+uires onl) one memor) access.

tack memorycan be placed an)where in memor). The stac can be located at odd

memor) addresses* but it is not recommended for performance reasons %see ;@ataMemor); aboe&.

'eserved locations:

9999h " 933h are resered for interrupt ectors. ,ach interrupt ector is a 2"bitpointer in format segment: offset.

33339h " 33333h " after ,5,T the processor alwa)s starts program e$ecution at the

33339h address.

Interrupts

The processor has the following interrupts:


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I'is a masable hardware interrupt. The interrupt can be enabled/disabled using

5T!/-L! instructions or using more complicated method of updating the 3LAF5 register

with the help of the >?>3 instruction.

=hen an interrupt occurs* the processor stores 3LAF5 register into stac* disables

further interrupts* fetches from the bus one b)te representing interrupt t)pe* and Dumps to

interrupt processing routine address of which is stored in location # O Vinterrupt t)peH.!nterrupt processing routine should return with the !,T instruction.

MIis a non"masable interrupt. !nterrupt is processed in the same wa) as the !NT

interrupt. !nterrupt t)pe of the NM! is 2* i.e. the address of the NM! processing routine isstored in location 999h. This interrupt has higher priorit) then the masable interrupt.

oft#are interruptscan be caused b):

!NT instruction " breapoint interrupt. This is a t)pe interrupt.!NT Vinterrupt numberH instruction " an) one interrupt from aailable 2'( interrupts.

!NT? instruction " interrupt on oerflow

5ingle"step interrupt " generated if the T3 flag is set. This is a t)pe 1 interrupt. =hen the->0 processes this interrupt it clears T3 flag before calling the interrupt processing

routine.Processor e9ceptions: @iide ,rror %T)pe 9&* 0nused ?pcode %t)pe (& and ,scape

opcode %t)pe &.5oftware interrupt processing is the same as for the hardware interrupts.


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adderessing mode and data transfer schemas 8085.rtf

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