ads1219 4-channel, 1-ksps, 24-bit, delta-sigma adc with ...sda scl a1 a0 reset drdy 3.3 v 0.1 pf 3.3...

ReferenceMUX

AIN0

AIN1

AIN2

AIN3

AVDD

AGND DGND

REFP REFN

2.048-V Reference

DVDD

Digital Filterand

I2C Interface

Low Drift Oscillator

ADS1219

SDA

SCL

A1

A0

RESET

DRDY

3.3 V

0.1 PF

3.3 V

0.1 PF

CF3

RF3

0 V to 2 V

RShunt

CF2

RF2

Load

3.3 V

+

-

RREF

Thermistor CF0

RF0

3.3 V

0.1 PF

3.3 V

3.3 V

INA180

0.1 PF

24-bitû��ADC

Gain1 or 4

Buffers

MUX

Product

Folder

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Now

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Documents

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ReferenceDesign

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS1219SBAS924A –JULY 2018–REVISED NOVEMBER 2018

ADS1219 4-Channel, 1-kSPS, 24-Bit, Delta-Sigma ADC With I2C Interface

1

1 Features1• Easy to Use With Only One Register to Program• Current Consumption as Low as 315 µA (typ)• Wide Supply Range: 2.3 V to 5.5 V• Rail-to-Rail Input Buffers to Achieve High Input

Impedance• Programmable Gains: 1 and 4• Programmable Data Rates: Up to 1 kSPS• Up to 20 Bits Effective Resolution• Simultaneous 50-Hz and 60-Hz Rejection at

20 SPS With Single-Cycle Settling Digital Filter• Two Differential or Four Single-Ended Inputs• Internal 2.048-V Reference: 5 ppm/°C (typ) Drift• Internal 2% Accurate Oscillator• I2C-Compatible Interface• Supported I2C Bus Speed Modes:

Standard-Mode, Fast-Mode, Fast-Mode Plus• 16 Pin-Configurable I2C Addresses• Package: 3.0-mm × 3.0-mm × 0.75-mm WQFN

2 Applications• Battery Test Equipment• Gas Detectors• Heat Meters• Optical Modules• Wearable Fitness and Activity Trackers

3 DescriptionThe ADS1219 is a precision, 24-bit, analog-to-digitalconverter (ADC) that includes all features necessaryto implement the most common system monitoringfunctions, such as supply voltage, current, andtemperature monitoring. The device features twodifferential or four single-ended inputs through aflexible input multiplexer (MUX), rail-to-rail inputbuffers, a programmable gain stage, a voltagereference, and an oscillator.

The device includes buffers that allow high-impedance sources to be directly connected to thedevice. A gain stage follows the buffers whichprovides selectable gains of 1 and 4. The ADS1219can perform conversions at data rates as high as1000 samples per second (SPS) with single-cyclesettling. At 20 SPS, the digital filter offerssimultaneous 50-Hz and 60-Hz rejection for noisyindustrial applications.

The ADS1219 features a 2-wire, I2C-compatibleinterface that supports I2C bus speeds up to 1 Mbps.16 different I2C addresses can be selected for thedevice via two address pins.

The ADS1219 is offered in a leadless 16-pin WQFNor a 16-pin TSSOP package and is specified over atemperature range of –40°C to +125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

ADS1219WQFN (16) 3.00 mm × 3.00 mmTSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Voltage, Current, and Temperature Monitoring Application

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Product Folder Links: ADS1219

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information .................................................. 56.5 Electrical Characteristics........................................... 56.6 I2C Timing Requirements.......................................... 76.7 I2C Switching Characteristics.................................... 86.8 Typical Characteristics ............................................ 10

7 Parameter Measurement Information ................ 147.1 Noise Performance ................................................. 14

8 Detailed Description ............................................ 158.1 Overview ................................................................. 158.2 Functional Block Diagram ....................................... 158.3 Feature Description................................................. 168.4 Device Functional Modes........................................ 20

8.5 Programming........................................................... 228.6 Register Map........................................................... 27

9 Application and Implementation ........................ 309.1 Application Information............................................ 309.2 Typical Application .................................................. 34

10 Power Supply Recommendations ..................... 3710.1 Power-Supply Sequencing.................................... 3710.2 Power-Supply Decoupling..................................... 37

11 Layout................................................................... 3811.1 Layout Guidelines ................................................. 3811.2 Layout Example .................................................... 39

12 Device and Documentation Support ................. 4012.1 Device Support...................................................... 4012.2 Documentation Support ........................................ 4012.3 Receiving Notification of Documentation Updates 4012.4 Community Resources.......................................... 4012.5 Trademarks ........................................................... 4012.6 Electrostatic Discharge Caution............................ 4012.7 Glossary ................................................................ 40

13 Mechanical, Packaging, and OrderableInformation ........................................................... 40

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (July 2018) to Revision A Page

• Changed Internal Voltage Reference, Accuracy parameter: added TSSOP package to test conditions of first rowand added second row to Internal Voltage Reference, Accuracy parameter......................................................................... 5

• Added TSSOP package to conditions of Internal Reference Voltage Histogram figure ...................................................... 11• Changed 976.56 nV to 61.04 nV in LSB SIZE column of Full-Scale Range and LSB Size table........................................ 17


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16A

15

AIN

2

1RESET 12 DRDY

15A

06

RE

FN

2DGND 11 DVDD

14S

CL

7R

EF

P

3AGND 10 AVDD

13S

DA

8A

IN1

4AIN3 9 AIN0

Not to scale

Thermal

Pad

1A0 16 SCL

2A1 15 SDA

3RESET 14 DRDY

4DGND 13 DVDD

5AGND 12 AVDD

6AIN3 11 AIN0

7AIN2 10 AIN1

8REFN 9 REFP

Not to scale

3

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5 Pin Configuration and Functions

RTE Package16-Pin WQFN

Top View

PW Package16-Pin TSSOP

Top View

(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.

Pin FunctionsPIN

ANALOG OR DIGITALINPUT/OUTPUT DESCRIPTION (1)NAME

NO.

RTE PW

A0 15 1 Digital input I2C slave address select pin 0. See the I2C Address section for details.

A1 16 2 Digital input I2C slave address select pin 1. See the I2C Address section for details.

AIN0 9 11 Analog input Analog input 0




AGND 3 5 Analog supply Negative analog power supply

AVDD 10 12 Analog supply Positive analog power supply. Connect a 100-nF (or larger) capacitor to AGND.

DGND 2 4 Digital supply Digital ground

DRDY 12 14 Digital output Data ready, active low. Connect to DVDD using a pullup resistor.

DVDD 11 13 Digital supply Positive digital power supply. Connect a 100-nF (or larger) capacitor to DGND.

REFN 6 8 Analog input Negative reference input

REFP 7 9 Analog input Positive reference input

RESET 1 3 Digital input Reset, active low

SCL 14 16 Digital input Serial clock input. Connect to DVDD using a pullup resistor.

SDA 13 15 Digital input/output Serial data input and output. Connect to DVDD using a pullup resistor.

Thermal pad Pad — — Thermal power pad. Connect to AGND.


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4




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratingssee (1)

MIN MAX UNIT

Power-supply voltageAVDD to AGND –0.3 7

VDVDD to DGND –0.3 7AGND to DGND –2.8 0.3

Analog input voltage AIN0, AIN1, AIN2, AIN3, REFP, REFN AGND – 0.3 AVDD + 0.3 VDigital input voltage SCL, SDA, A0, A1, DRDY, RESET DGND – 0.3 7 VInput current Continuous, any pin except power-supply pins –10 10 mA

TemperatureJunction, TJ 150

°CStorage, Tstg –60 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750

(1) AINx denotes one of the four available analog inputs. AINP and AINN denote the positive and negative inputs selected by the MUX.(2) Excluding the effects of offset and gain error.

6.3 Recommended Operating Conditionsover operating ambient temperature range (unless otherwise noted)

MIN NOM MAX UNIT

POWER SUPPLY

Analog power supplyAVDD to AGND 2.3 5.5

VAGND to DGND –0.1 0 0.1

Digital power supply DVDD to DGND 2.3 5.5 V

ANALOG INPUTS (1)

V(AINx) Absolute input voltage Gain = 1 and 4 AGND – 0.1 AVDD + 0.1 V

VIN Differential input voltage VIN = VAINP – VAINN(2) –VREF / Gain VREF / Gain V

VOLTAGE REFERENCE INPUTS

VREF Differential reference input voltage VREF = V(REFP) – V(REFN) 0.75 2.5 AVDD V

V(REFN) Absolute negative reference voltage AGND – 0.1 V(REFP) – 0.75 V

V(REFP) Absolute positive reference voltage V(REFN) + 0.75 AVDD + 0.1 V

DIGITAL INPUTS

Input voltage

SCL, SDA, A0, A1, DRDY,2.3 V ≤ DVDD < 3.0 V DGND DVDD + 0.5

VSCL, SDA, A0, A1, DRDY,3.0 V ≤ DVDD ≤ 5.5 V DGND 5.5

RESET DGND DVDD

TEMPERATURE RANGE

TA Operating ambient temperature –40 125 °C


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5




(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

6.4 Thermal Information

THERMAL METRIC (1)ADS1219

UNITWQFN (RTE) TSSOP (PW)16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 57.7 90.3 °C/WRθJC(top) Junction-to-case (top) thermal resistance 29.0 31.7 °C/WRθJB Junction-to-board thermal resistance 19.9 41.8 °C/WψJT Junction-to-top characterization parameter 0.3 1.8 °C/WψJB Junction-to-board characterization parameter 19.8 41.2 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 11.8 N/A °C/W

(1) See the Noise Performance section for more information.(2) Excluding error of voltage reference.

6.5 Electrical Characteristicsminimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;all specifications are at AVDD = 2.3 V to 5.5 V, DVDD = 3.3 V, all data rates, all gains, and internal reference enabled (unlessotherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Absolute input current VIN = 0 V ±5 nA

Absolute input current drift VIN = 0 V 10 pA/°C

Differential input current VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain ±5 nA

Differential input current drift VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain 10 pA/°C

SYSTEM PERFORMANCE

Resolution (no missing codes) 24 Bits

DR Data rate 20, 90, 330, 1000 SPS

Noise (input-referred) (1) Gain = 1, DR = 20 SPS 5.04 µVRMS

INL Integral nonlinearity AVDD = 3.3 V, VCM = AVDD / 2, best fit –15 4 15 ppmFSR

VIO Input offset voltage Differential inputs ±4 µV

Offset drift vs temperature 0.02 0.1 µV/°C

Gain error (2) ±0.01%

Gain drift vs temperature (2) 0.3 2 ppm/°C

NMRR Normal-mode rejection ratio50 Hz ±1 Hz, DR = 20 SPS 78 88

dB60 Hz ±1 Hz, DR = 20 SPS 80 88

CMRR Common-mode rejection ratioAt dc, gain = 1, AVDD = 3.3 V 90 105

dBfCM = 50 Hz or 60 Hz, DR = 20 SPS, AVDD = 3.3 V 105 115

PSRR Power-supply rejection ratioAVDD at dc, VCM = AVDD / 2 85 105

dBDVDD at dc, VCM = AVDD / 2 95 115

INTERNAL VOLTAGE REFERENCE

VREF Reference voltage 2.048 V

AccuracyTA = 25°C, TSSOP package –0.15% ±0.01% 0.15%

TA = 25°C, WQFN package –0.25% ±0.04% 0.25%

Temperature drift 5 30 ppm/°C

Long-term drift 1000 hours 110 ppm

VOLTAGE REFERENCE INPUTS

Reference input current REFP = VREF, REFN = AGND, AVDD = 3.3 V ±10 nA

INTERNAL OSCILLATOR

fCLK Frequency 1.024 MHz

Accuracy –2% ±1% 2%


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6




Electrical Characteristics (continued)minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;all specifications are at AVDD = 2.3 V to 5.5 V, DVDD = 3.3 V, all data rates, all gains, and internal reference enabled (unlessotherwise noted)


DIGITAL INPUTS/OUTPUTS

VIL Logic input level, low DGND 0.3 DVDD V

VIH Logic input level, high

2.3 V ≤ DVDD < 3.0 V,SCL, SDA, A0, A1, DRDY 0.7 DVDD DVDD + 0.5

V3.0 V ≤ DVDD ≤ 5.5 V,SCL, SDA, A0, A1, DRDY 0.7 DVDD 5.5

RESET 0.7 DVDD DVDD

VhysHysteresis of Schmitt-triggerinputs Fast-mode, fast-mode plus 0.05 DVDD V

VOL Logic output level, low IOL = 3 mA DGND 0.15 0.4 V

IOL Low-level output current

VOL = 0.4 V, standard-mode, fast-mode 3

mAVOL = 0.4 V, fast-mode plus 20

VOL = 0.6 V, fast-mode 6

Ii Input current DGND + 0.1 V < VDigital Input < DVDD – 0.1 V –10 10 µA

Ci Capacitance Each pin 10 pF

ANALOG SUPPLY CURRENT (AVDD = 3.3 V, VIN = 0 V)

IAVDD Analog supply current

Power-down mode 0.1 3

µAConversion mode, internal reference selected 250

Conversion mode, external reference selected 310

DIGITAL SUPPLY CURRENT (DVDD = 3.3 V, All Data Rates, I2C Not Active)

IDVDD Digital supply currentPower-down mode 0.3 5

µAConversion mode 65 100

POWER DISSIPATION (AVDD = DVDD = 3.3 V, All Data Rates, VIN = 0 V, I2C Not Active)

PD Power dissipation Conversion mode, internal reference selected 1.04 mW


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7




6.6 I2C Timing Requirementsover operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullupresistor = 1 kΩ (unless otherwise noted)

MIN MAX UNIT

STANDARD-MODE

fSCL SCL clock frequency 0 100 kHz

tHD;STAHold time, (repeated) START condition.After this period, the first clock pulse is generated. 4 µs

tLOW Pulse duration, SCL low 4.7 µs

tHIGH Pulse duration, SCL high 4.0 µs

tSU;STA Setup time, repeated START condition 4.7 µs

tHD;DAT Hold time, data 0 µs

tSU;DAT Setup time, data 250 ns

tr Rise time, SCL, SDA 1000 ns

tf Fall time, SCL, SDA 250 ns

tSU;STO Setup time, STOP condition 4.0 µs

tBUF Bus free time, between STOP and START condition 4.7 µs

tVD;DAT Valid time, data 3.45 µs

tVD;ACK Valid time, acknowledge 3.45 µs

FAST-MODE


tHD;STAHold time, (repeated) START condition.After this period, the first clock pulse is generated. 0.6 µs






tr Rise time, SCL, SDA 20 300 ns

tf Fall time, SCL, SDA 20 · (DVDD / 5.5 V) 250 ns





tSP Pulse width of spikes that must be suppressed by the input filter 0 50 ns

FAST-MODE PLUS


tHD;STAHold time, (repeated) START condition.After this period, the first clock pulse is generated. 0.26 µs






tr Rise time, SCL, SDA 120 ns

tf Fall time, SCL, SDA Pullup resistor = 350 Ω 20 · (DVDD / 5.5 V) 120 ns





tSP Pulse duration of spikes that must be suppressed by the input filter 0 50 ns


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tBUF

tLOW

1 / fSCL

1st clock cycle

tSU;STA tHD;STA tSP

Sr9th clock

tVD;ACK

70%30%

tSU;STO

P S

70%30%

9th clocktHD;STA

S

70%

30%SDA

SCL

tf tr

tftHD;DAT

tr

tSU;DAT

70%30%

tVD;DAT

tHIGH

. . .cont.

. . .cont.

SDA

SCL

8




I2C Timing Requirements (continued)over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullupresistor = 1 kΩ (unless otherwise noted)

MIN MAX UNIT

(1) No delay time is required when using the RESET command as long as all I2C timing requirements for the (repeated) START and STOPconditions are met.

(2) See the Timeout section for more information.tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz.

RESET PIN

tw(RSL) Pulse duration, RESET low 250 ns

td(RSSTA) Delay time, START condition after RESET rising edge (1) 100 ns

DRDY PIN

td(DRSTA) Delay time, START condition after DRDY falling edge 0 ns

TIMEOUT

Timeout (2) 14000 tMOD

(1) tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz.

6.7 I2C Switching Characteristicsover operating ambient temperature range, DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup resistor =1 kΩ (unless otherwise noted)


tw(DRH) Pulse duration, DRDY high (1) 2 tMOD

tp(RDDR)Propagation delay time, RDATA command latched toDRDY rising edge 2 tMOD

Figure 1. I2C Timing Requirements


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DRDY

tw(DRH)

S

SDA

SCL

W

STARTCondition

ADDRESSRDATA

CommandACK

P

STOPCondition

ACK

td(DRSTA) ttp(RDDR)t

RESET

ttd(RSSTA)t

tw(RSL)

S

SDA

SCL

STARTCondition

ADDRESS

9




Figure 2. RESET Pin Timing Requirements

Figure 3. DRDY Pin Timing Requirements and Switching Characteristics


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Temperature (qC)

Offs

et V

olta

ge (P

V)

-50 -25 0 25 50 75 100 1250

2

4

6

8

10Gain = 1Gain = 4

Offset Voltage (�V)

Num

ber

of O

ccur

renc

es

0

20

40

60

80

-10 -5 0 5 10 15 20 25 30 35 40

VIN (% of FS)

INL

(ppm

of F

SR

)

-100 -80 -60 -40 -20 0 20 40 60 80 100-15

-10

-5

0

5

10

15

VIN (% of FS)

INL

(ppm

of F

SR

)

-100 -80 -60 -40 -20 0 20 40 60 80 100-15

-10

-5

0

5

10

15

V(AINx) (V)

Abs

olut

e In

put C

urre

nt (

nA)

0 0.5 1 1.5 2 2.5 3 3.5-15

-10

-5

0

5

10

15

-40qC 25qC 85qC 125qC

VIN (V)

Diff

eren

tial I

nput

Cur

rent

(nA

)

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5-20

-15

-10

-5

0

5

10

15

20

-40qC 25qC 85qC 125qC

10




6.8 Typical Characteristicsat TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)

VIN = 0 V

Figure 4. Absolute Input current vs Absolute Input Voltage

VCM = 1.65 V

Figure 5. Differential Input Current vsDifferential Input Voltage

External reference, best fit

Figure 6. INL vs Differential Input Voltage

Internal reference, best fit

Figure 7. INL vs Differential Input Voltage

AVDD = 5 V, gain = 1, 110 samples

Figure 8. Offset Voltage Histogram Figure 9. Input Offset Voltage vs Temperature


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Temperature (qC)

Inte

rnal

Ref

eren

ce V

olta

ge (

V)

-50 -25 0 25 50 75 100 1252.045

2.046

2.047

2.048

2.049

2.05

2.051AVDD = 3.3 VAVDD = 5.0 V

AVDD (V)

Inte

rnal

Ref

eren

ce V

olta

ge (

V)

2 2.5 3 3.5 4 4.5 5 5.52.0478

2.048

2.0482

2.0484

2.0486

Internal Reference Voltage (V)

Num

ber

of O

ccur

renc

es

0

500

1000

1500

2000

2.04

7

2.04

72

2.04

74

2.04

76

2.04

78

2.04

8

2.04

82

2.04

84

2.04

86

Temperature (qC)

CM

RR

(dB

)

-50 -25 0 25 50 75 100 125100

105

110

115

120

125

Gain Error (%)

Num

ber

of O

ccur

renc

es

0

50

100

150

200

250

300-0

.03

-0.0

2

-0.0

1 0

0.01

0.02

0.03

0.04

0.05

Temperature (qC)

Gai

n E

rror

(%

)

-50 -25 0 25 50 75 100 125-0.03

-0.025

-0.02

-0.015

-0.01

-0.005

0

Gain = 1Gain = 4

11




Typical Characteristics (continued)at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)

Gain = 1, 620 samples,excluding error of voltage reference

Figure 10. Gain Error Histogram

Excluding error of voltage reference

Figure 11. Gain Error vs Temperature

Figure 12. DC CMRR vs Temperature

5940 samples, TSSOP package

Figure 13. Internal Reference Voltage Histogram

Figure 14. Internal Reference Voltage vs Temperature Figure 15. Internal Reference Voltage vs AVDD


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Sinking Current (mA)

Dig

ital P

in O

utpu

t Vol

tage

(V

)

0 2 4 6 8 10 12 14 16 18 200

0.1

0.2

0.3

0.4

0.5�40°C25°C125°C

Temperature (qC)

AV

DD

Cur

rent

(P

A)

-50 -25 0 25 50 75 100 1250

0.2

0.4

0.6

0.8

1

Temperature (qC)

Inte

rnal

Osc

illat

or F

requ

ency

(M

Hz)

-50 -25 0 25 50 75 100 1251.02

1.021

1.022

1.023

1.024

1.025

1.026

DVDD (V)

Inte

rnal

Osc

illat

or F

requ

ency

(M

Hz)

2 2.5 3 3.5 4 4.5 5 5.51.02

1.021

1.022

1.023

1.024

1.025

1.026

Internal Oscillator Frequency (MHz)

Num

ber

of O

ccur

renc

es

0

50

100

150

200

250

300

1.01

6

1.01

8

1.02

1.02

2

1.02

4

1.02

6

1.02

8

1.03

1.03

2

Temperature (qC)

Ref

eren

ce In

put C

urre

nt (

nA)

-50 -25 0 25 50 75 100 125-20

-15

-10

-5

0VREF = 1 VVREF = 1.5 V

VREF = 2 VVREF = 2.5 V

12





Figure 16. External Reference Input Current vs Temperature Figure 17. Internal Oscillator Frequency Histogram

Figure 18. Internal Oscillator Frequency vs Temperature Figure 19. Internal Oscillator Frequency vs DVDD

DVDD = 3.3 V

Figure 20. Digital Pin Output Voltage vs Sinking Current

Power-down mode

Figure 21. Analog Supply Current vs Temperature


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DVDD (V)

DV

DD

Cur

rent

(P

A)

2 2.5 3 3.5 4 4.5 5 5.550

60

70

80

90

100

Temperature (qC)

DV

DD

Cur

rent

(P

A)

-50 -25 0 25 50 75 100 1250

0.5

1

1.5

2

Temperature (qC)

DV

DD

Cur

rent

(P

A)

-50 -25 0 25 50 75 100 12550

60

70

80

90

100

Temperature (qC)

AV

DD

Cur

rent

(P

A)

-50 -25 0 25 50 75 100 1250

100

200

300

400

500

600

AVDD (V)

AV

DD

Cur

rent

(P

A)

2 2.5 3 3.5 4 4.5 5 5.50

100

200

300

400

500

600

13





Conversion mode

Figure 22. Analog Supply Current vs Temperature

Conversion mode

Figure 23. Analog Supply Current vs AVDD

Power-down mode

Figure 24. Digital Supply Current vs Temperature

Conversion mode

Figure 25. Digital Supply Current vs Temperature

Conversion mode

Figure 26. Digital Supply Current vs DVDD


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14




7 Parameter Measurement Information

7.1 Noise PerformanceDelta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The inputsignal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered anddecimated in the digital domain to yield a conversion result at the respective output data rate. The ratio betweenmodulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thusreducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator areaveraged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which isparticularly useful when measuring low-level signals.

Table 1 and Table 2 summarize the device noise performance. Data are representative of typical noiseperformance at TA = 25°C using the internal 2.048-V reference. Data shown are the result of averaging readingsfrom a single device over a time period of approximately 0.75 seconds and are measured with the inputsinternally shorted together. Table 1 lists the input-referred noise in units of μVRMS for the conditions shown.Values in µVPP are shown in parenthesis. Table 2 lists the corresponding data in effective resolution calculatedfrom μVRMS values using Equation 1. Noise-free resolution calculated from peak-to-peak noise values usingEquation 2 are shown in parenthesis.

The input-referred noise only changes marginally when using an external low-noise reference, such as theREF5020. Use Equation 1 and Equation 2 to calculate effective resolution numbers and noise-free resolutionwhen using a reference voltage other than 2.048 V:

Effective Resolution = ln [2 · VREF / (Gain · VRMS-Noise)] / ln(2) (1)Noise-Free Resolution = ln [2 · VREF / (Gain · VPP-Noise)] / ln(2) (2)

Table 1. Noise in μVRMS (μVPP)at AVDD = 3.3 V and Internal VREF = 2.048 V

DATA RATE(SPS)

GAIN1 4

20 5.04 (19.71) 1.57 (5.68)90 8.75 (42.59) 2.13 (10.52)330 18.58 (106.06) 4.54 (26.30)1000 36.98 (221.61) 9.27 (55.07)

Table 2. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)at AVDD = 3.3 V and Internal VREF = 2.048 V

DATA RATE(SPS)

GAIN1 4

20 19.63 (17.66) 19.32 (17.46)90 18.84 (16.55) 18.87 (16.57)330 17.75 (15.24) 17.78 (15.25)1000 16.76 (14.17) 16.75 (14.18)


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http://www.ti.com/product/ref5020

ReferenceMUXAIN0

AIN1

AIN2

AIN3

AVDD

AGND DGND

REFP REFN

2.048-V Reference

MUX

DVDD

24-bitû��ADC

Digital Filterand

I2C Interface


ADS1219

SDA

SCL

A1

A0

RESET

DRDY

Gain1 or 4

Buffers

15




8 Detailed Description

8.1 OverviewThe ADS1219 is a small, low-power, 24-bit, ΔΣ ADC. In addition to the ΔΣ ADC core and single-cycle settlingdigital filter, the device offers a multiplexer (MUX), rail-to-rail input buffers, a programmable gain stage, aninternal 2.048-V voltage reference, and a clock oscillator. All of these features are intended to reduce therequired external circuitry in typical voltage, current, and temperature monitoring applications. The device is fullyconfigured through a single register and controlled by six commands through an I2C-compatible interface. TheFunctional Block Diagram section shows the device functional block diagram.

The MUX selects the positive (AINP) and negative (AINN) signals that feed into the rail-to-rail input buffers. A gainstage with selectable gains of 1 and 4 follows the input buffers. The 24-bit ADC measures the differential signalprovided after the gain stage. The converter core consists of a differential, switched-capacitor, ΔΣ modulatorfollowed by a digital filter. The digital filter receives a high-speed bitstream from the modulator and outputs acode proportional to the input voltage. This architecture results in a very strong attenuation of any common-modesignal.

The device has two available conversion modes: single-shot conversion and continuous conversion mode. Insingle-shot conversion mode, the ADC performs one conversion of the input signal upon request and stores thevalue in an internal data buffer. The device then enters a low-power state to save power. Single-shot conversionmode is intended to provide significant power savings in systems that require only periodic conversions, or whenthere are long idle periods between conversions. In continuous conversion mode, the ADC automatically beginsa conversion of the input signal as soon as the previous conversion is completed. New data are available at theprogrammed data rate. Data can be read at any time without concern of data corruption and always reflect themost recently completed conversion.

8.2 Functional Block Diagram


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To ADC

AINP

AINN

AIN0

AIN1

AGND

AVDD AGND

AVDD AGND

AIN2

AIN3

AVDD AGND

AVDD AGND

AVDD / 2

Rail-to RailBuffers

16




8.3 Feature Description

8.3.1 MultiplexerFigure 27 shows the flexible input multiplexer of the device. Either four single-ended signals, two differentialsignals, or a combination of two single-ended signals and one differential signal can be measured. The positive(AINP) and negative (AINN) inputs selected for measurement are configured by three bits (MUX[2:0]) in theconfiguration register. When single-ended signals need to be measured, the negative ADC input (AINN) caninternally be connected to AGND by a switch within the multiplexer.

Figure 27. Analog Input Multiplexer

Electrostatic discharge (ESD) diodes to AVDD and AGND protect the inputs. The absolute voltage on any inputmust stay within the range provided by Equation 3 to prevent the ESD diodes from turning on:

AGND – 0.3 V < V(AINx) < AVDD + 0.3 V (3)

If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes orseries resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratingstable). Overdriving an unused input on the device can affect conversions taking place on other input pins.


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17




Feature Description (continued)8.3.2 Rail-to-Rail Input Buffers and Programmable Gain StageThe ADS1219 integrates two rail-to-rail input buffers to ensure that the effect on the input loading resulting fromthe capacitor charging and discharging of the ΔΣ ADC is minimal. The buffers therefore help to increase the inputimpedance of the device. See the Electrical Characteristics table for the typical values of absolute input currents(current flowing into or out of each input) and differential input currents (difference in absolute current betweenthe positive and negative input).

The usable absolute input voltage range of the buffers is (AGND – 0.1 V ≤ VAINP, VAINN ≤ AVDD + 0.1 V). VINdenotes the differential input voltage VIN = VAINP – VAINN between the buffer inputs.

A programmable gain stage follows the buffers. The GAIN bit in the configuration register is used to configure thegain to either 1 or 4.

Equation 4 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gainsetting and the reference voltage used:

FSR = ±VREF / Gain (4)

Table 3 shows the corresponding full-scale ranges and least significant bit (LSB) sizes when using the internal2.048-V reference.

Table 3. Full-Scale Range and LSB SizeGAIN SETTING FSR LSB SIZE

1 ±2.048 V 244.14 nV4 ±0.512 V 61.04 nV

In order to measure single-ended signals that are referenced to AGND (AINP = VIN, AINN = AGND), connect oneof the analog inputs to AGND externally or use the internal AGND connection of the multiplexer (MUX[2:0]settings 011 through 110). The device only uses the code range that represents positive differential voltageswhen measuring single-ended signals. See the Data Format section for more details.

For signal sources with high output impedance, external buffering may still be necessary. Active buffers canintroduce noise as well as offset and gain errors. Consider all of these factors in high-accuracy applications.

8.3.3 Voltage ReferenceThe device offers an integrated, low-drift, 2.048-V reference. For applications that require a different referencevoltage value or a ratiometric measurement approach, the device offers a differential reference input pair (REFPand REFN).

The reference source is selected by the VREF bit in the configuration register. By default, the internal referenceis selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when comingout of power-down mode, or when switching from the external reference source to the internal reference.

The differential reference input allows freedom in the reference common-mode voltage. The reference inputs areinternally buffered to increase input impedance. Therefore, additional reference buffers are usually not requiredwhen using an external reference. When used in ratiometric applications, the reference inputs do not load theexternal circuitry; however, the analog supply current increases when using an external reference because thereference buffers are enabled.

In most cases the conversion result is directly proportional to the stability of the reference source. Any noise anddrift of the voltage reference is reflected in the conversion result.

8.3.4 Modulator and Internal OscillatorA ΔΣ modulator is used in the ADS1219 to convert the differential signal provided by the gain stage into a pulsecode modulated (PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 4 =256 kHz, where fCLK is provided by the internal 1.024-MHz oscillator.


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Frequency (kHz)

Mag

nitu

de (

dB)

0 1 2 3 4 5 6 7 8 9 10-80

-60

-40

-20

0

D008

Frequency (Hz)

Mag

nitu

de (

dB)

0 100 200 300 400 500 600 700 800 900 1000-60

-50

-40

-30

-20

-10

0

D004Frequency (Hz)

Mag

nitu

de (

dB)

0 200 400 600 800 1000 1200 1400 1600 1800 2000-60

-50

-40

-30

-20

-10

0

D006

Frequency (Hz)

Mag

nitu

de (

dB)

0 20 40 60 80 100 120 140 160 180 200-120

-100

-80

-60

-40

-20

0

D002Frequency (Hz)

Mag

nitu

de (

dB)

46 48 50 52 54 56 58 60 62 64-120

-100

-80

-60

-40

-20

0

D001

18




8.3.5 Digital FilterThe device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering anddecimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for thedifferent data rates and always settles within a single cycle. The frequency responses of the digital filter areshown in Figure 28 to Figure 32 for different output data rates. The filter notches and output data rate scaleproportionally with the clock frequency. The internal oscillator can vary over temperature as specified in theElectrical Characteristics table. The data rate or conversion time, respectively, and consequently also the filternotches vary proportionally.

Figure 28. Filter Response(DR = 20 SPS)

Figure 29. Detailed View of the Filter Response(DR = 20 SPS)



Figure 32. Filter Response(DR = 1 kSPS)


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19




(1) The first conversion starts 28.5 · tCLK after the START/SYNC command is latched. The times listed in this table do not include that time.(2) tCLK = 1 / fCLK. fCLK = 1.024 MHz.

8.3.6 Conversion TimesTable 4 shows the actual conversion times for each data rate setting. The values provided are in terms of tCLKcycles and in milliseconds.

Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge.The first conversion starts 28.5 · tCLK after the START/SYNC command is latched.

Single-shot conversion mode data rates are timed from when the START/SYNC command is latched to theDRDY falling edge and rounded to the next tCLK.

Commands are latched on the eighth falling edge of SCL in the command byte.

Table 4. Conversion Times

NOMINALDATA RATE

(SPS)

–3-dBBANDWIDTH

(Hz)

CONTINUOUS CONVERSION MODE (1) SINGLE-SHOT CONVERSION MODEACTUAL

CONVERSION TIME(tCLK) (2)

ACTUALCONVERSION TIME

(ms)


(tCLK) (2)


(ms)20 13.1 51192 49.99 51213 50.0190 39.6 11532 11.26 11557 11.29330 150.1 3116 3.04 3141 3.071000 483.8 1036 1.01 1061 1.04

Although the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does notaffect the 50-Hz or 60-Hz rejection. The conversion time and filter notches vary by the amount specified in theElectrical Characteristics table for oscillator accuracy.

8.3.7 Offset CalibrationThe ADS1219 does not offer any self-calibration options. However the internal multiplexer offers the option toshort both inputs (AINP and AINN) to mid-supply AVDD / 2. This option can be used to measure and calibrate thedevice offset voltage by storing the result of the shorted input voltage reading in a microcontroller andconsequently subtracting the result from each following reading. Take multiple readings with the inputs shortedand average the result to reduce the effect of noise.


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Power-On Reset orRESET pin high or RESET command(1)

Low-power state

Reset device to default settings

START/SYNCCommand?

ConversionMode

Start newconversion

1 = Continuous conversion mode

0 = Single-Shotconversion mode

No

Yes

POWERDOWN Command?

Yes

No

Power-down Mode(3)

POWERDOWN Command?

Yes

No

START/SYNCCommand?

Yes No

Conversionmode selection(2)

20




8.4 Device Functional ModesFigure 33 shows a flow chart of the different operating modes and how the device transitions from one mode toanother.

(1) Any reset (power-on, command, or pin) immediately resets the device.(2) The conversion mode is selected with the CM bit in the configuration register.(3) The POWERDOWN command allows any ongoing conversion to complete before placing the device in power-down

mode.

Figure 33. Operating Flow Chart

8.4.1 Power-Up and ResetThe ADS1219 is reset in one of three ways: either by a power-on reset, by the RESET pin, or by a RESETcommand.

When a reset occurs, the configuration register resets to the default values and the device enters a low-powerstate. The device then waits for the START/SYNC command to enter conversion mode; see the I2C TimingRequirements table for reset timing information.


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21




Device Functional Modes (continued)8.4.1.1 Power-On ResetDuring power up, the device is held in reset. The power-on reset releases approximately 500 µs after bothsupplies have exceeded their respective power-up reset thresholds. After this time all internal circuitry (includingthe voltage reference) are stable and communication with the device is possible. As part of the power-on resetprocess, the device sets all bits in the configuration register to the respective default settings. After power-up, thedevice enters a low-power state. This power-up behavior is intended to prevent systems with tight power-supplyrequirements from encountering a current surge during power-up.

8.4.1.2 RESET PinReset the ADC by taking the RESET pin low for a minimum of tw(RSL) and then returning the pin high. After therising edge of the RESET pin, a delay time of td(RSSTA) is required before communicating with the device; see theI2C Timing Requirements table for reset timing information.

8.4.1.3 Reset by CommandReset the ADC by using the RESET command (06h or 07h). No delay time is required after the RESETcommand is latched before starting to communicate with the device as long as the timing requirements (see theI2C Timing Requirements table) for the (repeated) START and STOP conditions are met. Alternatively, the devicealso responds to the I2C general-call software reset.

8.4.2 Conversion ModesThe device operates in one of two conversion modes that are selected by the CM bit in the configuration register.These conversion modes are single-shot conversion and continuous conversion mode. A START/SYNCcommand must be issued each time the CM bit is changed.

8.4.2.1 Single-Shot Conversion ModeIn single-shot conversion mode, the device only performs a conversion when a START/SYNC command isissued. The device consequently performs one single conversion and returns to a low-power state afterwards.The internal oscillator and all analog circuitry are turned off while the device waits in this low-power state until thenext conversion is started. Writing to the configuration register when a conversion is ongoing functions as a newSTART/SYNC command that stops the current conversion and restarts a single new conversion. Eachconversion is fully settled (assuming the analog input signal settles to the final value before the conversion starts)because the device digital filter settles within a single cycle.

8.4.2.2 Continuous Conversion ModeIn continuous conversion mode, the device continuously performs conversions. When a conversion completes,the device places the result in the output buffer and immediately begins another conversion.

In order to start continuous conversion mode, the CM bit must be set to 1 followed by a START/SYNC command.The first conversion starts 28.5 · tCLK after the START/SYNC command is latched. Writing to the configurationregister during an ongoing conversion restarts the current conversion. Send a START/SYNC commandimmediately after the CM bit is set to 1.

Stop continuous conversions by sending the POWERDOWN command.

8.4.3 Power-Down ModeWhen the POWERDOWN command is issued, the device enters power-down mode after completing the currentconversion. In this mode, all analog circuitry (including the voltage reference) are powered down and the devicetypically only uses 400 nA of current. When in power-down mode, the device holds the configuration registersettings and responds to commands, but does not perform any data conversions.

Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuousconversion mode, depending on the conversion mode selected by the CM bit.


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22




8.5 Programming

8.5.1 I2C InterfaceThe ADS1219 uses an I2C-compatible (inter-integrated circuit) interface for serial communication. I2C is a 2-wirecommunication interface that allows communication of a master device with multiple slave devices on the samebus through the use of device addressing. Each slave device on an I2C bus must have a unique address.Communication on the I2C bus always takes place between two devices: one acting as the master and the otheras the slave. Both the master and slave can receive and transmit data, but the slave can only read or write underthe direction of the master. The ADS1219 always acts as an I2C slave device.

An I2C bus consists of two lines: SDA and SCL. SDA carries data and SCL provides the clock. Devices on theI2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high.Instead, the bus wires are pulled high by pullup resistors; thus, the bus wires are always high when a device isnot driving the lines low. As a result of this configuration, two devices do not conflict. If two devices drive the bussimultaneously, there is no driver contention.

See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.

8.5.1.1 I2C AddressThe ADS1219 has two address pins: A0 and A1. Each address pin can be tied to either DGND, DVDD, SDA, orSCL, providing 16 possible unique addresses. This configuration allows up to 16 different ADS1219 devices tobe present on the same I2C bus. Table 5 shows the truth table for the I2C addresses for the possible address pinconnections.

At the start of every transaction, that is between the START condition (first falling edge of SDA) and the firstfalling SCL edge of the address byte, the ADS1219 decodes its address configuration again.

Table 5. I2C Address Truth TableA1 A0 I2C ADDRESS

DGND DGND 100 0000DGND DVDD 100 0001DGND SDA 100 0010DGND SCL 100 0011DVDD DGND 100 0100DVDD DVDD 100 0101DVDD SDA 100 0110DVDD SCL 100 0111SDA DGND 100 1000SDA DVDD 100 1001SDA SDA 100 1010SDA SCL 100 1011SCL DGND 100 1100SCL DVDD 100 1101SCL SDA 100 1110SCL SCL 100 1111

8.5.1.2 Serial Clock (SCL) and Serial Data (SDA)The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line.The ADS1219 cannot act as a master and as a result can never drive SCL.

The serial data (SDA) line allows for bidirectional communication between the host (the master) and theADS1219 (the slave). When the master reads from a ADS1219, the ADS1219 drives the data line; when themaster writes to a ADS1219, the master drives the data line.

Data on the SDA line must be stable during the high period of the clock. The high or low state of the data linecan only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When inan idle state, the master should hold SCL high.


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https://www.nxp.com/docs/en/user-guide/UM10204.pdf

S

SDA

SCL

P

1 - 7 8 9 1 - 8 9 1 - 8 9

ADDRESS R/W ACKfrom slave

DATA DATA ACKfrom receiver

STARTCondition

STOPCondition

A6 ± A0 D7 ± D0 D7 ± D0

ACKfrom receiver

23




8.5.1.3 Data Ready (DRDY)DRDY is an open-drain output pin that indicates when a new conversion result is ready for retrieval. When DRDYfalls low, new conversion data are ready. DRDY transitions back high when the conversion result is latched foroutput transmission. In case a conversion result in continuous conversion mode is not read, DRDY releases highfor tw(DRH) before the next conversion completes. See the I2C Timing Requirements table for more details.

8.5.1.4 Interface SpeedThe ADS1219 supports I2C interface speeds up to 1 Mbps. Standard-mode (Sm) with bit rates up to 100 kbps,fast-mode (Fm) with bit rates up to 400 kbps, and fast-mode plus (Fm+) with bit rates up to 1 Mbps aresupported. High-speed mode (Hs-mode) is not supported.

8.5.1.5 Data Transfer ProtocolFigure 34 shows the format of the data transfer. The master initiates all transactions with the ADS1219 bygenerating a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a STARTcondition. The bus is considered to be busy after the START condition.

Following the START condition, the master sends the 7-bit slave address corresponding to the address of theADS1219 that the master wants to communicate with. The master then sends an eighth bit that is a datadirection bit (R/W). An R/W bit of 0 indicates a write operation, and an R/W bit of 1 indicates a read operation.After the R/W bit, the master generates a ninth SCLK pulse and releases the SDA line to allow the ADS1219 toacknowledge (ACK) the reception of the slave address by pulling SDA low. In case the device does notrecognize the slave address, the ADS1219 holds SDA high to indicate a not acknowledge (NACK) signal.

Next follows the data transmission. If the transaction is a read (R/W = 1), the ADS1219 outputs data on SDA. Ifthe transaction is a write (R/W = 0), the host outputs data on SDA. Data are transferred byte-wise, mostsignificant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each bytemust be acknowledged (via the ACK bit) by the receiver. If the transaction is a read, the master issues the ACK.If the transaction is a write, the ADS1219 issues the ACK.

The master terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDAline while SCL is high defines a STOP condition. The bus is considered free again tBUF (bus-free time) after theSTOP condition.

Figure 34. I2C Data Transfer Format

8.5.1.6 I2C General Call (Software Reset)The ADS1219 responds to the I2C general-call address (0000 000) if the R/W bit is 0. The device acknowledgesthe general-call address and, if the next byte is 06h, performs a reset. The general-call software reset has thesame effect as the RESET command.

8.5.1.7 TimeoutThe ADS1219 offers a I2C timeout feature that can be used to recover communication when a serial interfacetransmission is interrupted. If the host initiates contact with the ADS1219 but subsequently remains idle for14000 · tMOD before completing a command, the ADS1219 interface is reset. If the ADS1219 interface resetsbecause of a timeout condition, the host must abort the transaction and restart the communication again byissuing a new START condition.


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7FFFFFh

Outp

ut C

ode

-FS ¼ 0 ¼ FS

Input Voltage VIN

7FFFFEh

000001h

¼

000000h

800000h

FFFFFFh

800001h

¼

-FS2 - 1

23

223

FS2 - 1

23

223

24




8.5.2 Data FormatThe device provides 24 bits of data in binary two's complement format. Use Equation 5 to calculate the size ofone code (LSB).

1 LSB = (2 · VREF / Gain) / 224 = +FS / 223 (5)

A positive full-scale input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFFFhand a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 800000h. The output clipsat these codes for signals that exceed full-scale.

Table 6 summarizes the ideal output codes for different input signals.

(1) Excludes the effects of noise, INL, offset, and gain errors.

Table 6. Ideal Output Code versus Input SignalINPUT SIGNAL,

VIN = VAINP – VAINN IDEAL OUTPUT CODE (1)

≥ FS (223 – 1) / 223 7FFFFFhFS / 223 000001h

0 000000h–FS / 223 FFFFFFh≤ –FS 800000h

Figure 35 shows the mapping of the analog input signal to the output codes.

Figure 35. Code Transition Diagram

NOTESingle-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only usethe positive code range from 000000h to 7FFFFFh. However, because of device offset,the ADS1219 can still output negative codes when VAINP is close to 0 V.


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S = START condition

Sr = Repeated START condition

P = STOP condition

A = acknowledge (SDA low)

A = not acknowledge (SDA high)

From master to slave

From slave to master

25




(1) Operands: r = register address (0 or 1), x = don't care.

8.5.3 CommandsAs Table 7 shows, the device offers six different commands to control device operation. Four commands arestand-alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG)and write (WREG) register data from and to the device require additional information as part of the instruction.

Table 7. Command DefinitionsCOMMAND DESCRIPTION COMMAND BYTE (1)

RESET Reset the device 0000 011xSTART/SYNC Start or restart conversions 0000 100xPOWERDOWN Enter power-down mode 0000 001xRDATA Read data by command 0001 xxxxRREG Read register at address r 0010 0rxxWREG Write configuration register 0100 00xx

8.5.3.1 Command LatchingCommands are not processed until latched by the ADS1219. Commands are latched on the eighth falling edge ofSCL in the command byte.

NOTEThe legend for Figure 36 to Figure 40:

8.5.3.2 RESET (0000 011x)This command resets the device to the default states. No delay time is required after the RESET command islatched before starting to communicate with the device as long as the timing requirements (see the I2C TimingRequirements table) for the (repeated) START and STOP conditions are met.

8.5.3.3 START/SYNC (0000 100x)In single-shot conversion mode, the START/SYNC command is used to start a single conversion, or (when sentduring an ongoing conversion) to reset the digital filter and then restart a single new conversion. When thedevice is set to continuous conversion mode, the START/SYNC command must be issued one time to startconverting continuously. Sending the START/SYNC command when converting in continuous conversion moderesets the digital filter and restarts continuous conversions.

8.5.3.4 POWERDOWN (0000 001x)The POWERDOWN command places the device into power-down mode. This command shuts down all internalanalog components, but holds all register values. In case the POWERDOWN command is issued when aconversion is ongoing, the conversion completes before the ADS1219 enters power-down mode. As soon as aSTART/SYNC command is issued, all analog components return to their previous states.


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S SLAVE ADDRESS W A WREG A REGISTER DATA PA

S SLAVE ADDRESS W A RREG A

Sr SLAVE ADDRESS R A REGISTER DATA A P

��

��

S SLAVE ADDRESS W A RDATA A Sr SLAVE ADDRESS R A

CONVERSION DATA (MSB) A PA CONVERSION DATA A CONVERSION DATA (LSB)

��

��

26




8.5.3.5 RDATA (0001 xxxx)The RDATA command loads the output shift register with the most recent conversion result. Reading conversiondata must be performed as shown in Figure 36 by using two I2C communication frames. The first frame is an I2Cwrite operation where the R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the hostsends the RDATA command to the ADS1219. The second frame is an I2C read operation where the R/W bit atthe end of the address byte is 1 to indicate a read. The ADS1219 reports the latest ADC conversion data in thissecond I2C frame. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY pinat the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded,DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY ishigh.

Figure 36. Read Conversion Data Sequence

8.5.3.6 RREG (0010 0rxx)The RREG command reads the value of the register at address r. Reading a register must be performed asshown in Figure 37 by using two I2C communication frames. The first frame is an I2C write operation where theR/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host sends the RREG commandincluding the register address to the ADS1219. The second frame is an I2C read operation where the R/W bit atthe end of the address byte is 1 to indicate a read. The ADS1219 reports the contents of the requested registerin this second I2C frame.

Figure 37. Read Register Sequence

8.5.3.7 WREG (0100 00xx dddd dddd)The WREG command writes dddd dddd to the configuration register. Figure 38 shows the sequence for writingthe configuration register. The R/W bit at the end of the address byte is 0 to indicate a write. The WREGcommand forces the digital filter to reset and any ongoing ADC conversion to restart.

Figure 38. Write Register Sequence


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S SLAVE ADDRESS W A RREG (01h) A Sr SLAVE ADDRESS R A

REGISTER DATA (01h)

A P

A

CONVERSION DATA (LSB)

��

�� Sr SLAVE ADDRESS A RDATA AW

Sr SLAVE ADDRESS R A�� CONVERSION DATA (MSB) A CONVERSION DATA A ��

��

S SLAVE ADDRESS W A RDATA A Sr SLAVE ADDRESS R A

CONVERSION DATA (MSB) A PA CONVERSION DATA A CONVERSION DATA (LSB)

��

��

DRDY ��

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8.5.4 Reading Data and Monitoring for New Conversion ResultsConversion data are read by issuing the RDATA command. The ADS1219 responds to the RDATA commandwith the latest conversion result. There are two ways to monitor for new conversion data.

One way is to monitor for the falling edge of the DRDY signal. When DRDY falls low, a new conversion result isavailable for retrieval using the RDATA command. Figure 39 shows the timing diagram for collecting data usingthe DRDY signal to indicate new data.

Figure 39. Using the DRDY Pin to Check for New Conversion Data

Another way to monitor for a new conversion result is to periodically read the DRDY bit in the status register. Ifset, the DRDY bit indicates that a new conversion result is ready for retrieval. The host can subsequently issuean RDATA command to retrieve the data. The rate at which the host polls the ADS1219 for new data must be atleast as fast as the data rate in continuous conversion mode to prevent the host from missing a conversionresult.

If a new conversion result becomes ready during an I2C transmission, the transmission is not corrupted. The newdata are loaded into the output shift register upon the following RDATA command.

Figure 40 shows the timing diagram for collecting data using the DRDY bit in the status register to indicate newdata.

Figure 40. Using the DRDY Bit to Check for New Conversion Data

8.6 Register Map

8.6.1 Configuration and Status RegistersThe device has two 8-bit registers (configuration and status) that are accessible through the I2C interface usingthe RREG and WREG commands. After power-up or reset, both registers are set to the default values (which areall 0). All register values are retained during power-down mode. Table 8 shows the register map of the tworegisters.

Table 8. Register MapREGISTER

(Hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0h MUX[2:0] GAIN DR[1:0] CM VREF

1h DRDY ID[6:0]


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8.6.2 Register DescriptionsTable 9 lists the access codes for the ADS1219 registers.

Table 9. Register Access Type CodesAccess Type Code DescriptionR R ReadR/W R/W Read-Write-n Value after reset or the default value

8.6.2.1 Configuration Register (address = 0h) [reset = 00h]

Figure 41. Configuration Register

7 6 5 4 3 2 1 0MUX[2:0] GAIN DR[1:0] CM VREFR/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10. Configuration Register Field DescriptionsBit Field Type Reset Description7:5 MUX[2:0] R/W 0h Input multiplexer configuration

These bits configure the input multiplexer.000 : AINP = AIN0, AINN = AIN1 (default)001 : AINP = AIN2, AINN = AIN3010 : AINP = AIN1, AINN = AIN2011 : AINP = AIN0, AINN = AGND100 : AINP = AIN1, AINN = AGND101 : AINP = AIN2, AINN = AGND110 : AINP = AIN3, AINN = AGND111 : AINP and AINN shorted to AVDD / 2

4 GAIN R/W 0h Gain configurationThis bit configures the device gain.0 : Gain = 1 (default)1 : Gain = 4

3:2 DR[1:0] R/W 0h Data rateThese bits control the data rate setting.00 : 20 SPS (default)01 : 90 SPS10 : 330 SPS11 : 1000 SPS

1 CM R/W 0h Conversion modeThis bit sets the conversion mode for the device.0 : Single-shot conversion mode (default)1 : Continuous conversion mode

0 VREF R/W 0h Voltage reference selectionThis bit selects the voltage reference source that is used for the conversion.0 : Internal 2.048-V reference selected (default)1 : External reference selected using the REFP and REFN inputs


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8.6.2.2 Status Register (address = 1h) [reset = 00h]

Figure 42. Status Register

7 6 5 4 3 2 1 0DRDY RESERVEDR-0h R-xxh

Table 11. Status Register Field DescriptionsBit Field Type Reset Description7 DRDY R 0h Conversion result ready flag

This bit flags if a new conversion result is ready. This bit is reset when conversiondata are read.0 : No new conversion result available (default)1 : New conversion result ready

6:0 RESERVED R xxh ReservedValues are subject to change without notice.


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0.1 PF

SC

L

SD

A

3.3 V

GP

IO/IR

Q

Microcontroller with I2C Interface

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3.3 V

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DV

SS

16

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12

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9

1

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AGND

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AIN2

REFN REFP

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AIN0

AVDD

DVDD

DRDY

SDA

SCLA0

A1

0.1 PF

3.3 V

Rp

3.3 V

Rp

3.3 V

3.3 V

Rp

3.3 V

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9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe ADS1219 is a precision, 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) that integrates allfeatures required to implement the most common system monitoring functions, such as supply voltage, current,and temperature monitoring. Primary considerations when designing an application with the ADS1219 includeanalog input filtering, and establishing an appropriate external reference for ratiometric measurements.Connecting and configuring the interface appropriately is another concern. These considerations are discussed inthe following sections.

9.1.1 Interface ConnectionsFigure 43 shows the principle interface connections for the ADS1219.

Figure 43. Interface Connections

The ADS1219 interfaces directly to standard-mode, fast-mode, or fast-mode plus I2C controllers. Anymicrocontroller I2C peripheral, including master-only and single-master I2C peripherals, operates with theADS1219. Details of the I2C communication protocol of the device can be found in the Programming section. TheADS1219 does not perform clock-stretching (that is, the device never pulls the clock line low), so this functiondoes not need to be provided for unless other clock-stretching devices are present on the same I2C bus.


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SC

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A

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DV

DD

DV

SS

16

15

14

13

12

11

10

9

1

2

3

4

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7

8

Device 1

RESET

DGND

AGND

AIN3

AIN2

REFN REFP

AIN1

AIN0

AVDD

DVDD

DRDY

SDA

SCLA0

A1

Rp

DVDD

16

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14

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12

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10

9

1

2

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6

7

8

Device 2

RESET

DGND

AGND

AIN3

AIN2

REFN REFP

AIN1

AIN0

AVDD

DVDD

DRDY

SDA

SCLA0

A1

DVDD 16

15

14

13

12

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10

9

2

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8

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RESET

DGND

AGND

AIN3

AIN2

REFN REFP

AIN1

AIN0

AVDD

DVDD

DRDY

SDA

SCLA0

A1

DVDD 1

Rp

DVDD

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Application Information (continued)Pullup resistors are required on both the SDA and SCL lines, as well as on the open-drain DRDY output. Thesize of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-valueresistors yield lower power consumption when the bus lines are pulled low, but increase the transition times onthe bus, which limits the bus speed. Lower-value resistors allow higher interface speeds, but at the expense ofhigher power consumption when the bus lines are pulled low. Long bus lines have higher capacitance andrequire smaller pullup resistors to compensate. Do not use resistors that are too small because the bus driversmay be unable to pull the bus lines low. See the I2C-Bus Specification and User Manual for details on pullupresistor sizing.

9.1.2 Connecting Multiple Devices on the Same I2C BusUp to 16 ADS1219 devices can be connected to a single I2C bus by using different address pin configurations foreach device. Use the address pins, A0 and A1, to set the ADS1219 to one of 16 different I2C addresses.Figure 44 shows an example with three ADS1219 devices on the same I2C bus. One set of pullup resistors isrequired per bus line. If needed, decrease the pullup resistor values to compensate for the additional buscapacitance presented by multiple devices and increased line length.

Figure 44. Connecting Multiple ADS1219 Devices on the Same I2C Bus

9.1.3 Unused Inputs and OutputsTo minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, orconnect the inputs to mid-supply or to AVDD. Connecting unused analog or reference inputs to AGND is possibleas well, but can yield higher leakage currents on other analog inputs than the previously mentioned options.

Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digitalinputs to the appropriate levels, DVDD or DGND, even when in power-down mode. Connections for unuseddigital pins are:• Tie the RESET pin to DVDD if the RESET pin is not used• If the DRDY output is not used, leave the DRDY pin unconnected or tie the DRDY pin to DVDD using a weak

pullup resistor


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https://www.nxp.com/docs/en/user-guide/UM10204.pdf

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Application Information (continued)9.1.4 Analog Input FilteringAnalog input filtering serves two purposes:• Limits the effect of aliasing during the ADC sampling process• Attenuates unwanted noise components outside the bandwidth of interest

In most cases, a first-order resistor capacitor (RC) filter is sufficient to completely eliminate aliasing or to reducethe effect of aliasing to a level within the noise floor of the sensor. A good starting point for a system design withthe ADS1219 is to use a differential RC filter with a cutoff frequency set somewhere between the selected outputdata rate and 25 kHz. Make the series resistor values as small as possible to reduce voltage drops across theresistors caused by the device input currents to a minimum. However, the resistors should be large enough tolimit the current into the analog inputs to less than 10 mA in the event of an overvoltage. Then choose thedifferential capacitor value to achieve the target filter cutoff frequency. Common-mode filter capacitors to GNDcan be added as well, but should always be at least ten times smaller than the differential filter capacitor.

Internal to the device, prior to the buffer inputs, is an EMI filter. The cutoff frequency of this filter is approximately31.8 MHz, which helps reject high-frequency interferences.

9.1.5 External Reference and Ratiometric MeasurementsThe full-scale range (FSR) of the ADS1219 is defined by the reference voltage and the gain setting (FSR =±VREF / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR tothe specific system needs. An external reference must be used if VIN is greater than 2.048 V. For example, anexternal 5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swingbetween 0 V and 5 V.

The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometricmeasurement the same excitation source that is used to excite the sensor is also used to establish the referencefor the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to exciteboth the resistive sensor element (such as an RTD) and another resistive reference element that is in series withthe element being measured. The voltage that develops across the reference element is used as the referencesource for the ADC. These components cancel out in the ADC transfer function because current noise and driftare common to both the sensor measurement and the reference. The output code is only a ratio of the sensorelement and the value of the reference resistor. The value of the excitation current source itself is not part of theADC transfer function.

9.1.6 Establishing Proper Limits on the Absolute Input VoltageThe ADS1219 can be used to measure various types of input signal configurations: single-ended, pseudo-differential, and fully differential signals. However, configuring the device properly for the respective signal type isimportant.

Signals where the negative analog input is fixed and referenced to analog ground (VAINN = 0 V) are commonlycalled single-ended signals. The absolute input voltages of the ADS1219 can be as low as 100 mV below AGNDand as large as 100 mV above AVDD. Using the gain of 4 is still possible in this configuration. Measuring a 0-mAto 20-mA or 4-mA to 20-mA signal across a load resistor of 100 Ω referenced to GND is a typical example. TheADS1219 can directly measure the signal across the load resistor using the internal 2.048-V reference and gain= 1.

Signals where the negative analog input (AINN) is fixed at a voltage other the 0 V are referred to as pseudo-differential signals.

Fully differential signals in contrast are defined as signals having a constant common-mode voltage where thepositive and negative analog inputs swing 180° out-of-phase but have the same amplitude.

The ADS1219 can measure pseudo-differential and fully differential signals.

Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signalscan in general be measured with the ADS1219. A signal is called bipolar when either the positive or negativeinput can swing below 0 V. Bipolar signals cannot be measured with the ADS1219.


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Application Information (continued)9.1.7 Pseudo Code ExampleThe following list shows a pseudo code sequence with the required steps to set up the device and themicrocontroller that interfaces to the ADC in order to take subsequent readings from the ADS1219 in continuousconversion mode. The DRDY pin is used to indicate availability of new conversion data. The default configurationregister settings are changed to gain = 4 and continuous conversion mode.

Power-up;Delay to allow power supplies to settle and power-on reset to complete; minimum of 500 µs;Configure the I2C interface of the microcontroller;Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interruptinput;

Send the RESET command (06h) to make sure the device is properly reset after power-up;

Write the respective register configuration with the WREG command (40h, 12h);As an optional sanity check, read back the configuration register with the RREG command (20h);

Send the START/SYNC command (08h) to start converting in continuous conversion mode;

Loop{

Wait for DRDY to transition low;Send the RDATA command (10h) to read 3 bytes of conversion data;

}

Send the POWERDOWN command (02h) to stop conversions and put the device in power-down mode;

TI recommends running an offset calibration before performing any measurements or when changing the gain orMUX settings. The internal offset of the device can, for example, be measured by shorting the inputs to mid-supply (MUX[2:0] = 111). The microcontroller then takes multiple readings from the device with the inputs shortedand stores the average value in the microcontroller memory. When measuring the sensor signal, themicrocontroller then subtracts the stored offset value from each device reading to obtain an offset compensatedresult; the offset can be either positive or negative in value.


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ReferenceMUX

AIN0

AIN1

AIN2

AIN3

AVDD

AGND DGND

REFP REFN

2.048-V Reference

DVDD

Digital Filterand

I2C Interface


ADS1219

SDA

SCL

A1

A0

RESET

DRDY

3.3 V

0.1 PF

3.3 V

0.1 PF

CF3

RF3

0 V to 2 V

RShunt

CF2

RF2

Load

3.3 V

+

-

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RF0

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INA180

0.1 PF

24-bitû��ADC

Gain1 or 4

Buffers

MUX

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9.2 Typical ApplicationThis application example describes how to use the ADS1219 for the most common system monitoring functions(such as voltage measurement, high-side current measurement using a current sense amplifier, and temperaturemeasurement using a thermistor or 2-wire RTD). Figure 45 shows a typical circuit implementation.

Figure 45. Typical System Monitoring Example Using the ADS1219

9.2.1 Design RequirementsTable 12 lists the design requirements for this application.

(1) After offset and gain calibration at TA = 25°C.

Table 12. Design RequirementsDESIGN PARAMETER VALUE

Supply voltage 3.3 VVoltage measurement range 0 V to 2 V

Voltage measurement accuracy (1) ±0.5 mVCurrent measurement range (unidirectonal) 0.5 A to 10 AMaximum voltage drop across shunt resistor 20 mV

Current measurement accuracy (1) ±5 mAThermistor type NTC

Thermistor nominal resistance 10 kΩThermistor temperature range –40°C to +125°C

Thermistor temperature measurement accuracy (1) ±0.1°CUpdate rate 100 ms

9.2.2 Detailed Design ProcedureIn order to take one reading from each of the three input signals within 100 ms, the ADS1219 must use a datarate of 90 SPS or faster. When using a data rate setting of 90 SPS, every conversion takes approximately11.3 ms according to Table 4. Consequently, all three signals can be measured within approximately 34 mswhen also accounting for the time to read conversion results and to write new configuration register settingsbetween conversions.


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35




All three signal measurements use a single-ended measurement implementation. The voltage and currentmeasurements use the GND connection within the MUX, whereas the thermistor measurement uses an externalGND connection through AIN1 to showcase the two different options for implementing a single-endedmeasurement.

RC filters are provided on all three analog inputs of the device, which act as antialiasing filters and to limit thecurrent into the analog inputs in case of overvoltage events. The filter component values are chosen according tothe guidelines in the Analog Input Filtering section as RF = 1 kΩ and CF = 100 nF to create a filter cornerfrequency of fC = 1 / (2π · RF · CF) = 1.6 kHz.

9.2.2.1 Voltage MonitoringThe ADS1219 can measure single-ended signals ranging from AGND to VREF / Gain. In order to monitor voltagesup to 2 V, the device is configured to use the internal 2.048-V reference and gain = 1.

Equation 6 details the relationship between output codes of the ADS1219 and the input voltage on AIN3.VAIN3 = (VREF / Gain) · (Code / 223) = 2.048 V · Code / 223 (6)

An external voltage reference must be provided on the external reference inputs of the device in case largervoltages than 2.048 V are to be monitored. The device can measure input signals up to the positive analogsupply voltage in case AVDD is used as the positive reference input (REFP) and AGND as the negativereference input (REFN). However the ADS1219 cannot monitor its own supply voltage in that case. As describedin Equation 6, when using VAIN3 = AVDD and VREF = AVDD, the device will always output a positive full-scalecode irrespective of the value of AVDD. To monitor the supply of the ADC, use a resistor divider instead to dividethe supply voltage down to below 2.048 V and measure the voltage using the internal reference.

The input-referred peak-to-peak noise of the ADC is ideally a factor smaller than the required measurementaccuracy of ±0.5 mV. At 90 SPS using gain = 1 the ADS1219 offers an input-referred noise of 43 µVPP, whichmeets this requirement.

9.2.2.2 High-Side Current MeasurementThe unidirectional, high-side load current measurement is implemented using a shunt resistor, RShunt, and acurrent-sense amplifier, INA180, with a gain of 100. To meet the requirement of a maximum voltage drop acrossRShunt of 20 mV at the maximum current of 10 A, the shunt resistor must be RShunt ≤ 20 mV / 10 A = 2 mΩ. Theoutput signal of the INA180 is fed single-endedly to input AIN2 of the ADS1219. Consequently, the voltage atAIN2 ranges from 0 V to (2 mΩ · 10 A · 100) = 2 V, which can be measured using the internal 2.048-V referenceand gain = 1 of the ADC.

Equation 7 through Equation 9 describe the relationship between output codes of the ADS1219 and the currentacross the shunt resistor.

VAIN2 = (VREF / GainADC) · (Code / 223) = 2.048 V · Code / 223 (7)VShunt = VAIN2 / GainINA = VAIN2 / 100 (8)IShunt = VShunt / RShunt = (VREF · Code) / (GainADC· GainINA · RShunt · 223) = (2.048 V · Code) / (100 · 2 mΩ · 223) (9)

9.2.2.3 Thermistor MeasurementThe temperature measurement using a 10-kΩ thermistor is implemented using a ratiometric measurementapproach to achieve best accuracy. The analog supply voltage, AVDD, is used as the excitation voltage for thethermistor in a resistor divider configuration, as well as the external reference voltage, VREF, for the ADS1219.

The relationship between output codes of the ADS1219 and the thermistor resistance, RThermistor, is derived usingthe following equations. Equation 10 expresses the input voltage at input AIN0 as the voltage across RThermistor,whereas Equation 11 shows how the ADC converts the voltage at AIN0 into corresponding digital codes.

VAIN0 = RThermistor / (RThermistor + RREF) · VREF (10)VAIN0 = (VREF / Gain) · (Code / 223) (11)

Setting Equation 10 equal to Equation 11 and solving for RThermistor yields the relationship between thermistorresistance and ADC code.

RThermistor / (RThermistor + RREF) = Gain · (Code / 223) (12)RThermistor = RREF · Gain · (Code / 223) / [1 – Gain · (Code / 223)] (13)


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http://www.ti.com/product/INA180

VAIN3 (V)

Mea

sure

men

t Err

or (

mV

)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-1

-0.8

-0.6

-0.4

-0.2

0

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Before CalibrationAfter Calibration

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Equation 13 proves that the output code and thus the accuracy of the thermistor measurement is independent ofthe excitation voltage. The accuracy of the reference resistor, RREF, is typically dominating the measurementaccuracy in such a ratiometric circuit implementation. A high-precision, low-drift resistor is therefore required forRREF. For best performance, the value of RREF is chosen such that the ratio between RREF and RThermistor_Maxequals the ratio between RThermistor_Min and RREF. Equation 14 is therefore used to calculate RREF.

RREF² = RThermistor_Min · RThermistor_Max (14)

At the two temperature measurement extremes, –40°C and +125°C, a typical 10-kΩ NTC exhibits a resistance ofRThermistor_Max = 239.8 kΩ and RThermistor_Min = 425.3 Ω, respectively. Using Equation 14, RREF calculates to10.1 kΩ. A 10-kΩ resistor is chosen for this example. Consequently, when using Equation 10, the voltage at theADC input ranges from 0.13 V to 3.17 V. Thus, an ADC gain = 1 must be used for the measurement.

The microcontroller interfacing to the ADS1219 converts RThermistor into a corresponding thermistor temperatureby either solving the Steinhart-Hart equation or leveraging a look-up table.

9.2.2.4 Register SettingsTable 13 summarizes the configuration register bit settings used for the different measurements in this example.

Table 13. Configuration Register SettingsMEASUREMENT BIT SETTINGS DESCRIPTION

Voltage 1100 0100 AIN3:AGND, gain = 1, DR = 90 SPS, single-shot conversion mode, internal VREFCurrent 1010 0100 AIN2:AGND, gain = 1, DR = 90 SPS, single-shot conversion mode, internal VREF

Thermistor 0000 0101 AIN0:AIN1, gain = 1, DR = 90 SPS, single-shot conversion mode, external VREF

9.2.3 Application CurveFigure 46 shows the measurement results for the voltage measurement on AIN3. The measurements are takenat TA = 25°C. The black curve shows the measurement error in mV without any offset and gain calibration. Thered curve shows the measurement error after offset and gain calibration. The gain calibration removes both thegain error and the error introduced by the initial inaccuracy of the internal voltage reference.

Figure 46. Measurement Error of Voltage Measurement


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10 Power Supply RecommendationsThe device requires two power supplies: analog (AVDD, AGND) and digital (DVDD, DGND). The analog powersupply is independent of the digital power supply. The digital supply sets the digital I/O levels.

10.1 Power-Supply SequencingThe power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed therespective analog or digital power-supply voltage and current limits. Wait approximately 500 µs after all powersupplies are stabilized before communicating with the device to allow the power-on reset process to complete.

10.2 Power-Supply DecouplingGood power-supply decoupling is important to achieve optimum performance. As shown in Figure 47, AVDD andDVDD must be decoupled with at least a 0.1-µF capacitor. Place the bypass capacitors as close to the power-supply pins of the device as possible using low-impedance connections. TI recommends using multi-layerceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL)characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noiseenvironments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noiseimmunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections toground planes. Connect analog and digital grounds together as close to the device as possible.

Figure 47. Power-Supply Decoupling


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11 Layout

11.1 Layout GuidelinesEmploying best design practices is recommended when laying out a printed-circuit board (PCB) for both analogand digital components. This recommendation generally means that the layout separates analog components[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digitalcomponents [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gatearrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switchingregulators].

The following basic recommendations for layout of the ADS1219 help achieve the best possible performance ofthe ADC. A good design can be ruined with a bad circuit layout.• Separate analog and digital signals. To start, partition the board into analog and digital sections where the

layout permits. Routing digital lines away from analog lines prevents digital noise from coupling back intoanalog signals.

• The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but is not necessary.Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in thelayout, the split between the analog and digital grounds must be connected together at the ADC.

• Fill void areas on signal layers with ground fill.• Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground

plane is cut or has other traces that block the current from flowing right next to the signal trace, another pathmust be found to return to the source and complete the circuit. If forced into a larger path, the chance that thesignal radiates increases. Sensitive signals are more susceptible to EMI interference.

• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypasscapacitors and the active device. Placing the bypass capacitors on the same layer as close to the activedevice yields the best results.

• Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that reactwith the input bias current and cause an added error voltage. Reducing the loop area enclosed by the sourcesignal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMIpickup and reduces the high-frequency impedance at the input of the device.

• Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensorcan create a parasitic thermocouple that can add an offset to the measurement. Differential inputs must bematched for both the inputs going to the measurement source.

• Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Bestinput combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 andAIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G(NPO) that have stable properties and low noise characteristics.


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9: REFP

1: A0

8: REFN

7: AIN2

6: AIN3

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DY

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A1

Vias connect to either the bottom layer oran internal plane. The bottom layer orinternal plane are dedicated GND planes(GND = AGND = DGND).

RE

SE

T

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11.2 Layout Example

Figure 48. Layout Example


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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products DisclaimerTI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICESOR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related DocumentationFor related documentation see the following:• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet• Texas Instruments, INAx180 Low- and High-Side Voltage Output, Current-Sense Amplifiers data sheet

12.3 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.4 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.5 TrademarksE2E is a trademark of Texas Instruments.NXP Semiconductors is a trademark of NXP Semiconductors.All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


http://www.ti.com



http://www.ti.com/lit/pdf/SBOS410

http://www.ti.com/lit/pdf/SBOS741

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://e2e.ti.com

http://support.ti.com/

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PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

ADS1219IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS1219

ADS1219IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS1219

ADS1219IPWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 ADS1219

ADS1219IRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1219

ADS1219IRTET ACTIVE WQFN RTE 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1219

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

http://www.ti.com/product/ADS1219?CMP=conv-poasamples#samplebuy





PACKAGE OPTION ADDENDUM

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Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

ADS1219IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

ADS1219IPWT TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

ADS1219IRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2

ADS1219IRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jan-2021

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS1219IPWR TSSOP PW 16 2000 367.0 367.0 35.0

ADS1219IPWT TSSOP PW 16 250 210.0 185.0 35.0

ADS1219IRTER WQFN RTE 16 3000 367.0 367.0 38.0

ADS1219IRTET WQFN RTE 16 250 213.0 191.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jan-2021

Pack Materials-Page 2

http://www.ti.com/lit/slua271

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PACKAGE OUTLINE

C

14X 0.65

2X4.55

16X 0.300.19

TYP6.66.2

1.2 MAX

0.150.05

0.25GAGE PLANE

-80

BNOTE 4

4.54.3

A

NOTE 3

5.14.9

0.750.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE

4220204/A 02/2017

1

89

16

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153.

SEATINGPLANE

A 20DETAIL ATYPICAL

SCALE 2.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAXALL AROUND

0.05 MINALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP


4220204/A 02/2017

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE: 10X

SYMM

SYMM

1

8 9

16

15.000

METALSOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKOPENING

EXPOSED METALEXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASKDEFINED

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EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP


4220204/A 02/2017

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

SYMM

1

8 9

16

IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANYIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRDPARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriateTI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants youpermission to use these resources only for development of an application that uses the TI products described in the resource. Otherreproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third partyintellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available eitheron ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’sapplicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2021, Texas Instruments Incorporated

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