adsd fall2011 01 introduction updated
TRANSCRIPT
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Dr. Rehan Hafiz Lecture # 01
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Course Website for ADSD Fall 2011
http://lms.nust.edu.pk/
Key: EE803
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Lectures: Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm
Contact: By appointment/EmailOffice: VISpro Lab above SEECS Library
Acknowledgement: Material from the following sources has been consulted/used in theseslides:1. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan
Material/Slides from these slides CAN be used with following citing reference:Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
http://creativecommons.org/licenses/by-nc-sa/3.0/ -
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Introduction
Mine
On-going Projects & Research opportunities
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Introduction - Mine
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PhD, The University of Manchester: Reconfigurable signal processing
techniques for optical tomography
Area
Digital System Design for complex algorithms
Digital Image Processing, Video Registration, Immersive Displays
Activities
Group Director : Vision Imaging & Signal Processing Research Group (VISPRO)
Head: Digital Systems & Signal Processing Knowledge Group (Summer 2009-2011)
Projects
Ultra High Definition Panorama Generation & Rendering (Funded by ETRI Korea) Digital Image Calibration for Multi Projector Displays (Funded by Epic Technologies)
A Multi View Imaging (MVI) Processing Platform: Real Time Panoramic Mosaic
Generation (Funded by ICT R&D Fund)
Have been part of the project Design and Verification of Low-Power, High-Speed IP
Suite for Universal Serial Bus (USB 3.0) with Dr. Nazar (Funded by ICT R&D Fund)
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VISpro: Vision Imaging & Signal Processing Research Group
5htt ://vis ro.seecs.nust.edu. k/
Current Research Projects by various members
UHD Panorama & Rendering (ETRI)
Digital Image Calibration for Multi-Projector System (EPICTechnologies)
Multi View Imaging
Object Tracking & Tagging (Silicon Valley Company)
Texture Analysis based Population Estimation (HEC Funded)
Pico-Projection Systems
Collaborations
ETRI Korea
EPIC Technologies
Computer Vision LAB, LUMS
Image Processing Research
Group, Warwick
Dr. Rehan Hafiz (Lead)
Dr. M. Murtaza
Dr. Hammad Qureshi (DOC)
Dr. Shahzad (CSE)
Dr. Khawer Khurshid
Total Research Grants:
21 Million (PKR)
VISpro
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Research Opportunities 2010VISpro -- Multi-View Imaging (MVI) MVI: Videos acquired from multiple video sources
Enormous video dataEnormous information
Enormous applications
Multimedia/ Surveillance/ Inspection
Immersive Multimedia Applications
Sports/ Cricket Match
Video Conferencing
Research Theme
Real Time Panoramic View Generation
Real Time View Point Generation
Camera-1 Camera-2
Overlapping
region
I(x,y)T(x,y)
I`(x,y)
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Opportunities
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Volunteer RA-Ship
Do explore research groups at SEECS
Try out before your thesis begins
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Introduction-Aims
Name
Area of interest
Where u see yourself
in future Industry ?
Academia ?
Research ? Development ?
Any where else ?
What you expect to learn in this couse ?
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ADSD Fall 2011
Course Description
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Relevant Books
(Sho.) Digital Design of Signal Processing Systems
(Cil.) Advanced Digital Design with the Verilog HDL, M D. Ciletti
(Stv) Advanced FPGA Design, Steve Kilts
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Useful Books
Verilog HDL, Samir Palnitkar
Synthesis of Arithmetic Circuits
VLSI Signal Processing Systems, Parhi
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Course EvolutionADSD-Fall-2009 Course outline
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Introduction Digital design methodology (Cil.)
Combinational & Sequential Logic
(Cil.)
Common structures
HDL review
Synthesis
Design & Synthesis of Datapath
controllers (Cil.)
Micro-Architecture Fixed point & Floating point
Arithmetic
Architectures for ArithmeticProcessors (Cil.)
Adders, Multipliers, Dividers
Coordinate Rotation Digital Computer
(CORDIC Algorithm)
Advanced FPGA Design Concepts(Stv.)
Architecting Speed, Area & Power
Clock Domains
Reset Circuits
Coding for synthesis
Timing Analysis
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ADSD Fall 2011
Course Outline
Week Topic Description/ Lecture Breakdown
1 Introduction Outline & Introduction
Initial Assessment of students
Digital design methodology & design flow
2 Verilog+
Combinational Logic
Combinational Logic Review + Verilog Introduction
Combinational Building Blocks in Verilog
3 Verilog + Sequential
Logic
Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS)
Sequential Logic in Verilog
4 Synthesis in Verilog Synthesis of Blocking/Non-Blocking Statements
5 Micro-Architecture Design Partitioning + RISC Microprocessor + Micro architecture
Document6 Optimizing Speed Architecting Speed in Digital System Design: [Throughput, Latency,
Timing]
7 Optimizing Area Architecting Area in Digital System Design: [Area Optimization]
8 FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs
9 MID EXAM
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ADSD Fall 2011
Course Outline
Week Topic Description/ Lecture Breakdown
10 CDC Issues Cross-Clock Domain Issues & RESET circuits
11 Fixed-Point Arithmetic Arithmetic Operations: Review Fixed Point Representation
12 Adders Adders & Fast Adders
Multi-Operand Addition
13 Multipliers Multiplication , Multiplication by Constants + BOOTH Multipliers
13 CORDIC CORDIC (sine, cosine, magnitude, division, etc)
CORDIC implementation in HW
14 Algorithmic
Transformations for
System Design
DFG representation of DSP Algorithms
Iteration Bound
Retiming
15 AlgorithmicTransformations for
System Design
UnfoldingLook ahead transformations
16 Project Course Review &
Project Presentations
17 Project Project Presentations
18 END SEMESTER EXAM
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Distribution
Quizzes 10%
Assignment 10%
Research Project 15%
Mid 30%
Final 35%
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*There can be slight modifications & shall be notified earlier
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Furthermore
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After successful completion of this course the students shall be able to
port complex algorithms to hardware by designing efficient data-paths
and controllers; handle cross clock domain issues and shall have the
desired knowledge to design for meeting specifications (speed, logic
optimization).
The related relevant courses in your stream are:
ASIC Design Methodology
Advanced VLSI System Design
The course has NO associated LAB credit hours. However, interested
students can contact.
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Relevant Conferences
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IEEE International Symposium on Circuits andSystems ISCAS
DATE - Design, Automation, and Test in Europe
IEEE Symposium on Computer Arithmetic ISCA Applied Reconfigurable Computing ARC
Engineering of Reconfigurable Systems andAlgorithms ERSA
Design Automation Conference DAC International Symposium on High-Performance
Computer Architecture - HPCA
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Relevant Journals
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IEEE Transactions on Circuits and Systems for VideoTechnology TCSV
IEEE Transactions on Very Large Scale IntegrationSystems VLSI
ACM Transactions on Architecture and CodeOptimization TACO
Journal of Systems Architecture - Elsevier
Microprocessors and Microsystems Elsevier
Journal of Signal Processing Systems - Springer
AIP Review Scientific Instruments
ACM Transactions on Design Automation of ElectronicSystems (TODAES)
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Relevant Links
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Verilog Tutorial http://www.asic-world.com/verilog/veritut.html
Writing Technical Paper
http://www1.cs.columbia.edu/~hgs/etc/writing-style.html
http://www.asic-world.com/verilog/veritut.htmlhttp://www1.cs.columbia.edu/~hgs/etc/writing-style.htmlhttp://www1.cs.columbia.edu/~hgs/etc/writing-style.htmlhttp://www1.cs.columbia.edu/~hgs/etc/writing-style.htmlhttp://www1.cs.columbia.edu/~hgs/etc/writing-style.htmlhttp://www.asic-world.com/verilog/veritut.htmlhttp://www.asic-world.com/verilog/veritut.htmlhttp://www.asic-world.com/verilog/veritut.html -
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Class Ethics
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Class Ethics &.. Other stuff
Attendance
Respect for all & classroom discipline
Quizzes Anytime
Never cheat Better fail NOW or else will fail sometime LATER in life
Hard work always pays.
Assignments References (IEEE Indexing [1],[2],)
Plagiarism No copying
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PLAGIARISM
Adapted from What is Plagiarism PowerPoint
http://mciu.org/~spjvweb/plagiarism.ppt22
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Sirjeeby chancewe had the same
variable name
Oh !
I forgot toreplace-all the
variable names..
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Questions.
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Assessment
Status quo
Where we stand?
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Dr. Rehan Hafiz Lecture # 01
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More & Powerful design options are getting available to the developer.
Design Space Options : GPPs, DSPs, FPGAs, Application SpecificProcessors,ASICs
Design Space Exploration deals with deciding the best from theavailable options for the design.
For Further Reading : [SHO] Chapter-1
Design Space Exploration27
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Moores Law (1965) is fueling the DSP Market
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The number of transistors on a chip was doubling every 18 to 24 months and made the prediction for future
32nm => Sandy Bridge (2011) 11 nm => approx. 2015
More & Powerful Design Options are now available
[SHO]
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Design Options
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Programmable Processors (& Microcontrollers)
Programming flexibility
Optimized - Architectures with so much design effort put in their designs
Examples: Intel, Atmel, ARM Processors
Digital Signal Processors
Programming flexibility
Optimized - Architectures with so much design effort put in their designs
Examples: DSP from Texas Instruments
FPGA
Reconfigurable Hardware
Application Specific Instruction Set Processors (ASIPs) OR Fully dedicated design,e.g Unfied Serial Bus Controller for USB 3 PCI Expres 3.0
Also offer: Soft Processors [Microblaze, NIOS]
ASIC
Lower cost, low power
No flexibility of programming
Application Specific Instruction Set Processors (ASIPs) OR Fully dedicated design
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Design Space Options
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[SHO]
Design Decision depends on the
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Design Decision depends on the
nature & complexity of applications31
Applications are characterized
by amount of data, parallelism,
real time requirements.
l l f d
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Analyzing your application for design space
exploration
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Computationally intensive (number crunching) tasks Standard Tasks/Protocols/Interfaces/Encoding
Commercial off the shelf ASICs are available
Memory Controllers, Firewire interfaces
Non Standard Structured Tasks
Consist of code that has loops or nested loops with a few instructions being repeated anumber of times.
Suitable for FPGAs
Examples: FFT Butterflies
Non Standard Non Structured Tasks
More Code intensive & complex to port to H/W.
Suitable for DSPs
Adaptive Algorithms with multiple IF/Else such as Motion Vector Estimation
Control Oriented Tasks
User interfaces, control processes, system controllers and other code intensiveprotocols are usually mapped on GPPs or microcontrollers.
Multiple interrupts & Complex Scheduling are conveniently handled by OperatingSystems so better handled by instruction based Processors
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A typical system
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For complex systems
HW/SW co design may be
the only optimal choice.
Soft processors like NIOS
even allow you to make
custom instructions ! Use a processor with
FPGA/SICS as Hardware
Accelerators
http://www.openmoko.com/freerunner.html
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A little exercise
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Display- 480 x 640 pixels, VGA, resistance
type touch
User Interface Navigation- Touch screen on
LCD, 2 control buttons, 1 Power button, 1
Aux for 911 emergency call Wifi, Bluetooth,
Supports camera & JPEG compression
Built-in GPS Radio
Need support to run Mobile Applications
What components you shall be using for
your system ?
Group of 3 On a paper & submit
http://www.openmoko.com/freerunner.html
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An examples
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Good Resources Must Read
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Where are we focusing
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Digital Design Methodology
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From concept to reality
A long tiring process
http://nigamanth.net/vlsi/category/asic-design-flow/
Design Methodology: Big Picture
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Design Methodology: Big Picture
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MRD MarketingRequirement
Document
Arch. Spec.
(Macro
Architecture)
DesignSpecificationMicro
-Architecture &
Design Partition
Design Entry
HDL
SimulationFunctionalVerification
DesignIntegration &
Verification
Pre synthesisSign-Off
Synthesize &Map Gate-Level
Netlist
Post synthesisDesign
Verification
Test Generation& Fault
Generation
Clock Trees
Cell Routing
Verify Physical &Electrical Design
RulesExtract ParasiticDesign Sign-Off
Design Methodology
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Design Methodology
A list of desirable features
Studies
Customers expectations
Competing Products
Add-ons
Market opportunities
Time to market
Projects revenue estimates
Profit Margins
Evaluation
Architecture at a very high and
abstract level
Usually a transaction level
model (TLM) Defines communicating
processes
Events may not be defined
Marketing Requirement
Document (MRD)
Architecture Specification
Macro Architecture
Sample
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Sample
Architecture
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Architectural Spec : Another Example
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Architectural Spec : Another Example.
Design Methodology
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Design Methodology
Going deeper into design
Partitioning of functions into
blocks
Clock/reset requirements,
Pipelining of registers
Memory buffers
Algorithm State Machines (like
flowcharts)
State machines and interfacedetails.
State Transition Graphs
Timing Charts
FUs defined by their behavior
Interacting functional units
Control vs. datapath separation
Interconnection structures within
datapath
Top-down design method
Exploiting hierarchy
Design Reuse
This document is very crucial, for alarge team working on various
modules of the same design.
Design Spec/Micro Architecture / Design Partition
Design Methodology
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Design Methodology
HDL
Higher productivity thanschematic based gate levelimplementation
Easier to Debug, Modify & Update De-burdens gate level
optimizations
Allows this stage to be technologyindependent (e.g., FPGA LUTs orASIC standard cell libraries)
Behavioral descriptions
Simulation vs. Formal
Methods
Test Plan Development
What to test & how ? E.g: Instruction set for a range of
data
Testbench Development
Testing of independent modules
Test Execution and Model
Verification
Meets Specification ?
44Design Entry/ HDL
Simulation and Functional
Verification
Design Methodology
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Design Methodology
Integrate
Bugs lurking in the
interface behavior
among modules
The Testbench
I/O interfacing with top
level moduleMonitor port & bus
activity across module
boundaries
Full functionality
Demonstrated
Make sure thatthe behavior
specification meets thedesign specification
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Design Integration and
VerificationPre synthesis sign-off
Design Methodology
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Design Methodology
Synthesize the design fromthe behavior description
Optimized Booleandescription
Map onto target technology Optimizations
Minimize logic
Reduce area
Reduce power
Balance speed vs. otherresources consumed
Produces netlist of standardcells or database to configuretarget FPGA
Comparing Synthesized gate-
level description to the
verified behavioral model
A testbench that instantiatesboth models & drive them via
common stimulus
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Gate-Level Synthesis and
Technology Mapping
Post-synthesis Design
Validation
Design Methodology
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Design Methodology
Are the timingspecifications met?
Are the speeds adequate
on the critical paths? Re-synthesis may be
required to achievetiming goals
Resize transistorsModify architecture
Choose a different targetdevice or technology
Test Generation and Fault
Simulation
Placement and Routing
Clock distribution trees tominimize skew
Physical and Electrical
Design Rule Check
Determining Parastics Extract geometric
information
47
Post synthesis Timing
VerificationASIC Specific
Design Methodology: Big Picture
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Design Methodology: Big Picture
48
MRD MarketingRequirement
Document
Arch. Spec.
(Macro
Architecture)
Micro-Architecture& Design Partition
Design Entry
HDL
SimulationFunctionalVerification
DesignIntegration &
Verification
Pre synthesisSign-Off
Synthesize &Map Gate-Level
Netlist
Post synthesisDesign
Verification
Test Generation& Fault
Generation
Clock Trees
Cell Routing
Verify Physical &Electrical Design
RulesExtract ParasiticDesign Sign-Off
ASIC Specific
d
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Reading Assignment
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Relevant sections of Chapter-1 [SHO]
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Questions.