Advanced Digital CircuitsECET 146

Week 6

Professor Iskandar Hack

ET 221G, 481-5733

hack@ipfw.edu

Me as I typed this slides

This Week’s Goals

Adding a Time Delay to a Simple Finite State Machine

Designing a Simple Control System using AHDL with a FSM

Time Delay Function

This is a separate project that allows the designer to specify a particular amount of time (in clock cycles) that the main project will remain in a particular state

This project has as it’s inputs clk, reset, nsec (the number of clock cycles to remain in that state) and start

The only output of this project is te (time expired)

SubDesign for timedelay

Can be scaled up orDown depending on Number clock cycles needed

Variable Section for timedelay

Note: we are specifying that we want to keep track ofCount using d-ff’s In this case we’re using 5 dff’s for count

We have 3 states, one waiting to start counting, one to start the counter, and another where we are decrementing count until it reaches zero

Set up for the FF’s used in timedelay

Sets up the clk and reset signal for the state machine ff’s

Sets up the clk and reset signal for the count d-ff’s (note that a dff has a input clrn not that we use !reset (the ! Symbol inverts the reset signal

The Case Statement

This is similar to programming languages in that you can look a particular signal and determine what you want the logic do based on the contents of that signal

The syntax is shown on the next slide for the logic in the timedelay function

This case statement is the heart of timedelay

Case Statement in timedelayCASE ss IS

WHEN idle =>te = vcc;if start then ss = startstate;

else ss = idle;end if;

WHEN startstate =>te = gnd;count[].d = nsec[];if start then ss = startstate;

else ss = counting;end if;

WHEN counting =>if start then ss = startstate;else

count[].d = count[].q - 1;if count[].q == b"00000" then

ss = idle;te = vcc;

elsess = counting;te = gnd;

end if;end if;

END CASE;

Waiting for start to go High before counting

Start has gone high, so save the number of clock cycles to delay on the count dff’s and wait for start to go low

In case we want to start counting again

Subtract 1 from the output (q) of the ff’s and place them on the inputs (d) of the ff’s

Check if we’re done, if so take te high otherwise keep counting

Complete TimeDelay Function (cut and paste)

SUBDESIGN timedelay(

clk : INPUT;reset : INPUT;start : INPUT;nsec[4..0] : INPUT;te : OUTPUT;

)VARIABLE

ss: MACHINE WITH STATES (idle, startstate, counting );count[4..0] :dff;

BEGINcount[].clk = clk;count[].clrn = !reset;ss.clk = clk;ss.reset = reset;CASE ss IS

WHEN idle =>te = vcc;if start then ss = startstate;

else ss = idle;end if;

WHEN startstate =>te = gnd;count[].d = nsec[];if start then ss = startstate;

else ss = counting;end if;

WHEN counting =>if start then ss = startstate;else

count[].d = count[].q - 1;if count[].q == b"00000" then

ss = idle;te = vcc;

elsess = counting;te = gnd;

end if;end if;

END CASE;END;

Save, compile and made default symbol for timedelay

Go through the normal steps after copying and pasting the function timedelay into the text editor Save as timedelay.tdf Set project to current file Compile Make default symbol for timedelay

Example Project that uses timedelay

In this project we’re going to go from state s0 to s1 after 5 clock cycles, to s2 after 8 clock cycles and back to s0 after 3 clock cycles.

We’re going to have the following outputs: Y1 – high during s0 Y2 – high during s1 and s2 Y3 – high only during s2

Some points to remember

We have to as outputs from our new project the signals for timedelay (start and nsec)

We have to have an input for te We have to subtract from the variable nsec

one clock cycle for the startstate clock cycle We have to have a unique state to “START”

the timedelay function We have to have a ‘loop-back’ to the same

state until te goes high

Bubble Graph for Simple w/timedelay Design

Table to show State Transistions

Current State TE (the only input that has an effect on table transitions

Next State

S0 X (don’t care) S0a

S0a 0 S0a

S0a 1 S1

S1 X (don’t care) S1a

S1a 0 S1a

S1a 1 S2

S2 X (don’t care) S2a

S2a 0 S2a

S2a 1 S0

Table to show Outputs

Current State Nsec[] START Y1 Y2 Y3

S0 4 VCC VCC GND GND

S0a 4 GND VCC GND GND

S1 8 VCC GND VCC GND

S1a 8 GND GND VCC GND

S2 2 VCC GND VCC VCC

S2a 2 GND GND VCC VCC

SubDesign and Var Sections

Define Clk and Reset for State Machine

State Transition Table in AHDL

Output Table in AHDL

Complete File for Example Part 1

Complete File for Example Part 2

Save and Compile Example

Save as exampleweek6.tdf Compile (ignore warnings)

Create Default Symbol

Start Final Design (uses both timedelay and exampleweek6 Open Graphic Editor and add the inputs,

outputs and the two symbols just designed. NOTE – ALL files must be in the same

directory, don’t create separate directories for the three projects

Final Design Drawing

Note must be a BUS

Save as NEW Project Name

Save drawing as week6final.gdf Change Project to current project Save and Compile Define Device and I/O pins

Simulation

Same as before except you’ll need to change the end time to at least 4.5uS to see complete cycle

Note you can see the internal state machine states along with the count – again helps with troubleshooting non-working designs

Lab 5

Introduction to State Machines and Time Delay

Design using the techniques discussed in class a Finite State Machine (FSM) that will simulate a basic stop light with the MAJOR states shown on the next slide. (You can shorten the times if desired; these times seem to last forever when trying to verify the project)

Please Note that inside each state there needs to be several sub-states that perform the following.

a) Place on the output of the FSM the number of seconds (minus 1) that the FSM is to remain in that state, and sets the start signal high.

b) Removes the start signal (to start the timedelay component), and number of seconds

c) Waits until the TE signal goes high from timedelay d) Please note that during all of these sub-states the outputs have to be

set correctly, this is NOT a computer program that the outputs are set until changed – they must be specified for ALL states and sub-states (look at the example which had s0, s0a for s0)

• Built up the circuit using the Altera Educational Board, remove the onboard clock if present and use a function generator on Pin 2 on the Altera Board for the clock

• Submit a Formal Lab Report using the Standard ECET format

Lab 5 Table