advanced digital design the need for a design style by a. steininger vienna university of technology

Advanced Digital DesignThe Need for a Design Style

by A. SteiningerVienna University of Technology

Lecture "Advanced Digital Design" © A. Steininger / TU Vienna 2

Outline

Skew versus consistency

The need for a design style

Hazards, Glitches & Runts


Design: Boolean Logic

unambiguous functional description

combinational logic: truth table sequential logic: state diagram

technology agnostic

temporal relationsare not relevant (just sequence)


Implementation: Physics

There is a signal delay

in all transistors

through all interconnect

This signal delay

cannot be eliminated

is indeterministicW

hy ?


Fundam. Speed Limitations

EM wave propagationInformation can never travel faster than with speed of light. (20cm/ns)

Charging effectsCharging of a capacitance with limited current takes time. (Dt t = RC)

Charge movementMovement/diffusion of charges in semi-conductor has limited speed. (0,1mm/s)

Fundamental law

of physics

inevitable

material-im

manent


Can we predict Delay?

Gate Delay logic depth (<=optimization & mapping) data dependent delay (dynamic!)

Interconnect Delay geometry (lengths, capacitances) vias, switches crosstalk (dynamic!)

PVT Variations Process variations supply Voltage Temperature


Skew Prediction ?

Signal delay is difficult to predict, it even varies with operating conditions & data.

The delays along two individual signal paths will never be the exactly the same.

The (maximum) difference among two or more signal paths of interest – termed „skew“ – is even more difficult to predict.

?

?


Skew and Consistency

Data consistency When individual data items are interpreted

together, these mustbelong to the same context

they must be temporally correlated x- and y-coordinates of a moving object bits of a data word

Skew distorts temporal correlation


receiving 00 10 11 10 00

Consistency – an Example

sending 00 10 11 10 00

receiving 00 10 11 10 00

receiving 10 10 01 00 00

Delay

Skew


1

& Y = A A 010

A

10

100

DT

Everything OK for the steady stateA dynamic analysis reveals glitches!

Consistency & Glitches


Pulse & Glitch

Pulse: transition followed by opposite one „positive“: „negative:

Pulse width PW: time distance between these transitions

Glitch: spurious pulse, usually undesired

PW

Danger of a Glitch

Glitch becomes dangerous when converted from

spurious to steady state

by using the transition (control signal)

or

by capturing its value (data signal)


Types of Delay

Pure delay (transport delay) simple „time shift“ of all transitions pulses of any width are transported

Inertial delay (component delay) transition only made if still required after delay pulses shorter than the delay are suppressed


D

D

D

D D

pure pure = inertial inertial

Delay types in Reality

Pure delay much related to speed-of-light delay typical for wires with small RC increasing relevance for newer technology

Inertial Delay much related to RC delay typical for gates (& wires with high RC) considered more relevant in practice



Runt Pulses

when decreasing width PW of pulse applied to real circuit, large PW => pulse definitely recognized

small PW => pulse definitely ignored(circuit‘s inertial delay)

for some PW in between output will be very short and not reach full amplitude RUNT pulse

a runt will be marginally recognized (may or may not) by subsequent inputs

VDD

VSS


Design: Boolean Logic

unambiguous functional description

combinational logic: truth table sequential logic: state diagram

technology agnostic

temporal relationsare not relevant (just sequence)

cannot be expressed!


The Consequences

Boolean Logic describes I/O-mapping without consideration of time

This implies continuously consistent inputs

Skew inevitably causes inconsistency at the inputs and hence invalid dynamic outputs

glitches & runts

A B C F

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

A


Just change a single bit at a time, then skew does not take effect

Data permanentlyconsistent

( „Huffman Circuits“)

A

Skew

REALLY?

Why not avoid Skew?


Still glitches…

&

>=1

XYZ

W A&

&

K

L

M

1

11 0

Glitch!

single transition

Forks turn single transitions into multiple ones !

Some First Conclusions…

Boolean Logic is a powerful method for functional description, but

it does not take care of timing issues

Timing issues are relevant, their ignorance leads to glitches, runts and inconsistent data

We need a some form of „discipline“ when designing a real circuit

It makes sense to investigate further into glitches



Combinational Hazard

Potential for glitches to occur in a circuit, depending on relative path delays

Glitch is a manifestation of a hazard in a physical implementation of the circuit

Actual manifestation may depend on input patterns actual delay values (PVT variations)


Types of Comb. Hazards

static 1: input change retains output at 1, but negative glitch occurs

static 0: same for output 0 and positive glitch

dynamic: glitch occurs prior to desired output change


Static 0 Hazard

Fundamental circuit structure:

fork inversion on one lane reconvergent into AND gate

1 & Y = A A 0A


Static 1 Hazard


fork inversion on one lane reconvergent into OR gate

1 Y = A A 1A >=1


Eliminating SC Hazards

How to choose delay constraints ? no solution for constant delays solvable for edge-dependent delay:

: D1 > D2 : D1 < D2

1 &AY

D1

D2


Delay constraints

Absolute timing contraints:

keep skew between different paths within a certain limit

generally not achievable

Relative timing constraints:

keep one path slower than the other

generally possible, particularly in combination with input

restrictions


Detection in Schematics

&

>=1

&

1

>=1

1 &

A

YB

C

D


Detection in Equation

assign input values until B and B remains:

A = 0; C = 0; D = 1(enabling condition, need not exist)

Y = B B

static 0 hazard

Y = [(C D)(B D)] (A B C)


Detection in KV-Diagram

1 1 1 1

1 1

1

A B

C

D

static 1 hazards

1110 1111

0110 0111

remedy: redundant term

static 0 hazards

use KV for Y


F = (X Y Z) (W Z) (W Y)

1 1

1 1

1 1 1 1

1 1

00 01 11 10

00

01

11

10

W

Z

Y

X

YZ

WX

1

W

1 1

1 1 11 1

00 01 11 10

00

01

11

10

Z

Y

X

YZ

WX

F = (X Y Z) (W Z) (W Y)

1 1

Another Example

(Y Z) (W X Y) (W X Z)

A


Systematic Approach

define a notation to describe all scenarios of interest 9-valued logic

study propagation

extended truth table

identify critical input scenarios satisfyability problem


9-valued logic

1 stable high0 stable low rising edge falling edgeS1 static-1-hazardS0 static-0-hazardD+ dynamic hazard, rising edgeD- dynamic hazard, falling edge* any value at all

ordering: S0 > 0, S1 > 1, D- > , D+ >

This is NOT the IEEE 1164 logic!


Truth Table „AND“

& 0 1 S1 S0 D+ D- *

0

1

S1

S0

D+

D-

*


Truth Table „AND“

& 0 1 S1 S0 D+ D- *

0 0 0 0 0 0 0 0 0 0

1 0 1 S1 S0 D+ D- *

0 S0 D- S0 S0 D- *

0 S0 D+ S0 D+ S0 *

S1 0 S1 D- D+ S1 S0 D+ D- *

S0 0 S0 S0 S0 S0 S0 S0 S0 *

D+

0 D+ S0 D+ D+ S0 D+ S0 *

D- 0 D- D- S0 D- S0 S0 D- *

* 0 * * * * * * * *


Propagation Analysis 1

1 &AY

S0

Single Input Change (SIC)

So far: glitch due to single input signal changing

Watch out for reconvergent paths: Fork: put single transition on concurring paths Join: recombine the two transitions, whose

temporal relation has been distracted by skew

If we allow more input signals to change we do not need the fork by moving the relative position of the inputs we

gain even more freedom in arranging adverse timing conditions



Multiple-input change

&

>=1

&

1

>=1

1 &

A

YB

C

D


MIC Detection in Equ.

assign input values for A and B:A = 1; B = 0

Y = C D

static 0 hazard:1000 1011

Y = [(C D)(B D)] (A B C)


MIC Detect in KV-Diag.

1 1 1 1

1 1

1

A B

C

D

There is a shortest path leading over other logic value

„functional hazard“

cannot be eliminated


Handling Static Hazards

Elimination add terms (in sum-of-products implem.)

not always possible for MIC

Defeating disallow enabling conditions disallow critical transition(s)

restriction of operation add timing constraints

needs to be asymmetric

Filtering (i.e. adding inertial delay) limited effect only, slows down circuit


Dynamic Comb. Hazard


1 &A >=1

edge producer

glitch producer (010)


Dynamic Comb. Hazard

Fundamental circuit structure (dual):

1&A

>=1

edge producer

glitch producer (101)


Dynamic combin hazards

safe if D1 < D2 or D3 < D1

(no glitch) (edge masks glitch)

safe if D1 > D2 or D3 > D1

all safe if D1 > D2, D3 or D1 < D2, D3

1 &A >=1

D1

D2

D3


Extension to MIC

1 &A >=1

1 &A>=1

B

C


Dynamic Hazards ?

&

>=1

&

1

>=1

1 &

A

YB

C

D


Handling Dynamic Hazards

Elimination not always possible for MIC

Defeating relative constraints sufficient!

in complex circuits unclear if constraining always possible: constraints may be contradicting BUT not all input patterns occur

disallow enabling patterns disallow critical transitions

Filtering


What about „real“ HW?

z

A

A

B

B

C

C

A

B

C

z

&

>=1

Switching involves 2 transistors per input

Þ even more delay path combinations (p-stack, n-stack)

Þ may lead to tristate, short, glitch,…

Þ proper cell layout is crucial!

Example AOI gate:


So why a Design Stlye?

Skew is inevitable and unpredictable

It causes inconsistent transient states

Their logic evaluation causes runts & glitches

These are harmful if converted to stable states

There are methods to detect and prevent glitches; those are far from perfect

Specific precautions are needed, as Boolean Logic does not help here

we need some discipline, a design style

© A. Steininger & M. Delvai / TU Vienna 49Lecture "Advanced Digital Design"

Without a Design Style…

…combinational gates may, due to race conditions, receive contradictory signals „simultaneously“ on different inputs, hence

create glitch or runt pulses that may

be converted into erroneous stable states or

even cause metastability in storage loops.

These glitches, runts and/or manifestations of metastability may propagate, and

they may be subject to „Byzantine“ inter-pretation, causing further erroneous states.

advanced digital design the need for a design style by a. steininger vienna university of technology

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