advanced simulation and prototyping solution
TRANSCRIPT
Advanced Simulation and Prototyping Solution shortest path from imagination to verified hardware for physical system design
Jason Chen
Application Engineer
Keysight Technologies
1
Page
SystemVue: Unified Architecture for ESL PHY Design
2
C++
Target Flow RTOS
Synthesis Target Processor IDE/Tools
Implement (S/W app)
Implement (custom H/W)
Implement (targeted S/W)
Electrical (circuit) Design
Physical Design Assembly / Fab
General Purpose
Embedded
Open algorithmic modeling interface: math/MATLAB, C++, HDL
PHY system integration and verification
SystemVue: Cross-domain framework for Model-Based Design
Mainstream EDA Flows
Fixed-point
VHDL / Verilog ANSI-C or C++
RF EDA Flows
FPGA/ASIC
Embedded
DSP
Embedded
Detailed Specs &
Test Benches
RF Systems PHY IP
Complete a working PHY using combinations of Software, RF/BB Hardware, Simulation, and Measurements
Test
Page
PART I. Advanced Modem Library for 5G Communications
3
Page
5G Radio Access Candidate Technologies
New Air Interfaces
• Non-orthogonal waveforms
• FBMC, GFDM
• NOMA
• Full Duplex
Advanced Modem
Library for 5G
Communications 4
New Network Architecture
Massive MIMO New Spectrum Bands
• Legacy Spectrum < 6 GHz
• Higher mmWave bands
• Channel modeling
No cell edge effect. Uniform user
experience
Explore multiuser and spatial gain
Page
Non-orthogonal Waveforms
Motivations
- To overcome the drawback of OFDM that dominates LTE and WLAN
standards to meet 5G requirements.
Key Merits
- Lower out of band radiation to avoid interference
- Lower PAPR (peak-to-average-power ratio)
- Higher spectral efficiency
- Higher flexible frequency allocation
- Reasonable performance at cell edges
- Better robustness for time/frequency synchronization
Advanced Modem
Library for 5G
Communications 5
Basic Concepts
Page
Non-orthogonal Waveforms
Filter Banks Multi-Carrier (FBMC)
Generalized Frequency Division Multiplexing (GFDM)
Non-Orthogonal Multiple Access (NOMA )
Universal Filtered Multi-Carrier (UFMC)
Sparse Code Multiple Access (SCMA)
Advanced Modem
Library for 5G
Communications 6
Candidates
Page
FBMC (Filter Banks Multi-Carrier) Fundamental
– Prototype filter shifted and applied to other active sub-carriers
Advanced Modem
Library for 5G
Communications 7
Sub-Channel Frequency Response
Page
FBMC (Filter Banks Multi-Carrier) Fundamental
Advanced Modem
Library for 5G
Communications 8
Figure. OFDM vs. FBMC Spectrum
Using different filter overlap factor
Figure. FBMC Fragmented Spectrum
• Features and Advantages
• Suitability for fragmented
spectrum due to spectrally well
shaped prototype filter
• No interference with offset-QAM
modulation
• No Cyclic Prefix
• No requirement strict
synchronization
• Disadvantages
• Higher complexity
• Signal extension in burst
transmission due to filter dealy
Page
OFDM vs. FBMC Spectrum in Spectrum Analyzer
Advanced Modem
Library for 5G
Communications 9
• Lower out of band radiation for FBMC
• No guard needed for FBMC
FMBC Spectrum (10MHz bandwidth, no guard)
LTE OFDM Spectrum (9MHz bandwidth + 1MHz guard )
Page
OFDM vs. FBMC Implementation
Advanced Modem
Library for 5G
Communications 10
IFF
T
P
/ S
S / P
FF
T
Sym
bo
l
map
pin
g
Sub
-ca
rrie
r
map
pin
g
Sub
-ca
rrie
r
de
-mappin
g
Sym
bo
l
de
-mappin
g
OFDM baseband signal processing blocks
OQ
AM
pre
pro
cessin
g
IFF
T
Poly
Phase
Netw
ork
P
/ S
S / P
Poly
Pha
se
Netw
ork
FF
T
OQ
AM
post pro
cessin
g
Synthesis Filter bank Analysis Filter bank
Sym
bo
l
map
pin
g
Sub
-ca
rrie
r
mappin
g
Sub
-ca
rrie
r
de
-mappin
g
Sym
bo
l
de
-mappin
g
FBMC baseband signal processing blocks
Another FBMC implementation is so-called extended-FFT with longer IFFT operation
Page
FBMC Signal Generation in SystemVue
Advanced Modem
Library for 5G
Communications 11
FBMC Source Features:
• Preamble symbols, data and pilots
symbols
• OQAM modulation
• Extended-IFFT and PPN-IFFT
implementation
• Prototype filter with different overlapping
factor and filter coefficient
Data and Pilot Insertion
Preamble Insertion
IFFT
PPN Framing
OQAM
Modulation
IdleInterval
Insertion
Page
FBMC Signal Receiver in SystemVue
Advanced Modem
Library for 5G
Communications 12
FBMC Receiver Features:
• Timing & frequency synchronizition
• Channel estimation and equalization
• Extended-FFT and PPN-FFT
• Phase tracking by pilots
• OQAM demodulation
FBMC BER Performance
Timing and Freq Sync Frame Demux
OQAM
Demodulation
Channel Estimation
FFT Channel
Equalization
Phase
Tracking
Complex
Combiner
Preamble Removing
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MIMO & Beamforming Supports in SystemVue
• New multi-channel processing models
- MultiCh_Modulartor, MultiCh_Demodulator
- MultiCh_AddNDensity
• New advanced algorithm models
- Tx Beamformer
- Rx Beamformer
- MIMO Coding and Decoding
• Massive MIMO capacity evaluation
• New 3D MIMO channel modeling
- To be extended to support Massive MIMO and mmWave channel
Advanced Modem
Library for 5G
Communications 13
Page
Tx_Beamformer: flexibly configure antenna
array and desired direction to form tx
beamforming pattern
Rx_Beamformer: form rx beamfroming
pattern to extract desired signal by SMI or
LMS
Tx & Rx Beamformer
3D Antenna Pattern Display in SystemVue
Advanced Modem
Library for 5G
Communications 14
Page
Adaptive Beamforming Example in SystemVue
Advanced Modem
Library for 5G
Communications 15
Evaluate Adaptive Rx Beamforming Performance
Wanted
Signal
Interferences
Channel
Tx
Beamformer
Rx
Beamformer
Coding,
Modulation
Demodulation,
decoding
BER,
Throughput
Page
Advanced MIMO Encoder and Decoder
• STC (Space Time Coding)
• Alamouti coding, decoding (compatible with
LTE)
• SM (Spatial Multiplexing)
• Linear (ZF and MMSE)
• SIC (Successive Interference Cancellation) (ZF
and MMSE)
• ML (Maximum Likelihood)
Advanced Modem
Library for 5G
Communications 16
MIMO_DecoderRecoveredData
ModType
ChannelResponse
ReceivedData
DebugFlag=0
DecoderMethod=Linear ZF
Mode=Spatial Multiplexing
M4 {MIMO_Decoder@5G Advanced Modem Models}
MIMO_Encoder
NumTx=2
Mode=Spatial Multiplexing
M1 {MIMO_Encoder@5G Advanced Modem Models}
Page
MIMO Decoding Performance Simulation
• MIMO Tx/Rx simulation under Rayleigh
fading channel or AWGN channel
• Explore different decoding algorithms with
performances in order (from best to worst)
• ML, MMSE-SIC, ZF-SIC, MMSE-Linear,
ZF-Linear
Advanced Modem
Library for 5G
Communications 17
Evaluate Different MIMO Decoding Performance
Tx
Channel Gen AWGN Gen MIMO
Decoder Demapper
Page
Received signal at UE k:
The challenge for MU-MIMO is to find orthogonal
users and design precoding W to minimize the
second term with the restrictions of user grouping,
power, latency and complexity
Multiuser-MIMO
Advanced Modem
Library for 5G
Communications 18
Capacity Comparison
SU−MIMO: 𝑀𝑙𝑜𝑔(1 + 𝑆𝑁𝑅)
MU-MIMO: 𝑀𝑙𝑜𝑔 1 +𝑆𝑁𝑅
𝑀𝑙𝑜𝑔𝑈 , 𝑈 → ∞
M: TX antenna number
U: Total user number
MU-MIMO Scenario
Page
Advantages/Disadvantages of MU-MIMO
– Advantages:
• Multiple access capacity gain (proportional to BS antennas)
• More immune to propagation limitations such as channel rank loss, antenna
correlation and LOS
• Maintain spatial multiplexing gain without large antenna number at
terminals
– Disadvantages
• BS needs to know channel state information at transmitter (CSIT). The
challenges include
- TDD vs. FDD for CSIT
- CSI feedback path bandwidth, Code book design
• Complexity of the scheduling procedure at BS
- User grouping scheduling, power allocation and latency requirements
Advanced Modem
Library for 5G
Communications 19
Page
MU-MIMO Capacity Simulation in SystemVue
Advanced Modem
Library for 5G
Communications 20
Random Channel Generator User Scheduler Capacity Measurement
– Transmit antenna number (M) is 4; Total
user number is from 4 to 100
– SNR=10dB
– Power allocation by waterfilling algorithm
Users U: 4->100
Sum
Cap
acity
Page
LTE-Advanced 3D Channel Modeling
Advanced Modem
Library for 5G
Communications 21
Explore elevation dimension with 2D antenna array
– More accurate to simulate real
world with 2D antenna array by
considering elevation
– Mandatory for 3D beamforming
and MIMO scenario
– Follow 3GPP TR 36.873
– Features:
• New 3D scenario
• New Antenna modelling
• New Elevation parameters
• Coordinate system
Page
LTE-Advanced 3D channel model in SystemVue
Advanced Modem
Library for 5G
Communications 22
Follow 3GPP TR 36.873
Custom
antenna
pattern input
3D channel
scenario
Page
LTE-Advanced 3D channel model in SystemVue
23
LTE-A Throughput Simulation under 3D MIMO Channel
• Support of customer antenna
patterns input to measure the
performance under different
patterns
• In left curve, the throughputs
match well with the antenna
performances
Good
Antenna
Normal
Antenna
Bad
Antenna
Tx
3D Channel
Rx
Advanced Modem
Library for 5G
Communications
Page
PART II. Integrated Design Flow for Digitizer
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Page
Integrated Hardware Design Flow for Digitizer
– Realization of rapid real time application development for high performance wideband digitizer
• Integrated design flow for algorithm design, simulation, hardware design & implementation
• Custom algorithm design and software level simulation
• M9703A_Template design
• Hardware co-simulation with M9703A_CoSim model
• One push button approach for the bit file generation and FPGA programming
25
W1717 Behavioral Fixed pt
Digitizer FPGA Development
Kit Integration
W1461 Algorithm/Floating pt
RTL-level
VHDL, Verilog
MODEL-BASED DESIGN FLOW
Enterprise FPGA
Tools HW
Implementations
Continuous top-down
verification
W1462 FPGA Architect
M9703A Real Time Co-Sim
MO
DE
L-B
AS
ED
V
ER
IFIC
AT
ION
Integrated design
flow for digitizer
Page
Key Technology Innovations and Differentiations
Advanced architecture and design flow for
- Seamless SystemVue and Modular instrument integration
- Automatic FPGA implementation
- Rapid prototyping
- IP reuse
IPs to enable the above architectures
26
Firmware
and API
design
Circuit design System algorithm
design and verification Application and
display design
Typical period is couple years
Example MIMO Prototype system development
A
P
I
D
R
V
A
P
I
D
R
V
Whole system
design in
SystemVue
Automatic
FPGA
implementation
Seamless fast
prototyping
Agilent IPs and interfaces with automated generation
Integrated design
flow for digitizer
Page
Key Benefits of the integrated design flow
• Early development of Firmware/Software APIs before HW arrives
• Standard conforming baseband stimulus and response metrology
• Simplify complex post analysis
• Overcome function test limitation of a timing based simulator
• Real world system level simulation
27
Making the impossible possible
March 17, 2015
Integrated design
flow for digitizer
Page
Early development of Firmware/Software APIs
28
ADC
ADC
Register Block Reg
DDR MEM
DDR MEM
FPGA MathLang
corr_factor3
phase_factor3
mag_factor3
IN1
IN3
M9703_TEMPLATE
SYSTEMVUE
• Basic module configuration and control.
• Low-level functions for register-based I/O.
• Low-level functions for block-transfers to and from the FPGA and associated memories.
• Higher-level APIs for controlling the FPGA
C++ Custom Model Builder
Custom Application and API
REAL HARDWARE
Integrated design
flow for digitizer
Page
Standard conforming baseband stimulus and response metrology
29
3G/4G MOBILITY
LTE-Advanced (Rel 10)
LTE (Rel 8,9)
WCDMA, HSPA+,
CDMA, CDMA2000
GSM, EDGE
LOCAL
CONNECTIVITY
WPAN / 802.15.3c
802.11ad
Zigbee / 802.15.4
Bluetooth
Available with W1461BP
core environment
NETWORKING
WiMAX / 802.15e
WLAN /802.11abgn/ac
60GHz 802.11ad
Custom OFDM
BROADCAST &
SATCOMM
DVB-S2/T2, ISDB-T
General Digital Modem
GNSS sat nav
DEFENSE
RADAR: PD, UWB, FMCW,
SAR, DAR, SFR, MIMO,
Phased Array
SystemVue “Baseband Verification” Libraries
m2
m3
Soft bits demappingand metric calculation
Path-metric calculationand selection ofsurviving paths
Reversing the orderof decoded bitstream to
match the input
Counterand reset
signals
Reverse extraction ofdecoded bitstream
PM_calc_all_T1
dec0
dec1
dec2
dec3
m2
m3
reset
PM_calc {PM_calc_all_T1}
Delay=3
IntegerWordlength=18 [intwl_PM]
Wordlength=32 [wl_PM]OutputPrecisionMode=User Defined
IntegerWordlength=18 [intwl_PM]Wordlength=32 [wl_PM]
OutputPrecisionMode=User Defined
PORT=1Q_Phase
0
OutputPrecisionMode=User Defined
PORT=2I_Phase
IsSigned=Signed
IntegerWordlength=18 [intwl_PM]Wordlength=32 [wl_PM]
IsSigned=SignedIntegerWordlength=18 [intwl_PM]
Wordlength=32 [wl_PM]
D19
1
OutputPrecisionMode=User Defined0
OutputPrecisionMode=User Defined
1
OutputPrecisionMode=User Defined
0
OutputPrecisionMode=User Defined
D15
PathToRevBits
RevBitsOut
DecisionIn_0
DecisionIn_1
DecisionIn_2
DecisionIn_3
DownCntRead
UpCntWrite
reset
PathToRevBits {PathToRevBits}
En
Rst
0 1
Direction=Up
En
Rst
0 1
Direction=Down
A?BB
A
CompareOperation=Equal
RAM Data
WrtEn
AddrRe
AddrWr
Depth=64 [cntlen]
1
OutputPrecisionMode=User Defined
D14 D13
PORT=3
BitsOut
SystemVue Hardware Design
Data type conversion
Floating/Fixed Point
Integrated design
flow for digitizer
Page
Simplify complex post analysis
• Fixed to floating point data conversion
• FFT, Filtering, Re-sampling
• Time / Frequency domain conversion and plotting
• Send out data from SystemVue to user application
for further processing and display
30
FFT
FreqSequence=0-pos-neg
Direction=Forward
Size=256
FFTSize=256
F1 {FFT_Cx@Data Flow Models}
MathLang
corr_factor3
phase_factor3
mag_factor3
IN1
IN3
Length=64
R1 {ResamplerRC@Data Flow Models}
Integrated design
flow for digitizer
Page
Overcome function test limitation of a timing based simulator
• Traditional analog functions are being moved
to DSP - DUC, DDC, DDS, Beam Former, etc…
• Need more than timing & logic analysis
• How many FPGA designer can see vector
analysis results during HDL coding and
verification in traditional design flow?
31
RTL Simulator
Agilent 89600 Vector Analysis Software
Integrated design
flow for digitizer
Page
Real world system level simulation
32
Soc k etServerModel
t _sys_valid
dc_m ar k_sel
t _sys_r d
t _dig_r d
sys_addr
scl_out
dig_addr
dig_dat a
scl_in
dc_enable
t _dig_valid
sys_dat a
scaling=Register Value
Server_IP=
Port=13441
S5 {SocketServerModel@SocketServer Models}
GNCO
Sin
sys_r ead
Cos
r eg_r ead
angM odDat
sys_addr
scaleDat
r eg_valid
sys_dat a
M r k2
dc_m r ksel
M r k5
M r k4
CClk
Fr eq
r eg_addr
M r k1
r eg_dat a
dc_enable
sys_valid
M r k0
M r k3
Phase
MarkMode5=All Samples
MarkMode4=All Samples
MarkMode3=All Samples
MarkMode2=Toggle on Mark
MarkMode1=Marked Samples
MarkMode0=Toggle on Mark
Subnetwork1 {GNCO}
1 1 0 1 0
B1 {RandomBits@Data Flow Models}
T
SampleRate=240000Hz [SamplingRate]
S3 {SetSampleRate@Data Flow Models}
DigitalMod
WorkMode=Continuous
BitOrder=MSB
OversampleRatio=40 [OVSR]
BT =0.3
L=5 [Lpulse]
FreqPulse=GMSK [freq_pulse]
h=0.7 [h]
M_ary=2 [M_ary]
ModType=M-ary CPM
D2 {DigitalMod@Data Flow Models}
CDMA
BER
Ini=8
C3 {CDMA_BER@CDMA Models}
Re
Im
R1 {RectToCx@Data Flow Models}
Mag
Phase
C1 {CxToPolar@Data Flow Models}
123
StartStopOption=Samples
CPM_Phase {Sink@Data Flow Models}
123
StartStopOption=Samples
CPM_Wave {Sink@Data Flow Models}
Spectrum Analyzer
ResBW=100Hz
Spec_RF_TX {SpectrumAnalyzerEnv@Data Flow Models}
VSA_89600B_Sink
VSATitle='Simulation output
V1 {VSA_89600B_Sink@Data Flow Models}
0
Value=0
C2 {Const@Data Flow Models}
Periodic=YES
Offset=0V
Explic itValues=(2x1) [1; 0]V
W1 {WaveForm@Data Flow Models}
Digital I/Q
BB Modulation
Demod & BER
TCP/IP client and
data streaming
(control channel from Test Exec)
FPGA Model
Measurement and verification of an FPGA model requiring
complex metrics in the presence of real world impairments.
Integrated design
flow for digitizer
Page
Real Time Signal Processing in FPGA
33
AD DDC FIR
W Φ
∑
AD DDC FIR
W Φ
AD DDC FIR
W Φ
AD DDC FIR
W Φ
Adaptive Algorithm
I
Q
BE
AM
S
FPGA RF Front End
∑
𝑑[𝑘] 𝑒[𝑘]
𝑦[𝑘]
+ − SpectraSys RF Modeling
BB Processor
SystemVue System Level Simulation Complex Weight Wk update
AD DDC FIR
W Φ
∑
AD DDC FIR
W Φ
AD DDC FIR
W Φ
AD DDC FIR
W Φ
Adaptive Algorithm
I
Q
BE
AM
S
∑
𝑑[𝑘] 𝑒[𝑘]
𝑦[𝑘]
+ −
• Hardware implementation for digital down conversion and filtering
• Adaptive beam forming algorithm to update weighting vector on the fly
Adaptive Digital Beam Forming Signal Processing
Integrated design
flow for digitizer
Page
Realistic Digitizer Application Example
– What is difference between channels?
34
Phase & magnitude correction for multi-channel digitizer
RF
Module
RF
Module
RF
Module
IF
ADC
ADC
ADC
sin 2𝜋𝑓1𝑡
sin 2𝜋𝑓1𝑡
sin 2𝜋𝑓1𝑡
𝐴2(𝑓1) ∗ 𝑒𝑗𝜙2(𝑓1)
𝐴1(𝑓1) ∗ 𝑒𝑗𝜙1(𝑓1)
∗ A1(𝑓1)
A2(𝑓1)𝑒𝑗(𝜙1(𝑓1)−𝜙2(𝑓1))
𝐴3(𝑓1) ∗ 𝑒𝑗𝜙3(𝑓1) ∗ A1(𝑓1)
A3(𝑓1)𝑒𝑗(𝜙1(𝑓1)−𝜙3(𝑓1))
Wide band digital receiver
DDC
DDC
DDC
Physical Path Gain
RF
Module ADC sin 2𝜋𝑓1𝑡 𝐴4(𝑓1) ∗ 𝑒𝑗𝜙4(𝑓1) ∗
A1(𝑓1)
A4(𝑓1)𝑒𝑗(𝜙1(𝑓1)−𝜙4(𝑓1)) DDC
I
Q
I
Q
I
Q
I
Q
Multi-channel RF inputs
Integrated design
flow for digitizer
Page
Realistic Digitizer Application Example
– Signal processing
35
Phase & magnitude correction for multi-channel digitizer
Trigger
Sequence 𝒔𝒊𝒏 𝟐𝝅𝒇𝟏𝒕 𝒔𝒊𝒏 𝟐𝝅(𝒇𝟏 + Δ𝒇)𝒕 𝒔𝒊𝒏 𝟐𝝅(𝒇𝟏 + 𝟐Δ𝒇)𝒕 …… 𝒔𝒊𝒏 𝟐𝝅𝒇𝟐𝒕
Trigger
Sequence 𝒔𝒊𝒏 𝟐𝝅𝒇𝟏𝒕
…
[ A1(𝑓1)
A2(𝑓1)𝑒𝑗(𝜙1(𝑓1)−𝜙2(𝑓1)),
A1(𝑓1+Δ𝑓)
A2(𝑓1+Δ𝑓)𝑒𝑗(𝜙1(𝑓1+Δ𝑓)−𝜙2(𝑓1+Δ𝑓)) , …… ,
A1(𝑓2)
A2(𝑓2)𝑒𝑗(𝜙1(𝑓2)−𝜙2(𝑓2)) ]
IFFT
Phase & magnitude calculation
FIR filter coefficients update
Single period of reference signal
Integrated design
flow for digitizer
Page
Realistic Digitizer Application Example
– Block diagram
36
Phase & magnitude correction for multi-channel digitizer
Halfband
FIR1
1.6GSaPS
- >
800MSaPS
Halfband
FIR2
800MSaPS
- >
4 00MSaPS
Halfband
FIR3
400MSaPS
- >
2 00MSaPS
Halfband
FIR1
1.6GSaPS
- >
800MSaPS
Halfband
FIR2
800MSaPS
- >
4 00MSaPS
Halfband
FIR3
400MSaPS
- >
2 00MSaPS
FPGA1
c os
sin
NCO
c os
sin
NCO
FPGA0
Complex
FIR Filter
FIR Filter
Complex
Reference
Channel
Calibration
Channel
Calculate
FIR
Coefficients
Wk
Wk
Integrated design
flow for digitizer
Page
M9703A application development using SystemVue
37
Integrated design
flow for digitizer
Page
Summary: Keysight SystemVue For PHY system architects and baseband algorithm developers
38
Improved productivity
through RF/BB model-based
design
Provides ESL design cockpit
for comms/defense systems
Enhances Baseband modeling
with areas of Keysight leadership
in
RF, Test, and Communications IP: • superior cross-domain effectiveness
• earlier design maturity
• higher performance, lower margins