AD-A253 334

RL-TR-92-1 1Final Technical ReportFebruary 1992

ADVANCED TECHNOLOGYCOMPONENT DERATING

DTICAf ELECTE

J U L #0 4 1992Westinghouse Electronic Systems Group ATimothy A. Jennings

APPR1:O VED FOR PUS I, 47LEAS S•" DITR8IUT70N UNIALIM/TED,

92-19900

Rome LaboratoryAir Force Systems Command

Griffiss Air Force Base, NY 13441-5700

. ,..I

This report has been reviewed by the Rome Laboratory Public Affairs Office(PA) and is releasable to the National Technical Information Service (NTIS), At NTISit will be releasable to the general public, including foreign nations.

RL-TR-92-11 has been reviewed and is approved fcr publication.

APPROVED: ý/Vn14 J~ /A) 51t2TYA4AD

TIMOTHY J. DONOVANProject Engineer

FOR THE GO~mANDER:

JOttN J. BART, Chief ScientistReliability Sciences

If your address has changed or if you wish to be removed from the Rome Laboratorymailing list, or if the addressee is no longer employed by your organization, pl•.asenotify RL( ERS!• ) Griffiss AF!ý, NY 13441-5700. This will assist us in maintaining acurrent mailing list.

Do riot return copies of this report unless contractual obligacions or notices on aspecific document require that it be returned.

FomApprovedREPORT DOCUMENTATION PAGE MB No. 0704-0188P•Mt mP'l burman my Is ct-lian ai-l ct KUTmra2 Is vsbr• • wavewva in. hs •orww tudnq u'm fto rw ru•vAbwfi hgb-a swd*trg sc• "a sotgaflt-wr n =rrtt ttg l dan r a-wi/ cr qflt - witn rmdwmt, frsca-nn'sutm df kl-muam SfnlCYTTTmrtU r'dw' r, k bsf,• a,-,. s es w a-w c=tw t ,z=e ci its

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1. AGENCY USE ONLY (Leave Bl.nn. 2-. RPORT DATE a REPORT TYPE AND DATES COVEREDFebruary 1992 Final Jun 89 - Sep 91

4. TITLE AND tiUBTITLE 5. FUNDING NUMBERS

ADVANCED TTCHNOLOGY COMPONENT DERATING C - F30602-89-C-0095PE - 62702F

6. AUTHOR(S) PR - 2338TA - 02

Timothy A. Jennings WU - 4G

7. PERFORMING ORGANIZATION NAME(S) AND ADDRE$S(ES) a PERFORMING ORGANIZATION

Westinghouse Electronic Systems Group REPORT NUMBERFriendship SiteBo:: 746 N/ABaltimore ND 21203

9. SPONSOR!NG/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSORINQ/MONITOHINGAGENCY REPORT NUMBER

Rome Laboratory (ERSR)Griffiss AFB NY 1344L-5700 RL-TR-92-11

11. SUPPLEMENTARY NOTESRome Laboratory Project Enginecr: Timothy J. Donovan/ERSR/(3!5) 330-2608

12a. DISTRIBUT1ON/AVAJLABILfUTY SATEMENT 12b. DISTRIBUTION CODE

Approved for public release; distribution unlimited.

13. ABSTRACTQ.4uun~2m-cThis report has been piepared to sumnaariza the tecbnical study performed to determinethe derating criteria of advanced technology components. The study covered existingcriteria from AFSC Pamphlet 800-27 and the dcvelopment of new criteria based on data,literature searches and the use of advanced technology prediction methods developedin RADC-TR-90-72. The devices that were investigated were: VHSIC, ASIC, MIMIC,Microprocessor, PROM, Power Transistors, P" Pulse Transistors, RF Multi-TransistorPackages, Photo Diodes, Photo Transistors, Jpto--Electronic Couplers, Injection LaserDiodes, LED, Hybrid Deposited Film Resistors, Chip Resistors and Capacitors and SAWdevices. The results of the study are additional derating criteria that extend therange of AFSC Pamphlet 800-27. These data will be transitioned from the report toAFSC Pamphlet 800-27 for use by government and contractor personnel in deratingelectronics systems yielding increased safety nargins and improved system reliability.

14. SUBJECT TERMS i1 NUMBER OF PAGES

Reliability, VHSIC, Galium Arsenide (GaAs), FailurAý Rate, _98De it Ia PRICE CODE_Derat ing ___20____

17. SECURITY CLASSIFICATION 1 a SECJRFIY CLASSIFICAIIOrJ 14. SECURITY CLASSIFICATION 20. UMITATION OF ABSTRACIOF REPORT OF THIS PAGE OF ABSTRACT

UNCLASSIFIED UNCLASSIFIED IUNCLASSWTrED ULNIN 754001 4MStnwo F Brn 298 (Rev 2.89)

Plabo•be by ANSI Ste Z39,162WI 02

TABIE oF mw=~T

PAGE

1.0 EXECUTIE SLEMQWR 1

1.1 cbjective 1

1.2 Bac]hXmur3 2

1.3 Aproach 3

1.4 List of ALcLonynts 10

2.0 REP01U ORGANIZATICtV 11

3.0 ADVANCED TECI)WGY OXrkNT DERLT1M 12

4.0 N3ICFO=flIJI EERATfl CfLYEINET S 26

4.1 ASIC/VHSi.C Microcircui-t-- 34

4.2 Microprocessor Microcix'dits 58

4.3 amU m4icrocircuits 75

4.4 Application No~teS 87

5.0 NIMMC DEIAW12xG tJID L'MP 89

6.0 POWE TRANSISIOR Dý" ýý CJID=LTS 97

6.1 Silicin Transistors 97

602 Gak.- Transistors 105

3 MF77rs 114

7.0 PF TRANS=XSDZ URýVD rjfG jqý 119

80OPIC-EIX,0MIC1c iF71CE DERATING GJTDELTNES 127

5.0.0 SAW LEMA-T2: G3IDEZIN' 135

211.0 LIERAa'nM VERIFCATON 138

12.3 ALTERNAT APPROC0 TOX SIRýES DER7ITIG 143

13.0 SUMMfvARY 149

14,0 13BT U(ZAMN{ 151Acc:ý,joo Fo,"

Apeudix A DL7RTTNG GUf~I=1iEN EujMMARY r IiS C R4&B SO~~RE I~AD LC lAB

Ju tdIu atoI nce Li

Dit.iu~o ........................ ....... ........ .......

AvWjiabIoitv :c InDis Aw L, Li

LIST OF 1IUSTlATIONS

FIGURERA

3-1 Fl1ddirt of Technical APNzOac" 14

4-1 C1 Factor for M-X Digital Microcircuits 36

4-2 C1 Factor for Bipolar Digital Microcircuits 37

4-3 C1 Factor for MDS and Bipolar Linear Microcircuits 38

4-4 Package Pin Comnt for M(S Digital Microcirrcuits 39

4-5 Package Pin Oo.int for Bipol3r Digital Microcirc'its 40

4-6 Package Pin Coumt for MS and Bipolar Linear MicrocirQUits 41

4-7 Trasmistor Gate Area for MS Digital and Lliear Microcircults 42

4-8 Dielectric Thickness for Ms Digital and Linear Microcirats 43

4-9 Junctior Tenperature Deratirg for MOS Digital ASIC/VHSIC 44

4-10 Supply Voltage Derating for ?4S Digital ASIC/VHSIC 45

4-11 jurY-iiuii T-a•rc f-r-ti f MVWP_,/Rio!ar Linear ASIC/VHSIC 46

4- 12 Supply Voltage Deratirn for MS Linear ASIC/VHSIC 47

4-13 Junction Tterature Derating for Bipolar Digital ASIC/VHSIC 48

4-14 Criticality Level I SOA for MS Digital ASIC/VHSIC 55

4-15 Criticality Level II SOA for M1S Digital ASIC/VHSIC 56

4-16 Criticality Level III SOA for M4S Digital ASIC/VHSIC 57

4-17 Transistor Gate Area for MOS Digital Microprocessors 61

4-18 Dielectric Thickness for MIS Digital Micropcessors 62

4-19 Junmtimn Torpel-ture Derating for 8-Bit. M)S Digital

MicroProcessomr 63

4-20 Supply Voltage Derating for 8-Bit M1S Digital Microprocessors 64

4-21 Junction Temperature Derating for 16-Bit NOS Digital

Microprooossors 65

4-22 Supply Voltage Derating for 16--Bit MDS Digital Microprooessors 66

4-23 Junction Temperature Derating for 32-Bit NOS Digital

Micrcpracessors 67

4-24 Supply Voltage Derating for 32-Bit m1s Digital Microprocessors 68

LTST OF I=USTFATIICNS (continued)

FIC&JRE PAGE

4-25 iuwnction Tmperature Derating for 8-Bit Bipolar Micxtcprocessors 69

4-26 Junction Temperature Derdting for 16-Bit Bipolar Microrocessors 70

4-27 Junction Temperature Derating for 32-Bit Bipolar Micrtpropes-ors 71

4-28 C1 Factor for NOS PROIs 76

4-29 C1 Factor Zor Bipolar PRCMs 77

4-30 Dielectric Thickrnes for m s PF4s 79

4-31 Supply Voltag Derating for MSS PRfMs luiiing EEPWA-s 80

4-32 Supply Voltage Derating for EEFRTMs 81

4-33 Write Cycle Derating for E Hs 82

4-34 Maxinum CutTent Density for Microcircuits ep

5-1 MIMIC Failure Rate 93

5-2 MIMIC Prxbability of Suaxcess at 10,000 10L.rs 94

6-1 'ypical ower Transi.-tor SOA 99

6-2 Lifetest Results for GaAs Power MES•FTs 109

6-3 GaAs w MESFET Lifetime. Prediction 110

6-4 On-Off Cycling IAits for Power/RF PiL-se Transistors 118

7-1 CTt--w Innaflcmad ir, an RF Mul~titransistor Packiaae 121

7-2 Assembly Problem Resulting in Thermal Runaway 121

12-1 Ps = 0.9990 SOAs for MS Digital ASIC/VHSIC 146

12-2 Ps = 0.9900 SOAs for MDS Digital ASIC/VHSIC 147

32-3 Ps = 0.9000 SOAs for NOS Digital ASIC/VF.SIC 148

A-I On-Off Cycling Limits for Pawer/RF Pulse Tra¶nstors A-13

liii

LISr OF TABLES

TABPUI PAGE

1-1 Parts List 1

3-1 ýeratinqr Criteria Approach 153-2 Reliability Me.s and Derating Guidelines Used In Developing

Maxyimm Failure Rates 16

3-3 4axiumm Failure Rates for Each C0-iticaliti• Level 17

_•3•-4 WS Diital ASIC Reliability Model Factors at Derated Values 18

3-5 Reliability K-del Factors arxi Derated Values for ASIC/VHSIC,

flicrc~prxcessors andi P¶R4s 19

3--6 Reliabili ty Model Factors and Derated Values for Silicon

Bipolar Power Transistors 233-7 Gcmieram-mt/MilitarYiIndustry Stress Deratirq Guideline Titles 25

4-1 Attt.ibute and Paramters of Microcircit Model Factors 28

4-2 A';1C,/ ,73IC Device/Strer-Spacific Attributes 34

4-3 ASIC/VSIC IUS Digital Microcircuits Guidelines 50

4-4 M\IC/VHS.TC Bipolar Digital Microcircuits Guidelines 51

4-5 ASIC/VHSIC "VS Linear Microcircuits Guidelines 52

4-6 ASIC/VVWIC Bipolar Digital MicrocircUits Guidelines 53

4-rat-1m; -J--a5

4-8 Micrcpraoesso- Device/Stress-Specific Attributes 58

4-9 MXS Microprocessor Guidelines 72

4-10 Bipoiai Kicimprooesscr Guidelines 73

4-11 Ticroprocessor Stress Derating Criteria 74

4-12 P•g ULvice/Stress-Specific Attributes 75

4-13 WIGS P" Guidelires 83

4-14 Bipolar P"¶* Guidelines 84

4-15 P4M Stress Deratirv, Criteria 86

il

LISE OF TABLES (orntinued)

TABLE PAME

5-1 Attributes and Paramters of MIMIC Model Factors 91

5-2 NItIIC Device/Stress-Specific Attribtes 92

5-3 MIMIC Stress Deratinr Criteria 95

6-1 Attrijxites and Parameters of Silicon Bipolar PowSr Transistor

Model. Factors 101

6-2 Silicon Bipolar Power Transistor Stress-Specific Attributea 102

6-3 S.lirmr Bipolar Power Transistor Guidelines 103

6-4 Sllicon Bipolar Power •ransistor Stress Derating Criteria 104

6-5 GaAs RVr IMSFET Lifetest Data 106

6-6 GaAs Power Transistor Guidelines 112

6-7 GaAs Power Transistor Stress Derating Criteria 113

6-8 Power SFE Transistor Guidelines 115

6-9 Power MSFELT Stress Derating Criteria 116

7-1 Silicon Bipolar RF Pulse Transistor Guidelines 123

7-2 GaAs RF Pulse Transistor Guidelines 124

7-3 RF Pulse Transistor Stress Derating C-iteria 125

s-1 aito-electric Device Guidelines 128

8-2 Opto-elcctruiic Device Stress Derating CQi•teria 129

9-1 Passive Device Guidelines 132

9-2 Passive Device Stxess Deratirg Criteria 133

10-1 SAW Guidelines 136

10-2 SAW Stress Derating Criteria 137

11-1 Stress Derating Assessment for Level II Criticality 139

11-2 Maxinum Failure Rates for Criticality Level II 140

v

1.0 EXECUTIVE SUMMARY

1.1 OBJECTIVE

The objective of this effort was to develop and publish new derating

criteria so that the reliability of new upcoming and modified designs will

be enhanced. Stress deratting parameters were needed for advanced

components such as VHSIC (very high speed ir-cegrated circuits), MIMIC

(microwave/millimeter wave monolithic integrated circuits), GaAs FET

(gallium arsenide field effect transistor), and photonic devices since the

current standards were lacking guidance. The new standards will be used by

hardware design contractors and will serve as the basis, for an update of

AFSC Pamphlet 800-27, "Part Derating Guidelines." The complete parts list

for which updated stress derating criteria was to be developed is shown in

table 1-L

Table 1-1 Parts List

VHSIC RF Pulse .dransistorASIC RF Multi-tb-ansistor~4MIC PackageMicrc~pro-essor Photo Transistor1Rt4 Photo Dicde- ultra-violet erasable Cpto-electronic Coupler- e1ect±rca1ly erasable Injecticn Laser Diode- eleccricalLy alterable UM)- avalanche irduced Hybrid De±posited Film

migration nesistorur~r Transistor Chip Resistor- silic(m Chip Cipacitor- &•As SAW

1.2 BACKGROUND

Part stress derating has long been established as an imilportant element in

enhancing system reliability. Derating is generally defined as the

practice of limiting electrical, thermal and mechanical stresses on parts

to levels below their specified or proven capabilities in order to provide

a safety margin for operation and to improve system reliability. Most

contractors have developed their own internal derating practices, but until

recently, the DoD (Department of Defense) had no standard practices. RL

recognized the need for standardizing this area. This standardization will

proAide guidance to those contractors without their own policies, indicate

a means for invoking contractual derating requirements and create a

benchmark against which other derating methods may be evaluated.

In keeping with the cost effective tailoring approach to reliability as

defined in MIL--STD-785, "Reliability Programs for Systems and Equipment

Developxm•. nt and P xdutinn Boeing Aerospace (Seattle, WA) under contract

to RL, divided derating cri:t•eria into three different criticality levels.The three level derating approach provides a means of tailoring as a

function ot mission criticality and severity of the end use environment.

RL adapted the results of this study in the publication of AFSC Pamphlet

800-27, "Part Derating Guidedines.'l Further work on derating was performed

by Mart-i Marietta (Orlando, F4• under contract to RL, which included

development of an integrated circuit thermal measurement technique to

verify derating. Both of these eftorts precluded the deve1opment of

der"',Aing 5ctors for new parts dezsigned since the studJ'- were conducted.

While under contract to Pt, Westinghouse rece. '°Ly completed the

"Reliabilit~l At.llysiyA.;sment i:f Advanced Technology" (RA/AAWI) study1

with the intent of updating the microcidrut section of MII-IDBK-217. With

the availability of tJhe stress-failure relationships developed as part ofthat study, as well as ,ose working relationsbips with their :,uppliex s and

available field failure data, Westinghouse was selected to conduct this

"Advanced Technology Component Derating"' study.

2

1.3 APPROACH

Stress derating c.' advanced technology components is a critical strp in the

design of rllrctroric sy.stems which e-lnploy these components. Only by the

increased lifetime advantage offered by stress derating can the systera

reliability requirement be reallized wben using advanced technology

components in the system designer's intended application.

It was the intent of the authors of the revised AFSC Pamphlet 800-27 to

maintain the spirit of the current version of the Pamphlet (hereafter

referred to as "the Guidelines") and, at the same time, minimize

unnecessary constraints placed on the designers of electronic systems by

the derating criteria. These unnecessary constraints result from the

application of generalized derating criteria intended to encompass all

components within a specific component style in order to keep the

guidelines simplified. It was believed that, unless the designer can

eimploy derating criteria in his design with minimum difficulty, he will be

reluctant to take the tine necessary to apply the derating criteria

properly. In this day of Total Quality, process streamlining and high

speed design workstations, the designer is motivated to be proactive in all

areas affecting his design. Therefore, in the formulation of the new

stress derating criteria, a change in the derating criteria format is

presented (for microcircuits), with the thought that the designer should,

0.1 AL WLU±U.L J%.LA 1W rIL'.J.L QLKAJUI. LA= C0.JiUk.J1 %J i=L% W.ALt. W LLLýL.L JLA= W QX .Aý .' L C1A,01 IL

be more likely to design an optimum, reliable system by applying the

appropriate stress derating criteria. The need for the change in the

stress derating criteria format was a direct result of the logical approach

taken to update the stress derating criteria, and the structure of the

re-liability modeLs that describe the relationships between applied stresses

and component failures.

It is recognized that the stress derating criteria outlined in the

Guidelines is, by definition, a description of the maximum allowed stresses

that may be applied to a component according to a specified mission

3

criticatlity level. It is also recognized that these maximum stresses

result in a maximum component failure rate predicted by accepted

reliability model-,. It is noted here that, at the time the current version

of the Guidelines was released, the accepted reliability models were

ixr)uded in MIL'-HDBK-217D Notice L Therefore, the authors of the current

version of the Guidelines considered the maximum component failure rates,

calculated using the reliability models of MIL-HDBK-217D Notice I and the

maximum stress derating criteria outlined in the current version of the

Guidelines, acceptable for a specified criticality level. A logical

approach to updating this stress derating criteria would be to first

calculate these acceptable maximum component failure rates at each

criticality 'Level. Then, the stress-failure relationships outlined in

updated reliability models, such as those included in MIL-HDBK-217E Notice

1 and the RA/AAT study, may be evaluated such that new maximum stresses

that result in these same maximum failure rates may be identified. These

maximum stresses become the updated stress derating criteria.

This approach to updating the stress derating criteria has (at least) three

benefits. First, the stress trade-offs performed to derive the new maximum

stresses by evaluating the updated reliability models will identify the"lsensitivd' derating parameters in the model that, when varied, result in

the largest changes in expected failure rate. Second, the approach

provides a framework from which derating results can be easily

comraur•c•tci. That t 1-he ornept of how changes in "failure rate" affect

design reliability is more commonly understood among system designers and

reliability engineers than how changes in "percent of rated value" affect

design reliability. Third, the approach provides a basis for evolving the

stress derating criteria into a '1ontinuous" function of criticality rather

than the currently accepted three levels of criticality. This benefit is

expanded upon in a section near the end of this report.

This stress derating approach was applied to several classes of

components. The approach was first successfully applied to microcircuits.

Having just completed the Reliability Analysis/Assessment of Advanced

4

Technologies (RA/AAT) study, Westinghouse was intimately aware of those

stress factors which directly influence the reliability of advanced

technology microcircuits. From a study of the RA/AAT results, it was

observed that microcircuit complexity was a "sensitive" derating

parameter. Because of the impact that the complexity of the microcircuit

hal on its failure rate, part of the updated stress derating criteria was

gewerated as simple one variable equations. The variable, of course, was

complexity. For exaorple, in the development of the stress derating

criteria for MOS Digital ASIC/AHSIC cowpormnts, the supply voltage derating

criteria for criticality level . has the form

Si.,pply Voltage = 129 / (G ** 0.320) vclts

where G is the number of gates in the microircuit. In some instances, the

calculated derated stress was virtually independent of complexity. In that

case, a constanL derating value was substituted for the derating equation.

Also, if the calculated derated stress wais ouutide thQe regi- of validity

of the reliability model, the value of the maximum stress identified in the

model was substituted for the derating equation. For example, the maximum

junction temperatures allowed for MOS Digital ASIC/VHSIC level III

compo' ents, although dependent upon complexity, are abc ve the junction

temperatures reoorde,'I in the reliability data used in the development of

the reliability model. Since 125 deg C was the maximum junction

temperature identified in the reliability data, the maximum temperature of

125 deg C is substituted for the de•uating equation.

other microcircuit derating parameters were not explicitly identified in

the reliabilty models. These parameters, such as fanout and frequency,

weze considered design and application attributes which influenced the

dcatabase from which the reliaility models were developed. Therefore, the

updated stress dezating criteria for these parameters were developed froth,

reviews of the literature, supplier information and uther pertinent stxess

derating guidelines.

5

A similar stress derating method was used for silicon bipolar power

transistors. Although the MIL-HDBK--217D Nortice I raliability maodel for

silicon bijolar power transistors was significantly differenr from t''e

MIL-HDBK-217E Notice 1 :7eliability model, the approach used in th,-development of the microcircuit derating criteria could be applied co

silicon bipolar power trensistors. The difference between the microcircuit

approach and the silicon bipolar power transistor approach was 0-,at thederating criteria for the power transistor was developed with equal. weightapplied to the stresses identified in the reliability model ofMIL-HDBK-217E Notice 1. That is, the voltage derating and temperatuure

derating for criticality level I must both be 65% of maximum rating so thatthe failure rate calculated using MIL-HDBK-217E Notice 1 would equal thefailure rate calculated using MIL-HDBK-217D Notice 1 (4 FITS). Thetemperature derating was then transformed into temperature unit-s with avalue of 95 deg C (based on a 150 deg C maximum rating). For further de-tails on this calculation, see section 6.1 on page 102.

Since reliabil__ity models for silicon power MOSFETs and GaAs powertransistors were riot available at the time the current version of theGuidelines were published, different approaches were taken to develop

stress derating criteria for these devices.

For power MOSFETs, the, stress dezathig criteria was developed by a tharough

review of the literature and supplier surveys, and consensus of bothmilitary and industry stress derating guidelines. It was deter. ined thatthe currently accepted derating policies ade adequate in themargins of safety and success needed in the intended application.

The stress derating approach for GaAs power transistors was to collectreliability data, develop a stress-failure model and, assuming a maximumfailure rate for each criticality level (provided by R4•, calculata thei. ýximum stresses allowed. This effort resulted in maximum channeltemperatures of 85, 100 and 125 deg C for criticality levels I, II arid II,

respecýtively.

6

With the exception that a reliability model was developed on the RA/AAT

study, the stress derating approach for GaAs MIMICs was similar to the

approach for GaAs power transistors. The maximum channel temperatures for

MIMIC devices were calculated to be 90, 130 and 150 deg C for criticality

levels I, II and III, respectively.

It is noted here that, with the exception of the application notes, the

silicon arid GaAs RF pulse transistors are derated similarly to the silicon

and GaAs power transistors si both silicon and GaAs RF pulse transistors

must be able to "dissipate as much power in pulse mode as the silicon and

GaAs power transistors dissipate in continuous mode. GaAs power

transistors (power MESFETs) are often used in RF pulse applications

Opto-electronin components presented a different challenge in developing

updated stress derating guidelines. The differences between the

reliability models of MIL-HDBK-217D Notice 1 and MIL-HDBK-217E Notice 1

res..lted in up to several orders of magnitude difference n in

predicted failure rates. The quality factor had changed 2400% to 7000%,

and the PiT factor of MIL-HDBK-217E Notice 1 utilizes an activation energy

of approximately one third of the activation energy used in MIL-HDBK-217D

Notice 1. The use of the silicon bipolar power transistor approach to

stress derating would have resulted in virtually no stress derating

required to meet thve failure rates that were considered acceptable at the

time the currert version of the Guidelines was released. As an alternative

approach, the development of updated "acceptable" failure rates for the

three criticality levels was considered. The failure rates that can be

obtained by applying currently accepted derating guidelines to the

reliability models were deemed to be as "acceptable" as any other values

chosen. Therefore, without having to do the failure rate calculations and

the reverse stess analysis, the currently accepted guide) ines become the

updated stress derating criteria. A consensus of both military and

industry stress derating guidelines was used in the development of this

criteria.

7

There was apparently no change in the reliability models since

MIL-HDBK-217D Notice 1 for the passive components evaluated, namely thlickand thin film resistors, chip capacitors and SAW devices, and therafore

only a consensus of military and industry guidelines was again used in the

development of the stress derating criteria for these components.

To check if the expected results of applying stress derating crite, ia tothe components identified in table 1-1 were obtained, a failure rateanalysis was performed on available field failure data. The analysis wasperformed on field failure data provided by failure databases from the

AI/APG-66 and AN/APG-68 radar programs and the ALW-131 radar jammer programduring the sorties flown in the 1988 and 1989 time period. It wasdisoovered that che failure rates for PROM4 devices, power transistors, RFtransistors, epto-coupler.,-, LEDs and thin film chip resistors were close to

or below the failure rate that- would be expected when applying the stressderating criteri .- outlined in the current version of the Guidelines. Onlythick PIm resistors and cxramic chIp capacitors experienced failure rates

significantly above expected failure rates. The most likely reason forthis discaepancy" is that these components often get removed as part of the

reworx for the suspected failure of another component. Since failureana2~lyss are typically not. p-rformed on most of the components removed from

system~s, it is quite possible that some of the "failed" components are not

truly failed. The calculated failure rates in this analysis would

there•ore be inflated. The rcsults of this verification analysis are, in

either case, most encoura,9isg.

At the completion of this study, one concern is still left unresolved. Theconcern is -dhat the designer is 'locked ir." to a level of derating criteria

based on mission type of the whole isystem (SF, AUF or GF, for example)rather than the true component or board criticality. This concern

prompted the authors of this study to include a section near the end of

this report which outlines an alternate approach to implementing stressderating guideli es. The intent of this approach was to justify the

PasonihAlenrss of imnposing criticality level I guidelines on a criticality

8

2evel III mission design, and vice versa, depending as much upon systemarcldtecture. s the safety ard success of the mission. The possibility ofevolving stress derating criteria into a "continurous" function ofcriticality is evaluated.

9

1.4 LIST OF ACRONYMS

The following is a list of the acronyms used in this report.

AFSC - Air Force Systems Command

APD - Avalanche Photo Diode

ASIC - Application Specific Integrated Circuit

ATCD - Advanced Technology Component Derating

CTR - Current Transfer Ratio

EEPROM - Electrically Erasable Programmable Read-Only Memory

EM - Electromigration

ESD - Electrostatic Disrharge

eV - Electron Volt

FET - Field Effect Transistor

FMEA - Failure Modes and Effects Analysis

FPMH - Failures Per Million Hours

GaAs - Gallium Arsenide

ILD - Injection Laser Diode

JFET - Junction Field Effect Transistor

LED - Light Emitting Diode

MESFET - Metal Semiconductor Field Effect Transistor

MIL-HDSK - Military Handbook

MIMIC - Microwave/Millimeter Wave Integrated Circuit

MOS - Metal Oxide Semiconductor

MOSFET - Metal Oxide Semiconductor Field Effect Tran'sistor

PROM - Programmable Read-Only Memory

RA/AAT - Reliability Analysis/Assessment of Advanced Technologies

RL - Rome Laboratory

RTOK - Retest Okay

SAW - Surface Acoustic Wave

SOA - Safe Operating Area

TDDB - Time Dependent Dielectric Breakdown

VHSIC - Very High Speed Integrated Circuit

VISI - Very Large Scale Integration

10

2.0 REPORT ORGANIZATION

Section 3.0 presents the three approaches taken in the development of theupdated stress derating criteria. Each approach is outlined briefly in

this section with the details of the approaches provided in the followingseven section No stress derating criteria is developed in this section.

Section 4.0, 5.0, 6.0, 7.0, 8.0, 9.0 and 10.0 discuss silicon

microcircuits, MIMIC device-s, power transistors, RF tran.irtors,

opto-electronic devices, passive, components and SAW devices, respectively.

Stress derating cz-i'eria and associated application notes are provided in

each section for the relevant components in that section.

Section 1.o presents a summary of the accumulated field failure data for

the available component types outlined in table 1-1. A comparison of thepredicted failure rate based on Level II criticality derating and the

observed failure rate is made to ve'-ify the accuracy of the stress aerating

criteria.

Section 12.0 discusses an alternate approach to stress derating derived

from observations made in the development of the updated stress derating

criteria for this study.

Section 13.0 summarizes the results of the study and presents conclusions

and recommendations for follow-on analysis.

cSection 14.0 contains the bibliography of the literature used in part to

develop the updated stress derating criteria.

Appendix A provides a comprehensz.ve sulm-ory of the updated stress derating

criteria and associated application notes.

Appendix B provides sample Fortran programs used in the development ofstress derating criteria for microcircuits.

111

3.0 ADVANCED TECHNOLOGY COMPONENT DERATING

The developrent of stress derating criteria for advanced technologycomponents requires a fundamentally sound understanding of the

relationships between the electrical, thermal and mechanical stressesapplied to the components and the resultinq life distributions of the

component populations. Component reliability models ara used to describethese relationships and provide insight into the functional dependence of

component life distributions on the applied stresses.

The magnitude of the stress derating determines the amount of expectedchange in component lifetime or shift in the life distribution of a

population of components. In general the more the stress is derated, the

longer the life of the component. Therefore, the expected result of

derating the stresses applied to a component is to decrease its failurerate. Since most reliability models relate electrical, thermal and

mechanical staesses to component litetime in tie fociz, of a fai2-uro rate, itis reasonable to use the concept of failure rate as the key link between

the reliability model and the stress derating criteria.

The minimum acceptable stress derating depends upon the criticality of themission. Criticality levels referenced to mission safety and success, as

outlined in the current version of the Guidelines, can be established and

contasted -in terms of failure rates. The minimum acceptable stress

derating for each criticality level sets the maximum failure rate that

might be experienced by the component in a mission of specified

criticality. It is reasonable to maximize the stress derating, when

possible, to provide a greater than minimum margin of safety and success.

The definitions of the criticality levels used in the updated version of

the Guidelines are consistent with the current version of the Guidelines.

It is noted, however, that the formulation of the updated .tress deratingcriteria is iriven by the component failure rates associated with eachcriticality level and not solely the definitions of criticality.

12

Criticality Level I (.':aximum Derating). Used with equipment whose

failure would substantially jeopardize the life of personnel,

would seriously jeopardize the operational mission, or would

require repairs that are infeasible or economically unjustified,

or used when extremely high operational readiness requirements

are specie~ed. Level I derating is considered those stress

levels below which further reliability gain is small or at which

further derating will create design problems that are

unacceptable. This level is intended for the most critical

applications in which design difficulty can be justified by Lhe

reliability requirement.

Criticality Level In Used with equipment whose failure would degrade

the operational mission or would result in unjustifiable repair

costs, or used when high operational readiness requirements are

specified. Level II derating is considered still in the range in

which reiiabality Ya-"n5 adr rapid u trA-esiS i5 deca eased.

However, achieving designs with these reductions in allowed

stress is significantly more difficult than at level III.

Criticality Level III. Used with equipment of lesser criticality than

level I or II, namely, equipment whose failure may not jeopardize

the operational mission or that can be quickly and economically

repaired. Level III derating is that stress level reduction that

causes minor design difficulties and yet generates a large

incremental reliability gain. The large reliability gain is

realized since the effects of stress increase greatly as the

absolute maximum rating is approached.

Supplemented by updated stress-failure data provided by three sources,

namely, a thorough review of the literature, evaluation of available field

data and component supplier surveys, the component reliability models

developed on the RL "Reliability Analysis/Assessment of Advanced

Technologies" (FA/AAT) and "Reliability Prediction Models for Discrete

13

Semiconductors" 1 69 studies provided a starting point for the developmentof the updated stress derating criteria for several of the component types

identified in table 1-L For those component types not covered by currentreliability models, stress derating criteria was developed from eitherreliability models generated from accumulated life test data or fromconsensus of current stress derating guidelines available frov multiplemilitary and industry sources. These approaches to understanding thestress-failure relationships of advanoed technology components, outlined infigure 3-1, were executed on a priority basis in the order listed above.That is, if a current reliability model was available, it was used(approach A). If a reliability model was not available, a reliability

model was developed, when possible, from accumulated stress-failure data

Device List7Ij•J

SKevword List ].WEC Part NumberZ

Vendor Visit] Vendor Contacts F Systen identity

FTheory L ldp3 • rE[I.her ,L~per-~~d L~pr Field Fatr Fiel

Strnss / Failure Dai.gbase hicluding Application Limitations

J 8. Develop ,Vodel]

L Stress/ FilureRelationships - A. Rel. Models

Derating C.itcria - C. Derating Guidelinels

Criteria Verification]

Figure 3-1 Flowchart of Technical Approach

14

(approach B). If it was not possible to develop a reliability model, then

a consensus of available derating guidelines was used to generate the

proposed derating criteria (approach CQ. Table 3-1 identifies the approach

used for each component type listed in table 1-1.

In the approach taken to update the stress derating criteria using

rel/ability models, approach A, a methodology was established in which a

maximum failure rate was calculated for each criticality level for each

component type. The reliability model used to generate these maximum

failure rates was MIL-HDBK-217D Notice 1, since this revision of

MIL-HDBK-217 was the current Handbook revision (13 June 1983) at the time

in which the current version of the Guidelines was released (5 December

Table 3-1 Derating Criteria Approach

"I- ?nN- - - I- I

ASIC A, CWisIC A,CMicroprocessor A, CPRCM A,CMIMIC A,CPower Transistor A,B,CRF Pulse Transistor CRF Multi-tLansistor Package CIPhoto Transistor CPhoto Diode COpto-electronic Coupler CInjection Laser Diode CLED CHybrid Deposited Film Resistor XChip Resistor CChip Capacitor CSAW C

KEY: A - Reliability Model AvailableB - New Reliability Model DevelopedC - Ccocensus of Available Derating GuidelinesX - Insufficient Lnformation

15

1983>. The reliability models and derating guid lines used to calcui.ate

the failure rates are shown in table 3-2 for each component type for which

approach A was used. These failure rates, listed in table 3-3, represent

the maximum failure. 1ates expected for the given criticality level allowed

by the current version of the Guidelines.

The example of how the stress derating criteria was applied in the

development of the maximum failure rates for MOS digital ASIC/ VkSIC

microcircuits is shown in table 3-4. Using the stress derating criteria

for eiOS mirocircuits in the current Guidelines, the maximum values of each

factor in the reliability model were determined for each criticality

level. The failure rates were calculated to be 0.3402, 3.0593 and 31.640

fpmh for" criticality levels I, II and III, respectively (see table 3-3).

Table 3-2 Reliability Models and Derating GuidelinesUsed In Developing Maximum Failure Rates

Component Type NIIrIIDBK-217D Notice I AFSCP 800-27 (1983)

ASIC/VHSIC Microcircuits: Microcircuits:- MS Digital - Mownlithic MOS Random Logic ISI Digital (MJS)- M4S Linear - Monolithic MOS Linear - ldnear (MOS)- Bipolar Digital - Mrnolithic Bipolar Ran. Logic LSI -. Digital (Bipolar)- Bipolar Linear - Mnolithic Bipolar Linear - Linear (Bipolar)

Miczprocessor Microcirc•its: Microcircuits:- __ - Microprocessor (MrS) - Digital (MVS)- Bipolar - Microprocessor (Bipolar) - Digital "Bpoar

P" Microcircuits: Microcircuits:- MS - PRM (S) - Digital (MlG)- Bipolar - PRM (Bipolar) - Digital (Bipolar)

Power Transistors Transistors: Transistors:- Silicon Bipolar - Group I, Silicon - Bipolar Silicon- GaAs - (Not Listed) - Field Effect- MDSFEr - (Not Listed) - Field Effect

1.6

Table 3-3 Maximum Failure Rates for Each Criticality Level

Failure Rates (fmih) for Levels:

Component Type I II III

ASIC/VInsIC- NOS Digital 0.3402 3.0593 31.6405- NOS Linear 0.4932 4.3920 46.0962- Bipolar Digital 0.3126 1.5862 11.6614

Bipolar Linear 0.4932 2.7477 24.8862

Micrcprocessor- NOS 0.3402 3.0593 31.6405- Bipolar 0.3126 1.5862 11.6614

PROM- NOYS 2.7371 22.7459 264.2236- Bipolar 0.6322 2.8023 23.6754

Power Transistor- Silicon Bipolar 0.0040 1.2917 0.5763

The reliability model parameters and derating values for the microcircuitsand power transistors for which approach A was used are shown inabbreviated format in tables 3-5 and 3-6, respectively. The calculatedmaximum failure rates "bound" the stresses driving the componentreliability, described by the updated component reliability models, suchthat these maximum failure rates could not be exceeded. The values of thestresses, in absolute form or as a percentage of the maximum rated value,became the new derating criteria. Using this methodology, the new deratingcriteria could remain consistent with the old derating criteria. That is,the updated stress derating criteria will not allow a component to be usedin a particular mission with a higher failure rate than was allowed by thecurrent version of the Guidelines. In fact, the derating criteriadeveloped for more complex microcircuits results in a lower failhre rateper function for these microcircuits than less complex microcircuits. It

17

Table 3-4 MOS Digital ASIC Reliabihity Model Factors at Derated Values

Level Factor Value Stress Derating AttriLbites

I PiQ 0.5 S levelI PiT 6.9 85 deg C, A = 7532I PiV 1.0 5 voltsI PiE 0.9 SFI PiL 1.0 > 4 mnths productionI Cl 0.0919 20,000 GatesI C2 0.0024 20,000 GatesI C3 0.048 64 pin DIP, glass seal

II PiQ 1.0 B LevelII PiT 16.1 100 deg C, A = 7532II PiV 1.76 12-15.5 volts, 85% derating, 100 deg CII PiE 9.0 AUFII PiL 1.0 > 4 months productionII C1 0.0919 20,000 GatesII C2 0.0024 20,000 GatesIi C3 0.048 64 pin DIP, glass seal

Il PiQ 6.5 B-2 LevelIII PiT 27.3 110 deg C, A = 7532III PiV 1.89 12-15.5 volts, 85% derating, 110 deg CIII PiE 2.5 GFIII PiL 1.0 > 4 months pr:i/uctionIII C1 0.0919 20,000 GatesIII C2 0.0024 20,000 GatesIII C3 0.048 64 pin DIP, glass seal

is noted here that the environmental factors were chosen for the saruereason other constants and parameters were chosen, that is, to give themaximum failure rates. It should be noted, however, that the value of the

worst case environmental factor (as well as the other factors) in the

development of the maximum failure rate cancels with the worst caseenvironmental factor (as well as the other factors) in the development ofthe updated stress derating criteria. Again, the intent was not to develop"Conservative,, results, but results that would be. considered commensurate

with the results already experienced when using tht stress deratingcriteria outlined by the current version of the Guidelines.

18

Table 3-5 Reliability Model Factors arid Derated Valuesfor ASIC/VHISIC, Microprocessors and PROMs

a aa4K -I K 6K K 4K-K-

4O) a 0 QO 0 0 . 00

a. a a 0ý C' o ;C a a3 aD

"51 4m a, anC m aC , C 5C3 C DC 3C 3 4 a

C>3 cta- ,@~4 0 0 0 a0- CDl * 000 *ý c-al 000

-' r4 In 4.-e fn -rm an C l

*~- 4 *a

ad, a- 44 * a2aL-c *F-0 a g 'a r - c *et r c . 0

2 3 ~ pt :0 za :U Q'-i*O M 0 - ).U ~CI- ~ ~ ~ ~ ~ ~ ~ n '0'O a C0-*N 4 'o-*0O' '-t-*''? a'

CU * C'.ja a ~ aa .CJ a . ~ Q6

4 4 4 a 19

Table 3-5 Reliability Model Factors and Derated Values forASIC/VIISIC, Microprocessors arid PROMs (continued)

ai C4 -4 aa ?A a )(

- 0 C~O a iJO, C I= J 0 -C3 b! C31 Im 0 0 C3J C.- V.0 -af C$ C

m 1t'0 FQQ ~ In~ a 0CQ ae4 = a 10 C1 0Q~'

m CI 0 1~ f C a.O * 0,. Cm Q J.t aQ 00.- C 01 e - C6~~ a1 0CJ1

W 2S .Iim a z307 C18 a a 1 " 0 a CI ZI a1 1 I -1CS Cc. aý 0 0 a; a; aD aý0 C ; ý C - ~

0 C!. a. . a. . a9 . a.999 9 .4 C n C a 0 CD aýO a a aD aD C j M 0C 0C

0 0a

*) aj at a a1 J a

do X am 3 . a a

a a a a a0

Table 3-5 ReliabiliLty Model Factors and berated Values forASIC/VHSIC, Microprocessors and PROMS (continued)

00- 4a 00- LA Ul 4L.-44

it 4 4 4 ir. 4 'A~ 4AL

&A 4 A 6A 'A 4 W

fm 44 4q 4v -t -. 4y -~ CU-ct

*. cc c wnvq~sc

n icO(J J J it, r-r &--1C1 ..

riI. " -C -C. 1- -K N.z r- Z Z -K - C. -C -C 1-C->> * >> ~~4C ~ % > ~ t > 4 .

l~u 4 BA.) 4 ; C; C; L; M 4; 4; C L;

S/l~fl ; U~l 4 4; Wtl l 4 4 . 0

EC) NN. C3 C3 NCe C3 NOInCD

44n r- I4-" H m l I I r- ~ tI r- *ICI N ! - =il .- ils

'00 8 0mt>a3 5 40 OLI ) -00) 0 4 M0 *A i0 n 4 .0CD~~~~ ~ ~ ~ C>C ,SC 00ýC 1n O

to- Wcc toc In00400n3C CAcc W toC.CA w, lW,43- 0-24 4a -on (0344 t.*( 304300 w 4

-0 * C9.. . -- C

43 4 4 ~4 44

~~0~ 0N0 N. N. N' (A N N

&1 4 C I m 4' y_ 4- U 4 ' f 4 4

211

Table 3-5 Reliability Model Factors and Derated Values forASIC/VHS2EC, Microprocessors and PROMs (continued)

0 ~ ~ t $A fA 'A CA 'A 4 0 0 CO m 0 0 'A m W

4., 4.4 44. 4.- 41.4 .1~41'4a 44 4 4'4 4s 44 - 1'

: a. .1 . 4 4 4. 4.aa

A AA A AA 'A A A A A AA A A A~ A A A A A A A A

4-a w L Id 44 )4 ) 4 4 0 V q) C; 4 43 4 W 0 IV4

(A * C 4 U4 w 0 40 )# )wm 4 4 U)# AV

C24 4. a0 42 Cm (2 C 0 00C

13013 9 13 CA 9 L.9L a 0333111.11. 3136 .13131A.1a-3G0. 0. - I

0) 40 al ' nE E n 'Al fn i nEnE n 0n fA 0) 'A En 4, 4,E n * i nE

U 00), 300 ,ZUIl 40, UO 120 a42 Q0 C2 0(5 A A7

C. P ( . CD C0 C.3 000 C 00 C 00 3 C)0 C) C)0 D C) C) nL " f nIK. M. M. (N CU a. a. fn.a ~ .a . a. a. . . a. .a *a..a .a.a

-J41 ' 4

OW .,*IZ- at x50 m 4-.4.. 4O 0(50 *

-aJ 13- 4~ fn a - i4 Pn a4.--M.

L3. 4~ r

U 01 4 .4

I-______ -A______ L._____9C

>< -* a,' N a~43*'N3* E'l' EI'di 1- 4 4041- 1 U5 .. .

9-. m9 SW -l4- -.- L '.3 4.3 'N a4 '(.3 N .N ara

223

Table 3-6 Reliability Model Factors and Derated Values forSilicon Bipolar Power Transistors

Description Factors

Device Prediction Crit. Base FR Quality I Cowdi2xity Env*,onmentType Reference Level (LambdaB) (PiQ) (0l) (A'IE)

Transistor MIL-217D1 1 0.0092 0.12 1.0000 0.40Group 1 2 0.0092 0.24 1.0000 65.00(Silicon) - 3 0.0092 1.20 1.0000 5.8,

Description Factors Failure Rate

Device Prediction Crit. Application Power Rating Volt. Stress (Failures IType Reference Level (PiA) (PiR) (PiS) 10-6 Hrs)

Transistor MIL-217D1 1 1.50 5.00 1.20 0.0040G r o - ',! 1 .5 0 5 1 . . .1, r 5.0.0 1.0 1 ,(Silicon) j _ 1.50 5.00 1.20 0.5763

Description Rationale

Device Prediction Crit. Base FR Quality Complexity EnvironmentType Reference Level (LaenidaB) (PiG) (C0) (PIE)

Transistor HIL-ZfD1 M 1 (Rax) JANTXV singie Trans. SFGruup 1 2 (max) JANTX Single Trans. AUF(Silicon) 3 (max) JAN Single Trans. GF

Description

Device Prediction Crit. Application Power Rating Volt. StressType Reference Level (PiA) (PiR) (PiS)

Trans;stor MIL-217D1 1 Linear 200 Watts S2 - 70%Group 1 2 Linear 200 Watts $2 a 70%(Silicon) 3 Linear 200 Watts s2 u 70%

23

In the approach to update the stress derating criteria by creating new

reliability models, approach B, stress-failure data accumulated from the

literature search and supplier surveys wa., examined, and the r"eliability

model was generated, It is noted here that this approach was used only for

the temperature parameter in the reliability model for GaAs power

transistors (see Section 6.2).

If approaches A and B were not viable, then a consensus of available

derating guidelines was used to update the stress derating criteria,

approach C. The fourteen guidelines used in the criteria development are

listed in table 3-7. Of these fourteen guidelines, twelve guidelines were

from government or military sources and two were from industry sources.

V parameters selected for derating by these fourteen sources were not

consistent between the sources. Therefore, before the stress derating

criteria could be evaluated, it was first necessary to identify the key

-rarmeters to be derated. These key parameters were initially limited by

ttie sources that specified derating criteria for three criticality levels

(guidel ines A through F). The remaining parameters were included as

application notes, when appropriate. It is noted here that guidelines A

anid B were exactly the same, and therefore, guidelines A and b were

considered one source in the development of the final updated stress

dexating criteria. Once these parameters were identified, the consensus of

the five guidelines was obtained by calculating the median of the stress

dorý.Ung values for each stress parameter.

Ln.Ul cases, application notes and design limitations were developed from

accwu-Wtd component information, obtained in the literature search or

-.•d r. surveys, and extrapolated from other derating guidelines. The

ao~'9[Lr• notes for each component type are furnished at the end of each

py.v-i'c' :Leport sections and in Appendix A. In addition, the adequacy of

.Z ivress derating criteria was reviewed using failure rates calculated

ftom awcumulated field failure data (see Section 11.0).

24

Tah-Ile 3-7 Goverrunent/IMilitaxy/Industry Stress Derating Guidel-ine Titles

Designator Guideline

A AR3C Paniphlet 800-27, 5 Deoe1*er 3,983B FS-TR-83-197C ESD-'M-85-148D RAD)C-M-84--254E RADC-'M-82-177F NASC AS-4613G GSFC PPL-18 (MNSA) , October 1986H NAVNAT P-4855-1AJ MILrSfl>2174 (AS), July 1976F !4Th-SID-75H (NA&X) , June 1989If NAVSEA TEOOO-AB-GIP-010, September 1985M M~r-gID--1547A, Dwarber 1987W OFM Ax OEM B

25

4.0 MICROCIRCUJIT DERATING GUIDELINES

For advanced technology silicon microcircuits, the RA/AAT reliability

modelsI can be summarized in general form by

L(to) = PiQ * (Cl * PiT + LCyC + C2 * PiE) * PiL + LTDDB (to)

+ LEM (tr), ()

where:

I4to) is the device failure rate at time to in failures per million

hours,

PiQ is the quality factor,

PiT is the temperature acceleration factor, based on technology,

PiE is the application environment factor

PiL is the learning factor,

C1 is the circuit complexity failure rate in failures per million

hours,

C2 is the package complexity failure ratsA in failures per million

hours,

LCyc is the EEPROM write cycling induced failure rate in

failures per million hours,

LTDDB(to) is the time dependent dielectric breakdown (TDDB)failure rate at time to in failures per million hours, and

l;M(to) in the electromigration (EM) failure rate at time to in

failures per million hours.

A review of the literature 2 9 -1 0 0 concerned with microcircuit failure,

during the time since the RA/AAT reliability models were generated,

resulted in no change to thce basic rcliability models. However, it was

noted that, since failures due to electromigration, having failure rates

LE., are distributed normally with the logarithm of time with very small

variances, the effect of LEM on the total failure rate, L(to), is

either negligible or catastrophic. Therefore, the Lim term was

26

eliminated from the equation for calculating failure rate and the

,•ectromigration effect is presented as an application note. Without this

LM term, the failure rate equation for deriving stress derating criteria

simpliiile to

L(to) = PiQ A (C1 * PiT + Lcyc + C. * PiE) * PiL + LTDDDB (to) (2)

The stress parameters and attributes that directly affect the calculated

failure rate for a siiawn microcircuit are embedded in the Pi, complexity,

and wear out failure rate factors of the reliability model. To extract the

maximum stresses allowed for each criticality level from the factors in the

reliability model, L(to) in equation (2) must be set to the maximum

failure rate allowed by each criticality level. These maximum failure

rates are specified in table 3-3. In the approach to develop stress

derating criteria for advanced technology sill'con auicrocircuits, the

parameters and attributes of the failure rate model factors were separatedintothre goup,aon group for ~~j.'ij /C ~.u4e

group for device-specific (DS) attxibutes and the other group for

stress-specific (SS) parameters. Table 4-1 outlines the relationship

between the factors in the failure rate equation, the distinction between

criticality-specific, device-specific and stress-specific parameters and

attributes associated with the factors, and the microcircuit technologies

for which these parameters and attributes are applicable.

There were two basic types of device-specific attributes, technology and

complexity. The technology attribute was handled by creating stress

derating criteria for each technology individually. For exaiiple, there are

digital and linear, MOS and bipolar ASIC/VHSIC microcircuits. Therefore,

four stress derating tables were developed, one for digital MOS ASIC/VHSIC

microcircuits, one for digital bipolar ASIC/VHSIC microcircuits, one for

linear MOS ASIC/VHSIC microcircuits and one for linear bipolar ASIC/VHSIC

microcircuits. The complexity attribute was handled by making the circuit

complexity parameter (i.e., number of gates, transistors or bits) a

variable in tlh stress derating criteria. Because of the large number of

27

Table 4-1 Attributes and Parameters ot Microcircuit Model Factors

Application to:

Factor Type Attribute / Parameter MOS Bipolar

PiQ CS Application Envixorment Y Y

PiT DS Technology Y Y

Ss Junction Temerature Y Y

PiE CS Application Envitoiment Y Y

PIJL CS Years In Production Y Y

Cl DS Circuit Technology Y YDrn Circuit CmPleRxity Y Y

C2 Ds Package Tecluology Y YDS Package C~mplexity Y Y

L CYC DS Circuit Opeiity I Y * NSS Number of Write Cycles Y * N

L TDDB DS Circuit Cmplexity Y NSS Juncticn Tempet-a-ture Y NSS Supply Voltage Y N

KEY: * - O Only

Computations reqUred, the C1 factor tables in the RA/AAT final. report were

transformed to continuous functions. A relationship between circuit

oamplexity and package comRlexity was developed from literature sources 5 7

such that the package complexity parameter (i.e., number of pins) could

also be handled in terms of the circuit complexity parameter. All other

rx4lationships required in the development of the derating criteria were

also based on cixuit complexity. It js noted here that all relationships

based on circuit complexity were always developed in a conservative fashion

28

such that the resulting stress derating criteria would be valid for all

complexities of microcircuits.

The criticality-specific attributes included the application environm'ent

attribute and the years-in-production attribute. The application

environments for the PiQ factor were always S-Level, B-Level and B-Level

for criticality levels I, II and III, respectively. The application

environments for the PiE factor were always SF, AU and GF. for

criticality levels I, II and III, respectively. These application

environments were chosen since they were the most closely related to the

application environments outlined by the criticality levels in the current

version of the Guidelines and resulted in the highest failure rate for the

criticality level they represented. The years-in-production attribute for

the experience factor, PiL, were always 2 years, I year and 0.75 years for

criticality levels I, II and III, respectively. These years in production

were chosen based upon current experience with component procurement for

systems that can be categorized by the definitions given for each

critical.ty level.

The stress-specific parm-meters, as mentioned previously, are the only ones

that, when changed, re ;ult in a different failure rate for any given

microcircuit. These parameters, temperature, voltage and number of write

cycl, (EEPROMs only), are the ones that can be traded-off to obtain the

're- f-'1m- r fn.r A ...iva ...i.n... ....iiit. A -as-nnn..ra h

was taken (with an exception for EEPROMs, see Section 4.3) in developing

the bounds for these stress-specific parameters such that the resulting

derating criteria would be effective, but not oppressive, in the desired

application.

This approach initially ignored the number of write cycles, or LCYC,

which was only applicable to EEPROMs. It was then assumed that, if the

time dependent dielectric brea&iý.dwn (TDDB) failure rate was not a factor

because wear out was not a concern, then the only s-tress-specific parameter

left was temperature. .t is noted here that the defect -related failure

29

rate (exponential probability density function) is a concern for allmicrocircuits and cannot be ignored. The independence of the TDDB-drivenwear out stresses and temperature is addressed in Section 4.1 in theexample of MOS digital ASIC/VHSIC microcircuits. For any microcircuit of agiven complexity, the temperature was calculated for which the failure rate

did not exceed the maximum failure rate given in table 3-3, dependent uponcriticality level. In calculating this maximum temperature, it was noted

that the maximum failure rate was not always the limiting factor. Becauseof the form of the failure rate equation, to solve for temperature imbedded

in the PiT factor rf-piired the term L(to)/(PiQ*PiIQ to be greater thanC2*PiE. Since L(to), PiQ, PiL and PiE are fixed for a given type ofmicrxcircuit, C2 controls the validity of the argument. For this reason,only microcircuits of a specified maximum complexity are acceptable in a

given criticality level. This complexity limit is included in the stressderating criteria for microcircuits when applicable. If the maximum

temperature was calculated to be a value higher than 175 degrees Celsius,

then 175 degrees Celsiut was c1h.sen. as the ma."'mum temperature.

Once the maximum temperature had been calculated for a microcircuit ofgiven complexity, it was noted that any operating teimperature below this

maximum temperature resulted in a calculated failure rate that was lessthan the maximum failure rate allowed by the criticality level. This

difference in failure rate could then be used to bound the stresses

associated with tie TDDB wear out mechanism. Table 4-i shows TDDB failurerates are only applicable to MOS microcircuits, and therefore, this

development of the derating criteria for supply current is only applicable

to MOS microcircuits.

Time dependent dielectric breakdown is a failure mechanism that results in

a component failure distribution that is normal with the logarithm oftime. That is, unlike the failure rates currently addressed by1MIL-HDBK-217 Revision E Notice 1, the TDDB failure rate is timedependentI. There are three factors that affect the rate of failure forTDDB, the electric field across the dielectric, the dielectric film

~30

temperature and the total area taken up by the transistor gates. A

relationship was also developedI between the latter factor andmicrocircuit complexity. When dealing with a failure rate model thatincludes LTDDB, it is assumed that the dielectric film temperature is the

same as the junction temperature defining the PiT factor. Therefore, wit.h

th& film temperature previously defired and the total transistor gate area

correlated to microcircuit complexity, the only factor that is not defined

is the electric field.

This electric field factor is proportional to the supply voltage accordingthe dielectric thickness Mhich is related to the complexity of the

microcircuit. The difference in failure rate between the maximum deratedtemperature and the operating temperature therefore defines the maximum

derating criteria for the supply voltage. That is, with the operating

junction temperature less than the maximum junction temperature, theresulting failure rate is less than the maximum failure rate allowed by the

criticality level. Therefore, the microcircuit could be operated with asupply voltage higber than the supply voltage allowed when operating at the

maximum junction temperature provided the maximum failure rate is not

exceeded.

With the device-specific, criticality-specific and stress-specific

attributes and parameters defined, the maximum junction temperature and

maximum supply voltage (MOS microcircuits only) derating criteria was

developed. For convenience in developing this derating criteria, softwareproTrams were written in FORTRAN 77 programming language. Appendix B

contains an example program written to calculate the temperature and

voltage values displayed in the graphs for MOS digital ASIC/VHSIC

mxicrcircuits. Once the derating values were calculated, a least squares

fit transformed this data into simplified equations dependent upon circuit

complexity. The simplified equations become the update stress derating

criteria for thie junction temperature and supply voltage stress parameters.

31

It is noted here that, in some instances, the calculated derated stress was

virtually independent of complexity. In that case, a constant derating

value was substituted for the derating equation. Also, if the calculated

derated stress was outside the region of validity of the reliability model,

the value of the maximum stress identified in the model was substituted for

the derating equation. For microcircuits, it was determined that the

applicable reliability models were based on junction temperature data that

did not exceed 125 deg C. Therefore, this maximum junction temperature was

used in those cases where the calculated derated junction temperature

stress was above 125 deg C. It is also noted that the microcircuit

reliability models outlined in the RA/AAT study were valid only up to a

specified maximum complexity. Although the data graphs generated and the

corresponding stress derating equations are continuous past the specified

maximum complexity, the stress derating criteria is not considered valid

beyond this maximum complexity. Therefore, the derating parameter of

"maximum complexity" is included in the list of derating parameters for

microcircuits.

since existing stress derating guidelines, other than those for the

stresses explicitly identified in the reliubility models, have purposely

affected the observed failure rates of components used in applications

corresponding to one of the three criticality levels, it was necessary to

review the existing stress derating guidelines to determine their relevance

in being included in the updated stress derating guidelines, given that the

factors being derated were not explicitly included in the current

reliability models. It was observed that failure data for components that

did not abide by the stress derating criteria war not readily available

(typically due to goverment or military contracts that require some type

of derating) and to arbitrarily remove this criteria may be irresponsible.

Therepore, the updated stress derating criteria for microcircuits includes

both the n-awly created criteria baced upon updated failure rate models as

well as the current criteria which was developed for parameters not

explicitly included in the updated failure rate models. It is noted here

that the only stress derating criteria included by the guideline sources

32

that outline three criticality levels were included n this proposed

revision of the Guidelines.

TI\ application notes for advanced technology microcircuits were developed

from a review of applicable literature, supplier surveys and other stress

derating glidelines. These application notes may be found at the end of

this microcircuit section and in Appendix A.

33

4.1 ASIC/"VHSIC MJICROCIRCUITS

ecause of differences in technjology within the ASIC/1 HS C category, stress

derating tables were developed for KoS digital, bipolar digital, MOS

linear, and bipolar linear ASIC/VHSIC micro-dircuits. The differences

between the criteria in each table were the results o.1 applying the

different davice-spealfic attributes and stresa-spe-eifc parmeters to the

failure rate equation. These attribute" and paxameters included

temperature activation energy (PiT), circuit comp:lexity (Cl), number." of

package pins (C2), total tý.nsistor gate area (LTDDB) and dielectric

thickness (LTDDB), Table 4-2 outlinA-s the values or equations used in

evaluating these_ device/stress-specific attributes.

Table 4-2 ASIC/VHSIC Device/Stress-Specific Attributes

Te±mnology I Attribute Value / Equation

MOS Digital Ea 0.35 eVCl 0.01 + 0.00042? * GATES *w 0.588Pins 11.07 * GATES ** 0.342C2 2.8E-4 * IINS ** 1.08Transistor Gate Area 1349 * TRANS ** 0.609 (sq umn)Dielectric Uidckness 4.93 / A * 0.266 (kA.)

Bipolar Digital Ea 0.60 eVCL 0.0025 + 0.0000977 * CATES ** 0.601x -'-- 9.16 * C-ZTES ** 0.377C2 2.8E-4 * PINS ** 1.08

Mos Linear Ea 0.65 eVCl 0.01 4 0.00150 * TAH ** 0.488Pins 3.69 * GC5- ** 0.318(2 2,8E-4 * PINS ** 1.08iTransiLstor Gate Area 1349 * TRANS ** 0.609 (sq Ui)

Dielectric Thickn)es 4.93 / 'J•NS ** 0.286 (kA)

Bipolar Linear Ea 0.65 eVC1 0.01 4 0.00150 * TPI\NS ** 0.488Pins 8.69 CM-S ** 0.318C2 2.8E-4 * PINS ** 1.08

34

The temperature activation energies were obtained directly from the tables

provided by the RA/AAT final report. The Cl factor equations were derived

by fitting the Cl factor data associated with the RA/AAT failure rate

models to an appropriate curve. The data and best fit curves are shown in

figure- 4-1, 4-2 and 4-3 for MOS digital, bipolar digital ai ] MOS and

bipolar linear ASIC/VHSIC microcircuits, respectively. The re itionships

between package pin count and circuit complexity for MOS digital, bipolar

digital and MOS and bipolar linear ASIC/VHSIC microcircuits are shown in

figures 4-4, 4-5 and 4-6, respectively. The data from which tbe

relationship betaeen total transistor gate area and circuit complexity was

derived Js shown in figure 4-7 for MOS digital and linear ASIC/VHSIC

mirrocircuits. The dielectric thickncss dependence on circuit complexity

for" MOS digital and linear ASIC/VHSIC microcircuits is shown in figure 4-8.

By applying the approach outlined in section 4.0, maximum junction

temperatures and maximum supply voltages were calculated for the four

AZCJkl ... tochrhologics as a function of circuit complexity1,. Figure•• s 4-9

and 4-10 show the junction temperature and supply voltage derating curves

for MOS digital microcircuits. Figures 4-11 and 4-12 show the junction

temperature and supply voltage derating curves for MOS linear

mu,-rocnrcuits. Figure 4-21 is also the junction temperature derating curve

for bipolar linear microcircuits. Since bipolar ASIC/VHSIC microcircuits

dc- not experience weiar out due to TDDB, supply voltage derating curves are

not calculated for the.se technologies. Fri.gure 4-13 shows the junction

temperature dcrutýi-g curves for bipolar digital microcircuits. The solid

lines on the grapls in each figure represent the best least squares fit to

the calculated denating values. These equat .ons of the lines are the new

stress derating criteria for each criti.calJity level.

35--

Figure 4-1 C1 Factor for MOS Digital Microcircuitsl

I0

S"4--

00)

CCO0:)

e 000

C;C

CC t

00

3Z6

Figure 4-2 CI Factor for Bipolar Digital Microcircuits 1

0 C3 U)C

- E U

• E

to

a)r

o C +

z 0

0"•- 0

a) I

E1

0 o

_ 0 q4 U 0

U, C)

37

Figure 4-3 CI Factor for 140S and Bipolar Linear microcirc'Lits5

(D0C:-

C1CD

CO

z :

cc Ex

C:U

V 0

CI) q

0E 0

EECL00

C) 0

:3~

Figure 4-4 Package Pin count for MOS Digital MiCrOcircultS5 7

00

0CLC

CD

4-'ý

cboD

0 " 03_C

z

T-1.

E0

o 0 0 0 0 0 0to) U') 4, C() j

39

Figure 4-5 Package Pin Count for Bipolar Digital Microcircuits57

N E

> 0

(D 0)E 0_cc 0

0- 0CL0 QI C%

FLC CD

C oo o

0.0 0 0 0

(0 04

40

aee

Figure 4-6 Package Pin Count for MOS and Bipolar Linear Microcircuits 5 7

0aLaCO

>0

o Eao ° 5°

EE

E x

,C_: 0 C0

0~0

"W~~ C04",

441

CO (

EZE

CI zn) & I CD,

00

00

ci41

Figure 4-7 Tjransistor Gate Area for MOS Digital and Linear Microcircuit-s1

Ci)

0O

0 CoU) coc

O o 0

-IE EO

co EJ

co~

co f-c

~%~% 42

Figure 4-8 Dielectric Thickm-ass for MO,,.. Digital and Linear Microcircuit-sl

Co-Co

C) 0

C c E

W (0)Z

C 0U

C:)

4Q ) >

- 0 CCo

ccCD

-CM

I-J

4-3

Figur-e 4-9 Junction Temperature Derating for MOS Digital ASIC/VHSIC

L0

5cn ,*

,a) &-

.

0n(5o. 4-

C J CL C

E a 1 03 -

0)

LO~1 0" LO 0iO. 0) f-

44~oo

Figure 4-10 Supply Voltage Derating for MOS Digital ASIC/VHSIC

CO,(Dp

>I

,)> I D

0.

C >

0 M

0 _ 45

o~k / .1

a5 >

< 45

Figure 4-11 Junction Temperature Derat-ing forBipolar/MOS Linear ASIC/VHSIC

CI)!

o Lt

.o . _=__

1~. 1 a C 00

-- __- _" _0

':,tI I I~" 9 >

00

V __ __ ___oo

CO -5 _5 __

- ,,

CL l

,) 0 C0 0 L/

1I- 'IM

2

EE

CO O3 ocO u O U

-P w-- I - --E-

X4

~~CI I I I I I I I )I I I I

iFigare, 4-12 Supply Voltage Derating for MOS Linear ASIC/VIUSIC

(D >

__ _ LO=

(1) 0

C/) J-1 I 50~o

N- (

I O~

0t

co t 0N (f) (T) )

47

Figure 4-13 juny-tol- ¶Iemprerature Derating for Bipolar Digital ASIC/VHSIC

_____ ____LO

C, ~00

P CCj - -

EEM -0 E E

:L- E .

Z ili

C"

U) 0~ 0 0 U

0- It) (' 0 t- UI) 01J

48

Supplementing the junction temperature and supply voltage derating

parameteas were the stress derating parameters outlined, by other derating

guideline sources and shown in tables 4-3, 4-4, 4-5 and 4-6 for MOS

digital, MOS linear, bipolar digital and bipolar linear microcircuits. In

keepirg with the general approach outlined in Section 3.0, and because of

the uncertainty of criticality assumed with guideline sources not

specifying three criticality levels, only those guideline sources supplying

derating criteria for three criticality levels were evaluated for inclusion

in the updated guidelines. For each parameter specified by these guideline

sources, a median value for the parameter was chosen. In the case where

the choice was between an even number of values, the average of the two

median values was calculated and then rounded up.. Priority was given to

those guidelines specifyirct advanced microcircuits, such as VLSI and gate

arrays. The remaining guideline sources were used only as a "sanity check"

of the updated stress derating criteria. Table 4-7 summarizes the new

stress derating criteria for ASIC/VHSIC microcircuits.

As addressed ii-, section 4.0, the complexity of the ASIC/VHSIC device is

limited by the criticality level. Although the higher criticality level

(Level I, for example) derating criteria allows a more complex device to be

used, the allowed stress is typically less than the strcss allowed at the

lower criticality level (Level II, for example).

For MOS ASIC/VIRSIC microcircuits, both maximum junction temperature and

maximum supply voltage are a function of circuit complexity. Therefore,

these two parameters can be conbirbad to form effective Safe Operating Areas

(SOAs) for these microcircuits. Figures 4-14, 4-15 and 4-16 display the

SOAs of MOS digital microcircuits for criticality levels I, II and. Ill,

respectively. In each graph, the top set of SOAs is for a ICWO gate

micocizrcuit the middle set of SoAs is for a 10,000 gate microcircuit and

the bottom set is for a 100,000 gate microcircuit. Multiple SOAs are

displayed as part of each set of SOAs according to the required lifetime of

the microcircuit. The "squareness" of the SOA indicates the level of

independence of the temperature and voltage factors.

49

Table 4-3 ASICNHSIC MOS Digital Microcircuits Guidelines

DYNAMIC OUTPUT MAXIMUM MAXIMUM

CTF'-fUTY SUPPLY FREQU4ECY CURRENT JUNCTION OPERATINO

L.EVEL GUIDINE VOLTAGE (POMS) (FAN GUTI) TEMP, TEMP.

(PORy) Por" (dog C) (dog C)

AMB 70 80 8o as NL

C 75" 80 . 70(80) 85* NLI D 75* 80 70 (80) 85 * N1.

E 70' s0 80 as NILF 100 NL 80 NL 30 C FAL

A&B 85 80 85 100 NLC I0 t 8 0 7 5 ( 8 M) 0 0 N L ID so . 80 75 (80) 100 * N L.

E 80 8s 90 100 NLF 100 NL 90 NL 20 C FML

A&E a 90 90 110 NL

C 95 80 80 (90) 125 * NLI=. I i. * NI

E a 90 90 110 NLF 100 NL 100 NL 20 C FML

-- ~~~~ ~~ -___________ --- J-

0 90 9C 80 NL 85NIONE Hi- (Nomlnl - NL 80 110 NLSPECIFIED J NL 75 80 110 NI.

K 70* 80" 80* 95 NLL (NomInaJ) 70 80 100 NLM 8o NLI 80 125 NLW 100 50 80 65 PORV 30 C FML

X Voc +/-0,5V NL 75 125 NL

Kz-EY: FML - From Mexlmum UmIt- cw'zrpd'. M~~cc~iipoMS- PFiC6-i v-

NL - NW UglWd PORV - Percert of Rated Value

50

Table 4-4 ASICNHSIC Bipolar Digital Microcircuits Guiaelines

DYNAMIC OUTPUT MAXIMUM MAXJMUM

rBITKALITY Qa.INE SUPPLY eMUPPY FREOUENCY CURRENT JUNCTION OPERATING

LEVaEL VOLTAGE VOLTAGE (POMB) (FAN OUT) TEMP. TEIP.(POFt) (pO" (Clog P (dw C')

A&B +/-3% NL 80 80 85 NL

C +/. 3%* NIL 75 * 70(70) * 55. NLD NL 75* 75 * 70 (70) * 85 NLE 4+-3% NL. I0 &0 85 NLF NL NL NL 70 NL 33' C FML

A&F3 +/-5% NL 90 85 100 NL

C +-5% NL 8go. 75(75) * 100 NL

D NL 80 o80 75 (75) * 100, NL

E +/-5% NL 90 90 100 NL

NL NL HL 80 NL 25 C MWL

C +/-5" NL 90* 80(80) - 125 * NL.D NL 85 90 E0 (80) 12L * NL

E Pe Sm. NL 05 90 1le; NL

F NL NL NL 900 NL 20 C FML

G +/-5% NL g0 80 NIL 85NONE H NL (Nonilna) NLi 80 110 4L.&P-CIFIOD J NL NL 75 so 110 NI.

K NIL 70 o80 801' 85 PIL

L NI. (NomInal) 70 100 NL

M 10 % NL NL 80 125 N',WNia '0 no POCiv 300FML

x +/-0.5V NL NL 75 12.- Ni.L

C~rt*xP~uaft P0MS Pmcwo of k Op~~x dMIoNIL U•o Dd POWN - PvrWOr of PW V

51

Table 4-5 ASICNIVSIC MOS Linear Microcircuits Guidelines

C~nA-r UD- SUPI>tv INPUIT FRCO, OIUTPfT PO`NER MAX MAXCRI1CU~' OiIE~ VOLTAGE VOLTAGE (PM UFA-NT Gu) ISIP71N TEM OFP.

LEVL UES PORVO Form(PO (PON PTJ (dog C;) (dog C)

AMB 70 60 NL 70 NL so NLC 75' NL 80 * 70 (80) * NL 85. NLD 75' NL 80 * 70 (0)' NL a 1 N

E 060 NL 70 NL 80 NLF 060 NL NL 55 VP. ACFML

AMB s0o0 NL 75NL C5 NLBC 80* 70 ~ NL 75(80)' N 95' NL

O go' NL I 80' 75 (80)* NL 100* NLr 60 70 I NL so Nt. 95 NL

FM 70 0 NL NL 8 L 2 M

AC & 70' t 0 ) Nt. oin, Nt.

o 85* N. 80* so(w0) Nt. 125' NLF so 70 Nt. no Nt. 105 NL

Gi 90o 90 Nt. so 75 Nt. 95H- 80 s NL 70 Nt. 110 Nt.1~~If 70 70 7575 6o 110 NL

K so0. 100 Nt. SG 75"* 100 Nt.L (NomlnAi 75 Nt. 70 50 Nt. 125

MNt. 80 85 as 85 125 NLso8 65 s0 75 Nt. 6OPOfIV 30 C ML

L . 75_ 75 Nt. Nt. Nt 125 Nt.

"t.y C~xirAex Ma cutFML -From Maximrum Iimh

"'Worul cuea; w~gm v~r~tkw-s iiiýuqj 'P-' - Pemewi ol Maylmum Soect~eddfreodlng on da1vie type PORV/ - Parcerd ol Baled Value

Nt. - Nat LisWed

Table 4-6 ASICNHSIC Bipolar Unear Microcircuits Guidelines

CRITICAJTY SUPPLY INPUT OUTPUT POWER MAXIMUM MAXIMUM

OUIDtEUIN VOLTAGE VOLTAGE FREQUENCY CURRENT DIS31PATION JUNCTION OPERATINOLEVEL (PORV) (PORM (POM8) (FAN OUl) (POTM TEMP. TEMP.

(PoI' (dog C) (dog C)

A&B 70 60 NL 70 NL 80 NL

C +/-3%' NL. 75' 70 (70) * NL 85 * NLD 75 NL 75• 70 (70) * NL 85 * NIL

E 70 60 NL 70 NL s0 NL

F 80 60 N1- NL 55 NL 30 C FML

A&i +5 70 NL 75 NL 95. NLh c5%0 70' NL 75(75)- NL 95 NL80' NL 80' 75(' NL 100 k

E 80 70 NL 80 NL 95 NLF 80 60 NL NL so NL 25 C FML

,&B 80 70 NL so IhL. 105 NL

C +/-5% 70 NL 80(80)- NL 105' NLD 85 NL 90 * 80 (80) NL 125' NLE s0 70 NL G0 NL 105 NL

80 60 NL NL 90 NL 20 C FML

NONE 8 50 70 NL 80 75 NL 85OPECIrF•ID H 75 80 NL "0 NL 110 NL

J 70 70 75 75 60 110 NLK g0o. 100 NL 80 75 100 NLL (Nominal) 75 NL 70 50 NL 125

M NL 80 85 85 85 125 NL

W so 65 so 75 NL 60 PORV 30 C FMILX 75 75 NL NI- NL 125 NL

"KEY' -C= t HAMwroudroLV PCFff Pwsr4w of fRmod VimNL - NW Uh' ** - Wormt cae; zlkght vwlatlons likotyFML - Fron MuYmRri I" depenrvIrhg on d" ce typePO.Me u Pwmw of Mamnrn uDidped

53

Table 4-7 ASICNHSIC Stress Derating Criteria

-j r-- O ~ +

Lo

CS 6

-6 C 008,iO' n DnOU

Go ~ ~ ~ ~ 4 +ZC 0 1 t o ,c \ - r

C? 0

gE co 51111

:) . ?--~: c

.2, i , Z' -

-f 0

~~o~~Lo -*O~

c& ctd E LI w EcE 0 a) a

a 0 C >0 l-a

cn 2..L:E 54

Figure 4-14 Criticality TLvel I SOA for MOS Digital ASIC/VHSIC

tLO

0"to 0

0

W 00

0

No -o 0o

q5 't 0

"-" o 00

S- -- - - -

0

C I Q)

400

0 C~0

CLC

- ~ r 0

0)j T) aD C-w " - f'

4- 0kg5

Figure 4~5Criticality Level II SOA for MOS Digital ASIC/VHSIC

LO

00

LO0

0) 00

Uj) C 0o 0)

00

C4)0) > 0)

4.'40

0 I0oo 4) 04 0)c'

Figure 4-16 Criticality I~evel III SQA for MOS Digital ASIC./VHS3ZC

LO1

LO

-L

0 40

u-) IT 0

0)0

C0 0:

C) -10

% _ s- 76 i

Co

4-1

'a MUC

>0n

4--

Cji co C

57

4.2 MICROPROCESSOR MICROCIRCUITS

Tje stress derating criteria for microprocessors was developed similarly tothe ASIC/VHSIC microcircuits, with two exceptions. First, the lack of

stress-failure data and reliability models for bipolar or MOS linear

microprocessors precluded the development of derating criteria for thesetechnologies. Second, the circuit complexity factor, Cl, in the RA/AAT

failure rate model was a function of bit count. Therefore, stress deratingtables were generated for the three categories of microprocessors, 8-, 16-

and 32-bit, for both MOS digital and bipolar digital technologies. The

differences between the criteria in each table were the results of applying

the different device-specific attributes and stress-specific parameters tothe failure rate equation. These attributes and parameters included

temperature activation energy (PiT), circuit complexity (C1), number of

package pins (c2), total transistor gate area (LTDDDB) and dielectric

thickne-ss (LTDDB). The values or equations used in evaluating the

device/stress-specific attributes ar ouutlined in table 4-8z

Table 4-8 Microprocessor Device/Stress-Specific Attributes

Technology Attribute Value / Equation

SDigital_ Ea 0.35 eVCl 0.14C). 0.28cl 0.56Pins 11.07 * GAMES ** 0.342C2 2.8E-4 * PINS ** 1.08Transistor Gate Area 4047 * TRANS ** 0.463 (sq urn)Dielectric Thickness 28.18 / TRXIS ** 0.412 (kA)

Bipolar Digital Ea 0.60 e7Cl 0.06C1 o0.12C1 0.24Pins 9.16 * GATES ** 0.377C2 2.8E-4 * PINS ** 1.08

58

The temperature activation energies and C1 factor values were obtained

directly from the tables provided by the RA/AAT final report- The

relationships between pin count and circuit complexity for MOS digital and

bipolar digital microprocessors are the same as the relationships

associated with MOS digital and bipolar digital ASIC/VHSIC microcircuits,

respectively. The. circuit complexity dependence of total transistor gate

area and dielectric thickness for MOS digital microprocessors are shown in

figures 4-17 and 4-18, respectively.

By applying the approach outlined in Section 4.0, maximum junction

temperatures and maximum supply voltages (MOS) were calculated for the two

microprocessor technologies, three bit counts each, as a function of

circuit complexity. Figures 4-19 and 4-20, figures 4-21 and 4-22 and

figures 4-23 and 4-24 are the junction temperature and supply voltage

derating curves for MOS digital microprocessors of 8-, 16- and 32-bit

complexities, respectively. Figures 4-25, 4-26 and 4-27 are the junction

temperature derating curves for 8-, 16- and 32-bit bipolar digital

microprocessors, respectively. The solid lines on the graphs in each

figure represent the best least squares fit to the calculated derating

values. These equations of the lines are the new stress derating criteria

for each criticality level.

It is noted here that a review of the range of complexities within each

category of microurocessor showed the transistor counts varied marginally

for 8-bit microprocessors (22,000 to 27,000 transistors) as compared to

16-bit (30,000 to 120,000 transistors) and 32-bit (80,000 to 1,000,000

tmasistorsj) wicroprocessors. Therefore, an approximate worst case 8-bit

microprocessor complexity of 10,000 gates was assumed and the stress

derating equations for 8-bit microprocessors were changed to the values of

those equations at the 10,000 gate complexity.

supplementing the junction temperature and supply voltage deraUlng

parameters were the stress derating parameters outlined by other derating

guideline sources as shown in tables 4-9 and 4-10 for MOS digitEI

59

microprocessors and bipolar digital microprocessors, respectively. In

keeping with the general approach outlined in Section 3.0, and because of

the uncertainty of criticality assumed with guideline souirces not

specifying three criticality levels, the method for evaluating tlhe stress

derating criteria for microprocessors was the same as the method used forevaluating the stress derating criteria for ASIC/VHSIC microcircuits.

Table 4-13 summarizes thc nmw stress derating criteria for microprocessors.

60

Figt--e 4-?- Transistor Gate Area for MOS Digital MicroprocessorsI

CO)

0C I) ( D_ - _ _ _

0E E

,Q. :3 m O.

0 E

L---

0 OI

-2- r)

41!1

COC

(~ 61

Figure 4-18 Dielectric Thickness for MOS Digital Microprocessors 1

LO

(IIN

00

I - _ _ CXE

C)0 <0O

0 0

00w Eo

00

< Q

-C X

62')

CO.?)

o L~ C C) K1C

62

Figure 4-19 Junction Temperature Derating for8-Bit MOS Digital Microprocessors

LC4)

0 1 tE" Cr

09.•-

/: 00 :.: 4 . ",• '• m •-

CL -- O

,• ---

nD-,-

to 0- U1. 0 • O Cit) C* r_ U*

63 :----

Figure 4-20 Suppl~y Voltage. Derating for

8-Bit MOS Digital microprocessors

W(a

CLz CL 0 :3 -

00

E'tE 7

C)e

tO C' O ) CV)IL 1j a ( f

64

Figure 4-21 Junction Temperature Deratingfor 16-Bit MOS Digital microprocessors

_____CD

I _ _

0-•0

U) I- - _ L6

o /(1

C)A

€-,

CO LO OC'-2•D 00 )

265

:3 CD

Z. E- / -

CI) LLJ

00

CII

Q 0 ) 0 tf '

65

Figure 4-22 Supply Voltage Derating

for 16-Bit MOS Digital Microprocessors

(0

0 0 ECO>

CC)> 0.L- Ci >!CL) CIEX

00

,O 0"-_ I /E 0"E

.-- E 0)0

- - - -

- U

>>

V)6>

0C X' ) (0 C

0 Y.1

66

Figure 4-23 Junction Temperature Deratingfor 32-Bit MOS Digital Microprocessors

I G)

/ "-

CO

0 E0 x

0 0-

0 >'

•4- CO-J "

0CzC

U- 0 tno •o 0 n o '

67 ---

l'o

Figure 4-24 Supply Voltage Derating

for 32-Bit MOS Digital Microprocessors

* >

0U

co0)

q >

':1) / 0 --

C)L IQ

00

E 0)

._ -

0 I I

0i) >

) Li)

4O >

00

C9 L

co Li) C' ) (0 C C)

68

Figure 4-25 Junction Temperature Deratingfor 8-Bit Bipolar Digital Microprocessors

, U)

o,

SE D0 0

.=

.0 ~4) 4)I>-j

S' ' 4-J 0

00

00. 0

LLC

LO 0 U") 0 to 0 LO0I'- U-) (i 0 I1- U) 04

69

Figure 4-26 Junction Temperature Deratifl(

for 16-Bit Bipolar Digital Mi~croprocessors

7F)4)

0 U-)0(.3E >x

(D0

4) 0

OI1 a --

0.2 '

C) 0

EE

E C

07

Figure 4-27 Junction Temperature Deratingfor 32-Bit Bipolar Digital Microprocessors

I 'E -

>

I 0"

0.)So., g, =.

S__ /I"E I

0L-CL E _ __- LO

O InOI 0 In 0f(-- U' C4 0 0- In 04

7)1J

Table 4-9 MOS Microprocessor Guidelines

DYNAMIC OUTPIT MA)OMUM MAXIMUMCUmNCAUTY SUPPLY FFEOUENCY CURRENT JUNCTION OPERATING

LEVEL GUIOEUNE VOLTAGE (POMS) (FAN OUT) TEMP. TEMP.T (OV (POW (deo C) (dog C)

A&B 70 80 80 85 NLC 75 * 80 * 70 (80)* 85 NLD 75 * 80 * 70(80)- 85* NLE 70 80 80 85 NLF 100 NL 80 NL 30 C FML

A&B 85 80 85 100 NLC 804 80 * 75 (80) * 100 * NLD 80* 80 * 75 (80) * 100 * NLE 80 80 90 100 NLF 100 NL 90 NL 20 C FML

AD5 90 90 110 NL

C 85 80* 80 (90) * 125 * NLD 85* 80 80(90) * 125 * NL

E 80 90 90 110 NLF 100 NL 100 NL 20 C FML

G NL 90 NL NL 85NONE H (Nominal) NL 80 110 NLSP..iFIED J NL 75 80 110 NL

K 70* 80* 80* 85 * NLL (Nominti) 70 80 100 NLM 80 NL 80 125 NLW 100 50 80 65 PORV 30 C FMLx Vcc +/-0,5V NL 75 125 NL

KCY: FML - From Maimum Umit* - Comp4ex Mlro•irCulRN POMS - Po.rcet of Makimum SpecifledNL - Not Ustod PORV - Pero*M of Rated Vaiue

72

Table 4-10 Bipolar Microprocessor Guidelines

FDCED DYNAMIC OUTPUT MAXIMUM MAXMUM

CI TICALITY GUIDEUNE SUPPLY SUPPLY FRFQUENCY CURFENT .JUNCTION OPERATING

I.EVE. VOLTAGE VOLTAGE (POMI (FAN OUT) TEMP, TEMP.

(PORV) (PORV) (dg C) (do C)

A&B +/-3% NL 80 8O 85 NL

C +/- 3% NL 75. 70 (70) * 85* NL

o NL 75 75* 70 (70) * 85* NI.

E +/-3% NL so 80 85 NL

F NL NL NL 70 NL 30 C FML

A&B +1-5% NL 90 85 100 NL

C +/-5%* NL 80* 75 (75) * 100 * NL

D NI. 80 80 75 k75) * 100 * NL

E +/-5% NL 90 90 100 NL

F NL NL Ni, 80 NL 25 C FML

A&B +/-S% NL 95 j 90 110 NLC 5% NL o s 80(80) * 125 * NL

D NL 85* 90 *U(&i 125 * NL

E Per Spec. NL 95 90 115 NL

F NL NL NL 90 NL 20 C FML

O +/-5% NL 90 NL NL 85NONE H NL (Nominal) NL 80 110 NL

SPECIFIED J NL NL 75 80 110 NL

K NL 70* 80 s0 85 * NLL NL (Nominal 70 80 100 NL

M 10% NL NL 80 125 NL

W +/-5% NL so so 65 PORV 30 C FML

X 0.5v NIL NL 75 125 NL

KFY: FML - From MlajmUrr

" Cmwiea mkro¢ POMS : P•ort of MagIJvrn Sokd

NL - NoI Ujgd PORV PWVV0 Of PAW Vmkm

73

Table 4-11 Microprocessor Stress Derating Criteria

66,,

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74

w I0 II [

4.3 PROM MICROCIPCUITS

The. stres derating criteria for PROM devices was developed similarly to

ASIC/VUSIC miarncircuits, with exceptions for EEPROMY. These exceptions

centered (in the need to include the LCyC term in the failure rate model

of eqwittion (2). The differences between the criteria in each table were

the results of applying the different device-specific attributes and

stress-specitl parameters to the failure rate equation. These attributes

and parameters included temperature activation energy (PiT), circuit

complexity (C3), number of package pins (C2), total transistor gate area

(1 TDDB) and dielectric thickness "LTDDB). The values or equations used

in evaluating the device-spacific and stress-specific attributes are

outlined in table 4-12.

The temperature activati.on energies were obtained from the pre--release

version of MNIl-HDBK-217 Revision F. The Cl factor equations were derived

by fitting the Cl factor data associated with the RA/AAT reliability models

to an appropriate c,,rve. The CI data and best fit carves are shown in

figures 4-28 anid 4-29 for MOS PROMS and bipolar PROMs, respectively. The

value for maximum pin count was derived by exarniation of current supplier

Table 4-12 PROM Device/Stress-Specific_ Attributes

___~ahn AtrhE ciuationI7iirr I - _ aIi _-- _

WIG Ea 0.60 evC! 0.00085-: 5A5E-6 * Bfl5 w* 0.515Pins 40C2 2.88E-4 * PINS ** 1.08Tr-ansistor Gate Area 3..209E6 (sc urn)F1)ic1c--ric thickness 2.31 / BITS ** 0. 175 (VA)

BiroAlar Ea 0. 60 cVCl 0.0094 4 6.20E-5 * BITSJ *k 0.514PinEs 40(22 2-8E-4 * P1715 ** 1.08

"¶5

Figure 4-28 Cl Factor for MOS PROMS 1

I LL

OO 0

4* C Eto E0~

f-r x

LU .

I E El

c'z

C- 04)

o7 6

F.'gure 4-29 C1 Factor for Bipolar PROMsI

LL

-- I - (0--

U +

001 m -

0 C0

SE 0

0. c E

00

i9 i t.._o Ir

ca

4-

04 0

7m

o N

0 =

• 77

data books which described memory complexities up to one megabit- The.

total transistor gate area for MOS PROMs was extracted directly from the

RA/AAT final report. The dielectric thickness dependence on memory

complexity for MOS PROMs is shown in figure 4-30.

By applying the approach outlined in section 4.0, maximum junction

temperatures and maximum supply voltages were calculated for the two PROM

technologies as a function of memory complexity. Figures 4-31 and 4-32

show the supply voltage derating curves for MOS PROMs excluding EEPPh)Ms and

EEPROMs, respectively. The maximum supply voltage for EEPROMs is lower

than the maximum supply voltage for other PROMs because it was. traded off

with the number of write cycles. It is noted, however, that the difference

in supply voltage between EEPROMs and other types of PROMs of similar

complexity is at most 0.85 volts. In the trade-off between supply voltage

and number of write cycles for EEPROMs, the only guideline used was the

requirement was that the supply voltage remain above 5V for all EEPROMs up

to"' 1 Mbit complexity for any criticality level. Figure 4-33 shows the

write cycle derating curves generated for EEPROMs. Since bipolar PROMs do

not experience wear out due to TDDB, supply voltage derating curves are not

calculated for this technology. The solid lines on the graphs in each

figure represent the best least squares fit to the calculated derating

values

Supplementing the junction temperature and "*-"7s ,VltAe derating

parameters were the_ slress derating parameters outlined by other derating

guideline sources as shown in ta•bes 4-13 and 4-14 for MOS PROM devices and

bipolar PROM devices, respectively. In keeping with the general approach

outlined in Section 3.0, and because of the uncertainty of criticality

assumed with guideline sources not specifying thiree criticality levels,

only those guideline sources supplying derating criteria for three

criticality levels were evaluated for inclusion in the updated guidelines.

For each parameter specified by these guideline sources, a median value for

the parameter was chosen. In the case where the choice was between an even

78

Figure 4-30 D~ielectric Th~ickness for NOS PROMs 1

IF

0 0

tO E

Tc_ __ _ _

____ ___-I-. -_________ L OCD ~ C -W.

2 L.

~U 0~; ------ 6

OR(C)C 6L79

Figure 4-31 Supply Voltage Der-athig for MOS PROMs Excluding EEPROMs

I-

!! ')I ,D

00

CmD

080

> E E

C -

z >

__ 0

Wa f

80

Figure 4-32 Supply Voltage Derating for EEPROMs

U'))ix

-l

I• -II

U) - - --- - . O-

CL

/ /--

/ //0I I l

_'I- -

I _//__-IL)_

z (Dwao -J-

>

D .CQ

wr: C)

Figure 4-33 Write Cycle Derating for EEPROMs

LO

(D i

C i) ell.Uu"o

x

Cu z

o / 0----

- LO Cf )J

U._) .Of: EM N 0

08 -. ... LO Lo73o o o

0 0n 0 0n 0 0 0

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Table 4-13 MOS PROM Guidelines

DYNAMIC OUTPUT MAX]MUM MAXIMUM

CmCAUTY SUPPLY IREOUENCY CURRENT JUNCTION OPERATING

LEVEL GUIDENE VOLTAGE (POMS) (POTEMP. TEMP.(PORV) (deg C) (deg C)

AB70 80 80 85 NLC 75* NIL 70 * 85 * NILD 75* NIL 70 * 85 * NLE 70 80 80 85 NLF 100 NL 80 NL 30 C FML

A&B 85 80 85 100 NILC 80 * NIL 75 * 100 * NILo 80 * NIL 75 * 100 * NLE 80 80 90 100 NLF 100 NL 90 NL 20 C FML

A&B 85S 90 -90 11!0 Nt"

C 85* NL 80* 125* NLD 85* NL 80 * 125 * NLE 80 90 90 110 Nl-F 100 NLt 100 NL 20 C FML

SG NL 90 NL NL 85H (Nominal) Nt 80 110 NtLC Nt 75 80 110 NtL

K 70* 80* 80* 85* NLL (Nominal) 70 NtL 100 NLM 80 NL 80 125 NLW 100 50 80 65 PORV 30CFM.LY Vc? +/-0.SV NL 75 125 NL

KEY: FML . From MuNJnumn Umlt* - Complex Microcircuit POMS - Per.MTat 01 Mxmmurn Spncffie

NL - Not UiW PORV -' Pw.tt of Ratad VaAke

83

Table 4-14 Bipolar Prom Guidelines

FIOED DYNAMIC OU'FUT MAXIMUM MAIMUM

CP,;TFALITY GUIDELUNE SUPPLY SUPPLY FREQUENCY CURRENT JUNCTION OPERATING

LEVEL. VOLTAGE VOLTAGE (POMS) (PORW) TEMP. TEMP.

NI.NI-- 70NI(PORV) (dog C) ((*a C',

A&B +/-3% NL so so 85 NL.C +/- 3% NL NL 70 * 45 . NL i ,=

ID NL 75 *NL 70 * g5 * NL E

E +1-3% NL 80 so 85 NLF NL NL NL 70 NL 30 C FML

A&B +/-5% NL go as 100 NLC -5% *NL NL 75 * 100 * NLD NL. 80 *NL 75 * 100 *= NL

E +/-5% NL 90 90 100 NLF NL NL NL so NL 25 C FML

MEB ,.-,% NL 95 90 110 NLC /-5%* NL NL 80s 125 * NLD NL 85* NL 80* 125 * NLE Per Sp•c. NL 95 90 115 NLF r4L NLL so NL P0 C FMIL

NONE G +/-5% NL 90 NL NL 85SPEOFIED H NL (Nominal) NL 80 110 NL

J NL NL 75 80 110 NLK NL 70* 80 80. 85 . NLL NL (Nomlnal) 70 NL 100 NL

M 10% NL NL 80 125 NL.W +/-5% NL 5s 80 65 PORV 30 C FML.X +/- 0.5V NL NL. 75 125 NI J

KEY: FML * From Mrun LmUA. . Canipin kx ocVcift POMS" Pow"~ of Madmu¶ SpeogodHL W Mof LAWd PORV - Pvot of 'Nhd Van

84

number of values, the average of the two middle values was calculated.

Priority was given to those guidelines specifying advanced microcircuits,

such as VLSI and gate arrays. The remaining guideline sources were used as

a "sanity check" of the updated stress derating criteria. Table 4-15

summarizes the new stress derating criteria for PROM microcircuits,

including the pertinent stress derating criteria from the current version

of the Guidelines.

8,!a)

Table 4-15 PROM Stre~ss DeratiJ-fg Criteria

CC

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o 81 *- eaion

co+

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ao 4--.

p~ 46

4.-

1- 413 CL im a4.

-6 -1:sIu t LI L

4 41

I- 44. - 434- 4)- 0 0 w

'n *n .C 43

4. . c 0 0

434-

0-0

:>:- >~~~3L >> U4.U 4 40C

L)I. 31 d 3

>,>~ 9 --. 04 86

4.4 MICROCIRCUIT APPLICATION NOTES

The following application notes for advanced technology microcircuits were

developed from a review of applicable literature, supplier surveys andother stress derating guidelines. These application notes may also be

found in Appendix A.

Digital Microcircuits:

1. Advanced technology microcircuits are sensitive to ESD.2. Unused inputs should be connected to a supply voltage or grcand.3. Supply filtering is required to filter out transients.4. Heat sinks may be required to maintain der;ted junction temperatures.5. Design margJns should be used for input le-akage (+100%), fanout (-20%)

d frequency (-10%).6. uood engineering judgement should be used to derate other microcircuit

characteristics, including hold and propagation delay times, toproduce a conservative design.

7. circuit design must avoid application of reverse voltages on deviceleads.

8. Do not exceed the current density derating described by the equationCurrent Density = 366 / (Temperature in deg. C ** 1.67)

or 5E5 A/cm2 , whichever is smaller, for aluminum-based metallizedmcrocircuits for either internal circuit operation or output driveroperation (see figure 4-34).

9. (Bipolar) Supply voltage deviations from rthe specified nominal willshift. internal bias points which, when coupled with thermal effectscan cause erratic performance.

10. (MOS) Input destruction may cxxur by shorting leads during assembly.11. (MOS) High speed transients may result in parasitic bipolar latch-up.

Linear Microcircuits:

I. Each liiear device is unique and the designer should have a thoroughknowledge of its application requirements to assure that the device isoperated within its performance envelope at all times.

2. Heat sinks may be required to maintain derated junction temperatures.3. Design margins should be used for gain (-20%) and offset voltages and

currents (+50%).4. The circuit design must avoid application of reverse voltage on device

leads.5. Do not exceed the current density de- ating described by the equation

Current Density = 366 / (Temperature in deg. C ** 1.67)or 5E5 A/cm2, whichever is smaller, for aluminum-based metallizedmicrocircuits for either internal circuit operation or output driveroperation (see figure 4-34).

87

Figue 434 a~cu~mcurrent tXonsitY fýor ImircrociXcuits

LO

00

C__ LC)

000

CU 44V)

13L

ID 0)

C5)

_ _ F-I C

C0~

de-

0))

C~

88

5.0 MIMIC DERATING GUIDELINES

For advanced technology MIMIC devices, the RA/AAT reliability modelsI can

be summarized in general form by

I = PiQ * [(CIA * Pi.TA + ClP * PiT) * PiA + C2 * PiE) * PiL (3)

where:

L is the MIMIC failure rate in failures per million hours,

PiQ is the quality factor,PiTA is the temperature acceleration factor for active devices,

PiTP is the temperature acceleration factor for passive devices,

PiA is tho MIMTC application factor,

PiE is the application environment factor

PiL is the learning factor,

CIA is the circuit complexity failure rate for active devices, in

failures per million hours,

CiP is the circuit complexity failure rate for passive devices, in

C2 is the package complexity failure rate in failures per million

hours.

A review of the literatureI01-122 concerned with MIMIC failure, during

the time since the RA/AAT failure rate models were generated, resulted in

no change to this basic model.

The stress parameters and attributes that directly affect the calculated

failure rate for a MIMIC devict: are embedded in the Pj and complexity

failure rate factors of the reliability model. To extract the maximum

stresses allowed for each criticality level from the factors in the

reliability model, L in equation (3) must be set to the maximum failure

rate allowed by each criticality level. Since MIMIC devices were not

included in either the current version of the Guidelines or any version of

89

MIL-IliIBK-217, txiese maximum failure rate-s are not specified in table 3-3.

Therefore, an alternate approach was used to bound the failure rate tor

each criticality level. It was noted that the maximum failure ratescalculated for silicon microcircuits closely approximated the failure rates

that would Ze calculated given probabilities of success oZ 0.9990, 0.9900

and 0.9000 at 10,000 hours for criticality levels I, II and III,

respectively. The actual failure rates associated with these threeprobabilities of success are 0.1001, 1.0050 and 10.5361, respectively.

These three failure rates were Lised in the apprcach for developing stress

derating criter-ia in a fashion similar to the approach used for advanced

technology silicon microcircuits. The parameters and attributes of the

failure rate model z ctors were separated into three groups, one group for

criticality-specific (CS) attributes, one grotl.p for device-specific (DS)

attributes and the other group for stress-specific (SS) parameters. Table

5-1 outlines the relationship between the factors in the failure rate

equation and the distinction between criticality-specific, device specific

ana stresis-specific parameters and attributes associatecd with tne tactIs,

There were two types of device-specific attributes, technology and

complexity. The technology attribute of the C2 factor was handled by

noting that the pin count for most MIMICs does not exceed 10 pins. The

packaging technology selected was the one that gave the highest failure

rate for a 10 pin package according to th. RA/AAT final report. Having

boLud tU= package t . ,com ti_ •h cuit complexity attribute was handled

by noting that the relative difference in values of the CIP factors Zor

MIMIC devices with 11 to 100 passive elements and MIMIC devices with

greater than 100 passive elements was less than 30 percent, and that many

MIMIC devices had more than. 10 passive eLements. Therefore, the CIP factor

for Ai4MICs with greater than 100 passive elements was used to represent the

CIP factor for MIVICs with 11 to 100 passive elements. Four sets ofderating criteria were developed t. handle the tvio CIA and two (iP circuit

complexity categories of MIMIC devices.

90

Table 5-1 Attributes and Parameters of MIMIC Model Factors

Factor Type Attribute / Parameter

PiQ CS Application Environment

PiTA SS Channel Tmzen ature

PiTP SS Ciannel Temperature

PiA N/A Applicaticn

PiE C Application Environment

PiL CS Years In Prcdadtion

CIA IS Circuit COmplexity, Active Devices

CiP DS Circuit Omplexity, Passive Devices

C2 MS Pacuage Tenology

The criticality-specific attributes included application environment and

years-in-production. The application environments for the PiQ factor were

S-Level, B-Level and B-Level for criticality levels I, II and III,

respectively. The application environments for the PiE factor were SF "

Au and GF for criticality levels I, . and III: respectively. These

application environments were chosen since thc y were the most closely

related to the application environments outlined in the current version of

the Guidelines. The years-in-production attribute for the experience

factor, PiL4 were 2 years, 1 year and 0.75 years for criticality levels I,

II and ]II, respectively. These years in production were chosen based upon

current experience with component procurement. for systems that can be

categorized by the definitions given for each criticality level.

9"

The stresss-srp2f c parameters, as mentioned previously, a~e the only ones

that, when changed, result in a different failure rate for any given

MIMIC. The channel temperature parameter was the only parameter that could

be varied to obtain the maximum failure rate for the MIMIC. With the

device-specific, criticality-specific and stress-spescific attributes and

parameters defined, the maximum cbannel temperature derating criteria was

developed.

The criteria in the MIMIC stress derating table was the result of applying

the device-specific attributes and st'uss-specific parameters to the

failure rate equation. These attrijhtes and parameters included

temperature activation enezgy (PiTA and PiTP), circuit complexity (CIA and

CeF) and number of package pins (C2). Table 5-2 outlir.es the values used

in evaluating these device/stress-spec.fiu attributes.

'Ihe dependemo of failure rate and proL,!cility of success at 10,000 hovrs

of o;pcrticn are shown in figures 5-1 5 •-2, respectively. by applying

the approach outlined in sections '1.0 and 4.0, the maximum channel

tenperature is calculated by setting Uc KIMIC failure rate of equation (3)

to the failure rates of the three criticality levels. The channel

temperature derating criteria for .. IC devices is found in table 5-3.

Table 5-2 MIMIC De-vicertresii-Specific Attributes

Technology Attribute Value / Equation

GaAs Ea (Active) 1.50 eVEa (Passive) 0.43 eVClA 7.22UIP 2.94pins 10C2 2.8E-4 * P2IS ** 1.08

92

Figure 5-1 MIMIC Failure Rate

LO

*0

o 4)_

Oco-$I-

SCL_L_0

El4 c

'Uo

4))0.

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4 0 0

93

Figure 5-2 MIMIC Protmability of 2uccess at 10,000 Hours

00

tom

oI

co

Ya.c

O)) !Z

,i 1 --a--

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C,))

4" co

00

oc 6oý 6 '1 6 p0 C 0C

94

Table 5-3 MIMIC Stress Deratirig Criteria

"000 u uj

4,

0

~ VUAV A A

a.~L uJa.m

C. a.

'~ 95

It is noted here that the calculated derated channel temperature stress for

level IiY mission criticality (approximately 160 to 165 deg C) was above

the region of validity of the RA/AAT reliability model. Therefore, the

maximum channel temperature for level III criticality was set to the

maximum valid channel temperature of 150 deg C.

Since existing stress derating guidelines have purposely affected the

observed failure rates of components used in applications corresponding to

one of the three criticality levels, it was necessary to review the

existing stress derating guidelines to determine their relevance in being

inlluded in the updated stress derating guidelines, given that the factors

being derated were not explicitly included in the current failure ratemodels. It was determined that none of the identified fourteen guideline

sources pr ovided MIMIC stress derating criteria. Therefore, the updated

stress derating criteria for MIMICs is limited to only the newly created

criteria based upon the updated RA/AAT reliability models.

MIMIC APPLICATION NOTES

The following application notes for MIMIC devices were developed from a

review of applicable literature, supplier surveys and other stress derating

guidelines. These application notes may also be found in Appendix A.

1. The enviromrent of the internal package cavity of the MIMIC must bekept inert.

2. Precautions must be observed during electrical test to preventpotential latent failure due to overstress.

96

6.0 POWER TRANSISTOR DEMAT GUIDELINES

Power transistors are designed for power anplification and harndling high

voltages and large currents. The main concern with power transistors is

the high absolute values of power and the limitation of operation iuposed

by second breakxown.

Stress derating guidelines were generated for three classes of power

transistors, silicon bipolar, GaAs -nd MOSFET. For silicon bipolar power

transistors, an approach similar to the microcircuit atproach %was used to

develop the stress derating criteria. For GaAs powr MESFETs, adequate

data was accumulated which allowed the generation of a temperature

dependent failure rate mciel. For power MlSFETs, it was determnied that

the currently accepted derating policies were adequate in providing the

margins of safety and sucoess needed in the intended applications. Reviews

of the literature123- 1 5 9 , supplier surveys and available stress derating

guidelines from governmnt and iniustnr sou•ces were used to evaluate and

urpate the stress derating criteria for these types of power transistors.

The application notes for power transistors were also developed froa a

review of applicable literature, supplier surveys and other stress derating

guide-lines. These application notes may be found at the end of this power

transistor section and in Appendix A.

6.1 SIL103• O kLFIAR POWEIER MANISIORS

The junction teap..xture, Tj, in a silicon bipolar power transistor

increases a., thc the x increases. The maximum value of T! is limited

by the tekv-ature a" which the base region of the transistor becX1Is

intrinsic, that is, the collector is effectively shorted to the emitter and

transistor actio.i o ases. 'The tenperature and power handling ability of a

trdnsistor can be inproved by providing adequate heat sink for efficient

thermal dissipation, providing a large enough emitter stripe width to

97

reduce orent density and preferring low voltage, high curre-nt application

to high voltage, low currtnt applicatiom,. Tfe latter oondition results in

higher tenrature rises at the stripe centers. Consequently, both power

and junction teq arature stresses need to be derated.

The use of power transistors is often limited by a phencumvo called second

breakdown, wViich is marked by an abnupt decrease in dek•vice voltage with a

siavltareous intenval ccsstriction of current. For high pFer devices,

operation zust be confined to a safe operating area (SOA) so that permaz nt

damage caused by the second br•-kdocn can be avoided, Figure 6-1 shows a

typical SCA for a silicon power transistor oqei-ated in the cxmon-euAitter

configuration. At the upper left (A), collector load lines are limited by

current-carrying ability. The DC thermal limit (B) is determined from the

thermal restanoe RtI of the. device,

Rth = (Tj - To) / P (4)

where P is the power dissipated. Therefore, the thermal limit defines the

maxinum allowed junction tenperature, where

Rth(peak) = (Tj (max) - TO) / (IC x VCE) limit (5)

If Tj (max) and Pth~peak) are assumed constant, then

(IC X VCE) limit = (Tj (max) - TO) / Rth(peak) = comntant. (6)

Thus a straight. line relationship with slope=l exists h ..n Ln(Ic) and

In (VCE). At higher voltages and lower currents, the temperature rise at

the stripe center is responsible for tLe secoml breakdown, and the slope

(C) is generally between -1.5 and -2. The device is eventually limited by

the first breakdoW voltage, or avalanche, in the SOA as indicated by thle

verticai line (D). For vmperatures higher than To, the SOA is reduced.

All portions of the SQA should be derated to provide margins of safety as

needed for application.

98

Figure 6-1 Typical Power Transistor SOA

aO

aQ-0

0~ C)

0

OL

0/ - -

C)) o

"o 0

CC;

o' I . / •_•°_,

- -

I-9

1 • -

!~ 0

C.,.r'-

99 '

For silicon bipolar power transistors, the MIfj-IU)B!<-217E Notice 1

reliability mod-11 6 9 has the form

L = Lb * PiA * PiR * PiS * PiQ * PiE * PiT (7)

uhere:

L is the transistor failure rate in failures per million hours,

Lb is the base failure rate,

PiA is the application factor,

PiR is the power rating factor,

PiS is the voltage stress factor,

PiQ is the quality factor

PiE is the application environment factor, and

PiT is the tperature acx-relration factor.

A 'reVi.e of the literatuvre oo_.exvrnd with silicon bipolar power transistor

failure, during the tine since 'Lr-HDBK-217E Notice 1 failure rate models

were gene-rated, resulted in no dcange to this basic model.

The stz3!ss parameters and attributes that directly affect the calculated

failure rate for a silicon bipolar power transistor are embedded in the P!

factors of the reliability model. To extract the maxiiuam stresses allowed

for each criticality level fron the factors in the reliability model, L in

equation (7) must be set to the maxi.mu failure rate alimmd by eachcriticality level. These maxinum failure rates arm specified in table

3-j. In the approach to develop stress derating criteria for silicon

bipolar power transistors, the parameters and attributes of the failure

rate L=Idel factors were separated into three groups, one gruup for

criticality-specific (CS) attrilbutes, one group for device-specific (DS)

attributes and the other group for stress-specific (SS) parameters. Table

6-1 outlines the relationship between the factors in the failure rate

equation and the distinction between criticality-specific, device-specific

and stress-specific parameters and attrbiutes associated with the factors.

100

Table 6-1 Attributes and Pa-_-ameters of Silicon Bipolar Powe:

TransLitor Model Factors

Factor Type Attribute / Parameter

Lb N/A Base Failure Rate (constant)

PiQ CS Application Envirornrnt

PiT SS Junctiorn Tet-erature

PiE CS Application Dnv:-xrm4nt

PiA N/A Application (cnintstant)

PiR SS Power Rating

Pis SS Voltage Stress

In tnis power transistor reliability model, tilere were no device-specitic

attributes. The only criticality-specific attribute was the application

environment attribute. The application environments for the PiQ factor

were JANTXV, JANTX and JAN for criticality levels I, II and III,

rec-ptive:.y. The application environments for the PiE factor were SF,

AUF and ir for criticality levels I, II and III, respectively. These

application environments ware chosen since they were the most closely

zelated to the application environments outlbied by the criticality levels

in the current version of the Guidelines and resulted in the highest

failure rate for the criticality level they represented.

The stress-specific parameters, as mentioned previously, are the only ones

that, when changed, result in a different Lailure rate for the given power

transistr. These parameters, junction temperature, breakdown voltage and

power rating, are the ones that can be traded-off to obtain a failure rate

similar ro the maximum failure rate that was calculated using MIL-HDBK-217D

Notice 1. As shown in table 6-2, the stress specific attributes include

temperature activation energy (PiT) and voltage acceleration (PiS).

101

/Table 6-2 Silicon Bipolar Power Trcansistor

Stress-Specific Attributes

Technololycx Attribite Value / Equation-

Silicon Bipolar Ea 0.18 eVPiS 0.045 * exp [3.1 * A/R]

The approach taken to develop the bounds for these stress-specific

parameters first assumed the power rating was the same as the power rating

used to develop the maximum failure rate (200 W). Then, the derating of

the remaining stress-specific parameters associated with the other

reliability model factors, namely breakdown voltage and junction

temperature, were equally weighted in calculating a similar failure rate.

The equal weighting o: the stress p-raiametjers rcz,1•.•d in derating both

voltage and temperaturi.e to 65%, 85% and 90% of their maximum ratings for

criticality levels I, II and III, respectively. Since the conservative

maximum rating for silicon bipolar power transistors is 150 deg C, the

junction temperature derating for criticality levels I, II and III are 95

deg C, 125 deg C and 135 deg C, respect.vely.

Supn eknnting the breakdown voltage and junction temperature derating

parameters were the stress derating parameters outlined by other deratingguideline sources shown in table 6-3. In keeping with the general approach

outlined in Section 3.0, and because of the uncertainty of criticality

assumed with guideline sources not specifying three -,riticality levels,

only those guideline sources supplying derating criteria for three

criticality levels were evaluated for inclusion in the updated guidelin~es.

The" - aining guideline sources were used only as a "sanity check" of that

updated stress derating criteria. Table 6-4 summarizes the new stress

derating criteria for bipolar silicon power transistors.

102

Table 6-3 Silicon Bipolar Power Transistor Guidelines

MAXIMUM SAFE S• ONOF

MPOWER SFWE BREAKDOWN ON-OFF

JUNCTION POWER OPERATIN43 OPERATING VOLTAGE TEMPERATUREJUTC GUIDELNE T TEMPCIR E OSSIPAT'ON AREA AREA (PORV) CYCLES

EM (POR V) (POw, Vc0 (POFr), IC

A&B 95 50 70 Vce 60 IC 60 NLC 95 50 70 Vce 60 Ic NL. NL

0 NL NL NL NL NL NL

E (55 PORV) 50 70 Vce 60 Ic 60 Fig. 6-4

F (55 PORV) 55 55 Vce 55 Ic 60 Fig. 6-4

A&B 105 60 70 Vco 60 Ic 70 NLC 105 60 70 Vce 60 Ic NL NL0 NL NL NL NL NL NLE (70 PORV) 65 80 Voe 70 Ic 70 Fig. 6-4

F (80 PORVs) 80 80Vc so k Fig. 6-4

,'S 125 70 70 Vce 60 IC 70 NL

C 125 70 70 Vce 60 kI NL NL

p NL NL NL NL NL NL

( ,0 l °,-,,-W Fig.

F (90 PORV) 90 90V08 90 IC 80 Fig. 64

NONE 6 80 60 75 Vce 751c NL NL

,PECIFIED 1 110 50 75 Vce 60 IC. 65 NL

J 110 50 75 Vce 70 IC NL NLK 125 FO 75 Vce 75 Ic NL NLL NL 50 70 Vce 70 Ic 70 NL

PA 125 NL 75 Vce 75 Ic NL NL

W NL 70 NL NL NL NL

X 125 NL 100 Vco 10010 NL NL

KEY: NL LNoUWPORV - Perwcen of Aade ViA*e

103

Table 6-4 Silicon Bipolar Power Transistor Stress Derating Criteria

44,

4'

41

4'1

'U

-JA

104

i i i I I I I I

6.2 G-As POW*ME TRANSISTIORS

Although both -TFTr and MOSFET styles of GaAs transistors exist, the most

common style of GaAs power trcusistor is the MESFEr. From reviews of the

available literature and supplier surveys, the primary failure mechanism for

MESFErs is the interdiffusion of the deposited xmeta-l (typically alumirum or

gold based) and the GaAs. Tyn•ically, the interdiffusion results in a

gradual degradation in performanoe due ti increased contact resistaKcl,

decreased drain current ard redched chatuxel depth.

The primary stress that accelerates this process is temperature. Table 6-5

summarizes in detail the geometry, materials, ratings and life test bias

conditions ac results obtained from various literature a-4 supplier sources

in which the effects of temperature are well documented. It is observed

that the primary failure mode has ctianged fran one that produces

catastrophic results, such as gate burn-out, to one that results in gra +-ul

energy was calculated, sucri that a lifetime prediction could be made based

on ckannel temperature. Tbese predictions are shown graphically in figure

6-2. It is noticed that, at high temperatures where the life test was

monitored, most of the re -Aences showed fairly consistent results. The

only exception was reference 154. The mean and standard deviation of the

extrapolated lifetimes from the other references enables an appruximation of

the probability of sixxess to be calculated for a given tenperature. Mae

0.5 (nean), 0.9000, 0.9900 and 0.9990 probabilities of s are shown

graphically in figure 6-3. By evaluating each curve at its intersection

with the 5 log-hour lifetime line (100,000 hours), and assuming the same

relationship between probability of success and criticality level that was

assumed for GaAs MalICs, the maximum junction temperature can be evalated

for each criticality level.. UN maxim•e m channel temperatures for GaAs power

?SFETf's are 85, 100 and 125 degrees Celsius for criticality levels I, II and

III, respectively.

105

Table 6-5 GaAs Power MESFET Lifetest Data

A A1 A4 Ar Aj AiC, ý cL ; Z AC j(j"!: A. A-- :2 : ! A A, A1 A A,ý 5 2 C

a A3 A 0 0 C AA

cmA n( nc )c n'nmm m m i C 443" ,""c A A0 CA Z ZnAZ(

cu A'NZC% CA In~AZ~ V3 U) U) n'eJ4 3 J\3J3 S(

E Zs (/34/DAW3 Z) (3 (A C/3W A :/3 4- 0 m0 0 t0/13 ~ ( / / ~~l/M1 A) A AD A) CnA~. M CM A M - - - - - - - - 4 24 , W

OU W U4)I A) A U AK -A/C - - CA( A ( AC AK

0. S A AAm

AK AC AK AC AK AC AK -

AC A w A- -C AC -CA

A1 AA A A A A 4. .41- ~ ~ J~ A- C.AA 2A .Q A -L

AA-J-J---.-J-J4 A A A A A A A A A A A A A A A A A A A *-1 7A-j (

.C 43 ~ A W A 0 O A 0., - AO AO -Z Ao ca AA A10 AA A A AA A A A AAA0AA A A A A0 A0 10A A41 11,;C ;'I I"Ir n 1 1" nI no

03030303 ~ ~ ~ ~ ~ ~ ~ ~ a C; Aý 0300 33A 00 PAnA~ A 4 34 3 34 34

A MF - - A-

Ac 'A m~ A 44q*343J3 4334433 434 A - on "NO Anu na n U t oc ý C 01

A6 Ac C; A;8C c ;C ;C c ;C. c c ;Ao ao c Ao Q

C2 AAA

A ~~ ~ A A

If A 1 Ar A A AAIn A % Ait A LeA

A1 A Aj Aj -j co ADc mc j- 1 - j-

A. A A A) A) 0. A c' A 'Aijý j - j ý 4 Aj j4 0 A f.) . A u A)u - j j - 1-

A Ax x x A x A A ;

,:7 AA A AA A J AL A J 2

0. 0 43 - 1C 4 14C 1 JC I At A r- I- AtA* i M rn Ie fnLA L LL .. . . L L t *A

or - -/3 - -L(C4 A -UA.A A I-C .)AU.~L2 J

I A A AA A1A6

Table 6-! GaAs Power MESFET Lifetest Data (continued)

cme

C3 a C4 It C1 a43C ýI 4- OG O C oo C, C0 - ; ; 0 I

0, 0000.000

*m 4 ,0- n D o0C3C . . -. .1 4. j -. .4-aCD. ý a 3C 4= ~ zC40 ' UN ,. K%,'

0CC~~~I (VIN'. r4__ __

O• '.0 W 0,C303.CD 000 C040000000 0 • •.*fm Cm 4q C4f

C Cm

n404 ^C OInr 24 3C ~ 4 0 C3 C: 3 4 > D0C; 40 C3 4OC ) C N 0 3 UC

4.0 1- r.- ..- r4 '0 U . n zPnIn P n r.r W%-_ f. C3 4-t. ' CO n .ý 0 . Cm

4 4 f,' 4 ,4 .' ',0. ',0'O

1- Q 4m v C4 4m f4 IN

0 r.

In •0 °0 V, • 0

'. -*.......................I - d-l- - •.•I N,.....4. . ..d...J.• d .-• , .•.,Zr....................ZZZe~t

4 -. 4f 4l V4 41 W! *4 l ýII . ..

n ! 4 i4, 0 " 0 .0 DV* 4a ID 40 40

""-J -J" -J.Jý %tU%&' ýt • -J ' -1- . t.J - - J J. .J.J J --J. J~ • • -J -•.1 OCO4

.407

*L - J- J A - II f- f- r ZZ *l -Z -1 -1Z . *. ZZ-j-j 4jt It r-j -4C; 4 r z 2 4 2

IM 4 M 1 0 v . 4

4 , a 0.00

4I Ch p Q I" In M

-' *)- P' 4 -I- CO 'l It I -'

4 2V4 :: '2.2: !2 !: r tý0.r-~..i. it..q. JJ .J.J4 Ji~.44 AI I*4 4..4.4. 44%4

~- ZZ ZZ ZZ 4 4. Z~ 4Z ZZ 4Z Zr ZZ Z0 (l~l~r107 4 4

Table 6--5 GaAs Power MESFET Lifetest Data (continued)

l 0. m 9 C' 0 C) C3-* 4 4 4 4

(a 4 44 4 9CA m -a 4 4 en C3C4C , CýC

fn On f C4 NM-4 4J enMM4 QC)MM( O

CO O 0u2'0 * FN 0 *-0 Nf. a 0 ('J x 'O'. 0OCJ2C*.i'iO ,J

4A IT~44 IT 991 EVE.@P)4 44.4~* J4~. .~~t)4~~44) . . . . . . . ..k*

W 2 em; C4 4- =, 4LQ 4~u =4 4t L% ; u"A -n Vt f: P P : 4 C:)=JV ý - J n

! 4 4 , C, ý Q 4 W 9, L

L 2c z. Ln 4 4 L rkr 4. 0 A.n

On Fa 4 . C, 4, 4! 4 - 1p

a 4 9 4 9 c

C C)C3 C C C C 0.0 D0 00 00 C- QoaOO C5CJOO3U1 C,0

0 N 0 -4 4 ýC'

c - Vt- W10 n 0 0 W-3004000 N 6m CQOO..N'~O4. lAO at 00

40 0 4n' M9 4- 414 *

41 L % 14 n 0 gn0 4 .

C- - -L >> b

on In 44

43 4 44 4 44108.

Figure 6-2 Lifetest Results for GaAs Power MESFUTs

I ~cm

cmJ

/ 0O

0

0) ILO

~~4)

0 I Alf

CIDI

/ I-O

0~

to 0 t

cm'

0 10 109 U

IFigure 6--3 GaAs Power MESFET Lifetime Prediction

' •04

04 0

to

N C5

040

F-- <)

LL - .0 )0)

00

to 0 oCW Lf 0)

CC

(.O cE

2MC~N,0 C4

110-

Supl7ementing the channel teraerature derating parameter was the stressderating paLameters ou•-lined by other derating guideline sore as 'own.n table 6-6. In keeping with the general approach outlined in Section

3.0, and because of the uncertainty of criticality assumed with guideline

sources not specifying three criticality levels, only those guideline

sources supplying derating criteria for three criticality levels were

evaluated for inclusion in the updated guidelines. For each parameter

specified by these guideline sources, a median value for the parameter was

chosen. In the case where the dcoice was between an even number of values,

the average of the two median values was calculated and then imurded up.

The remaining guideline sources were used only as a "sanity check" of the

updated stress derating criteria. From a thorough rev.iew of the

literature,- it was determined that currently accepted derating policies are

adequate in supplementing the channel temperature derating parameter inprovidiing the margins of safety and success needed for the application.

Table 6-7 summarizes the new stress derating criteria for GaAs power

transistors.

111

Table 6-6 GaAs Power Transistor Guidelines

MAY]MUM

CHANNEL POWER BREAKOWN ONOFFCRITCALTY GUIDELINE TDISSIPATION VOLTAGE TEMPERATURELEVEL (deMPERATC) POR ORV) CYCLES

(dog C)

A&B 95 50 60 NL

c 95 50 60 NL

D 95 50 60 NLE (55 PORV) 50 60 FNg. 6-4F (55 PORV) 55 60 Fig. 6-4

A&_, 105 60 70 tA&B 105 60 70 NL

C 105 60 70 NLD 105 60 70 NL

E (70 PORV) 65 70 Fig. 6-4F (80 PORV) 80 70 Fig. 6-4

A&B 125 70 70 NL

C 125 70 70 NLD 125 70 70 NL

E (80 PORV) 80 80 Fig. 6-4F (90 PORV) 90 80 Fig. 6-4

NONE G NL NL NL NL

H NL NL NL NLSPECIFIE-D NL NL NL NL

K NL NL NL NL

L NL NL NL NLM NL NL NL NL

W 82 PORV 70 70 NL

X__ K 125iI NL J N. NL

KEY: NL - Not Listed

PORV Percent of Rated Vauue

112

Table 6-7 GaAs Power Transistor Stress Derating criteria

U.' CO (3

4)

C4 Chn

4,1-J.

U

11

6.3 POWER NWxFErs

MSOFETs cannot be derated in the same way as bipolar junction transistors

because the devices are constructed and operate differently. MSrS•71s have

considerably higher input impedanae than hipolar transistors, whidi makes

them suitable for microwave systems. MISFETs also have a negative

temperature coefficient at high current levels, resulting in the current

decreasing with increasing temperature. This characteristic provides for

temperature stability and prevezts the FET from thermal runaway or second

breakdown. Consequently, MISFETs have found increased acoeptanoe as power

devices.

FFrnm a thorcugh review of the literature, it was determined that currently

accepted derating policies are adequate in providing those margins of

safety and success needed for the application. The stress derating

criteria for power MOSFET transistors outlined by other derating guidelinesoures i' 5hui ln t Ir b-.epri ng. with the general approach

outlined in Section 3.0, and because of the uncertainty of criticality

assumed with guideline sources not specifying three criticality levels,

only those guideline sources supplying derating c-riteria for three

criticality levels were evaluated for inclusion in the updated guidelines.

For each parameter specified by these guideline sources, a median value for

the parmter was chosen. In the case where the choice was between an even

number of values, the average of the two median values was calculated and

then rounded up. The remaining guideline sorcs were used only as a

"sanity dceck" of the updated stress derating criteria. Table 6-9

summarizes the nev stress derating criteria for power MOSFET transistors.

114

Table 6-8 Power MOSFET Transistor Guide!ines

N"Mum PO 1 SAFE SAFE BREAKDOON ON-ut F

MUNCTION PATI OPERATING OPERATING VOLTAGC TIMPERATURELEVEL.UY UII=N TEMPERATURE (FJV RAAE PO"t CYCLES

EVI. (dog C) PRV PORV), Iv (PORVV. L

A&B 95 50 NL NL 60 NL

D95 50 NI. NL 60 NL

NL NL NL NL NL NLE (55 PORV) 50 NL NL 60 Fig. e-4F (55 PC'R) 55 55 Vc 55 Ic 60 Fig.6-4

A&B 105 60 NIL NL 70 NLC 105 60 NL NL 70 NLD NL NL NL NL NL NLE (70 PORV) 66 NL NL 70 Fig. 6-4F (80 PORV) t) 80 Vce 80 Ic 70 Fig. 6-4

A&3 125 7 NIL NL 70 NLC 125 7 6 NL NL 70 NLD NL NL NL NL NL NL

Nt (80 PON so NL NL Be Fig. 6-4

_(90 _ I_ _ _ _ &0 __ vG_ __ 80 Fig. 6-4

NAJE G 60 60 75 Vce 751c NL NL

MP.CIFiED 1 -I 110 50 75 Vca &) Ic 65 NLJ 110 50 ",5 Vcc 70Ic NL NLK 125 50 (75 Vda) (75 Id) NL NiL

L NL 50 70 Vce 701c 70 NLM 125 NL PtL NL 75 NL

W NL NL. NL NL 70 NL

X 125 NL 100 Vcu 100 Ic NL NL

KEY NHI - LWdPORV P p•c og PF, V*.I

115

Table 6-9 Power MOSIFET Transisqtor Stress Deratingc Criteria

-IZ

o3. itiý

4,

44

-u

L. IU

6.4 POWER T 3ANSISTOR APPLICATION NTPES

The following application notes for power transistors were developed from a

review of applicable literature, supplier surveys and other stress derating

guidelines. Miese application notes may also be found in Apperdix A.

1. Power transistors my be sensitive to ESD.2. Design margins should be used for gain (+/- 10% for screened devices;

+/- 20% for unscreened devices), leakage cnrent (+100%), switchingtimes (+ 20%) and saturation voltage (+/- 15%).

3. Heat sinks may be required to maintain derated junction/channeltaqeratures.

4. SOA curves, adjusted for junctiorVndh l temperature, should not beexceeded under any transient conditions.

5. The number of on-off cycles (temperature cycles) shodld be limitedaccording t!he derated power as shown in figure 6-4.

117

Figure 6-4 On-off Cycling Limit:., for Power/Pulse Transistors

00_______ _________0

w~2ZZZL~0

C:

+-W

(0

0,

V/)

4-0-

0

(UU

0,0

ceJ

0

0~ ) CU~ I*- (D LO Kt (9 N~ 0

7.0 RF TRANSISTOR DERAPING GUIDELINES

RF pulse transistors and RF miultitransistor packages have typically

operated in the low microwave frequency rzge and have been largely silicon

NPN transis-tors. However, because of the advanoes in performan:ýe and

reliability of GaAs transistors, many of the siliconn RF pulse trinsistors

are being replaced by GaAs MESFETs.

Scme of the critical parameters and coxnstnrction details for RF PUke and

microwave transistors include current gain, switi time, doping level i

the base, maximum open circuit voltage (breakdown voltage) , off iixrance,

on ixpedance, emitter stripe width, base thickness package and wafer

parasitics and active area ge-imtry, includirq interdigitated, overlay and

mesh types.

Significant failure mechanisms of RF pulse transistors includes

le ." %AL"LLCL-LUII, %LJ. I..L I A .A L--t=gILt "L" -L A..L.." - LJA.I - -.La-A 0 LAfl I LriV t S.L

junction leakage and secondary breakdown. Narrow base widths can result in

collector emitter shorts due to temperature acceleratel diffusion spikes

and pipes if bulk silicon defects such as dislocations and stacking faults

are present. 'Thermal resistance problenr can occur on RF transistors and

attention to die size, die attach method, package type and application,

heat sinks and air flow are important factors relating to the derating

criteria. It is noted that the. newer device styles are 4ore powerful, more

sensitive and cover greater bandwidths, although the basic technologies are

the same. Therefore, the updated stress derating criteria for RP pulse

transistors and FF voultitxansistor packages has not changed frum the

current stress derating criteria, with the exception that perhaps greater

attention to detail is required. This attention to detail is highlighted

in the following two examples.

119

In this example, a thermal runaway failurp- was cbserved in a microwave

Miltitransistor (NpN) package (see figure 7-1). .In this pacKage, two

4--transistor arrays were mounted next to each other. £lring the f.iIure

anilysis, it was detenrined that in the assembly operation, the sexradarray was not mounted properly. The array was sitting on top of the edge-

of the first array (see figure 7-2). The greatly irrzased thermal

resistance at that end of the array resulted in thermal overstress and

evet.ial !tastr1phic failure of the multitxansistor package.

-Y.-icr thzn this analysis, no additional information was accunulated on RF

nailtitransistor packages that indicated a differeme between the behavior

of pp mIultitransistor packages and RF single transistor packages.Therefol-e, it is concluded t-at the stress derating for these packages

should be no different than for PF single transistor packages. It is

reccuerled that the stress der-AtinY criteria and associated application

notes for RF transistors outlined by the current version of the Guidelines

s4hould be followed for BF irultitransistor packages.

In a seconr example, failure analysis performed on 118 RF pilse transistor

fieb,1 failures of SPS-40 transmitters identified 76 of the fuilures to be

related to MOS capacitor overvoltage, high RF voltages due to reflection,transis-.tor mismatch and thermal ireases due to reduced die attach. A

detailer thetrmal analysis idlentified war~t case junation temperatures of 87

de1.Z,••" ... l. . ihu,_ tIhh _ ruired (etrating. The RF transistors were

rated c-,t 50 volts and were not expected to see more than the transistor

emitt',--i,,ýe breakdown voltage of 6 volts. However, it was possible to

develcT) rr' vvotages across the M4S capacitors considerably higher than the

erittd-4x., k-reakdown voltage whei looking at 35 watts of palsed 450 MHz

pCwX. T • unitter-base junction breaks down without damage, but the

• it[•r• '. ?lectric breaks down as an irrevewrsible short. Good

er1i.,'w! practioes need to supplenent any deratirj policy in order to

obtAin ar. acu•erabie level of safety and success.

1.20

FigLure 7-1 Catastrophic Damage in an RF Multitransistor Package

Figure 7-2 Assembly Problem Resulting in Thermal Runaway

L 2 1

Although studies are being performed 16 0 - 1 6 3 to better understand the

effects of peak pulse yxxer per unit gate width, the number of pulses in a

pulse train and the duty cycle of the pulse train on the failure rate of RF

pulse transistors, the data from these studies does rot provide encNgh

insight into modifYing current stress derating guidelines for RF pulse

transistors.

The stress derating criteria for RF pulse transistors was developed

similarly to the stress derating criteria for power t-ansistors. The

chiannel teeratura stress derating developed for GaAs power MESFETs is

also considered applicable for the GaAs RF pulse transistors. The stress

der-ating criteria for RF pulse transistors outlined by other derating

guideline sources is shown in tables 7-1 and 7-2 for silicon bipolar RF

pulse transistors and GaAs pulse MESFT, respectively. In keeping with

the general approach outlined in Section 3.0, and because of the

uncertainty of criticality assumed with guideline sources rnot specifyingLLeA criticality levels, only- those - 1ide e i delr squrip yinga derating

criteria for- thre criticality levels were evaluated for inclusion in the

updated guidelines. For each parameter specified by these guideline

sources, a redian value for the parameter was chosen. In the case where

the choice was between an evem number of values, the average of the two

icdian values was calculated and then rounded up. Mhe remaining guideline

s;ources were used only as a "'sanity check" of the updated stress derating

criteria. Table 7-3 summarizes the new stress derating criteria for RF

pulse transistors.

122

Table 7-1 Silicon Bipolar RF Pulse Transistor Guidelines

MAMUM PSAFE SAFE 1 ON-OFFiC• O~RA'TINO OPERAT1NG BR •

CRITICALITY JCMN DISS1PAT•ON pRAA.sT:T.A VOLTAGE TEMPERATURE(dog C)TMPJ1UFE (PORV) (PORV), Vc0 (PORV,:. I (POFN) CYCLE.

A&B 65 50 7G Vce 601 f 60 NL

C 95 50 NL NL 60 NL0 NL NL NL NL NL NL

E NL NL 70 Vce 60c C 60 FIg. 6-4F (55 PORC 55 55 Vce 5510 60 Fig. 6-4

A&S 105 60 70 VCe 60 Ic 70 NLC( 105 60 NL NL, 70 NLD NL NL NL NL NL NLE (70 PORV) NL 70 'ce GO 10 NL Fig.$-4F (80 PoRV 80 80 Vce 80 1c 70 Fig. 6-4

A& S 125 70 70 V - 60 IC 70 NLC 125 70 NL NL 70 NLD NL NL NL NL NL NLE (80 POqV) NL 70 Vca 6010 NL rI!.&-4F X ,0 SV f•,k. 6.4

G NL NL NL I NL Nt. NLSH NL NL NL NL NL' i04L

SPECIFIED j 110 50 75 Vce 70 I NL NL

K NL NL NL NL NL NLL NL 50 70 Vce 701c 70 NL

M 125 NL 75 Vce 754- NL NLW NL 70 NL NL N1- NLX NL NL NL NL NL NL

KEY; NL"NotIsidPORV - Peomn o PAb. Vakj.

123

Table 7-2 GaAs RF Pulse Transistor Guidelines

t AAXIMUMCHANE POWYEn BREAKDOWN ON-OFFCRfTiCAUI"Y GUIDEUNE DISSIPATION VOLTAGE TEMPERATURE

LEVNS TEMPEPATURE (poO'PON CYCLES(dag C)

A&B 95 50 60 NLC 95 50 60 NLD 95 50 60 NLE (55 PORV) 50 60 Fig. 6-4F (55 PORV) 55 60 Fig. 6-4

A&B 105 60 70 NLc 105 Go 70 NL-D 105 60 70 NL

E (70 PORV) 65 70 Fig. 6-4F (80 PORV) 80 70 Fig. 6-4

A&B 70b I 70 NLC 125 70 70 NL

III D 125 7U 70 NLE (80 PORV) 80 80 Fig. 6-4F (90 PORV) 90 80 Fig, 6-4

G NL NL NL NLNONE H NL NL NL NLSPECIFIED i NL NL NL NL

K NL NL NL NL

L NL NL NL NL

M NL NL NL NL

W 82 PORV 70 NL

X NL NL NL NL

KEY: NL - Not st•d

PORV - Percent cif Rated Value

124

Table~ 7-3 RF Pulse Transistor Stress Derating Guidelines

> 00 f-f

0m U U V% 4 002

e Lj Mi. - -. en.0t'

4m 34&U C -c

43 w

.-- - -.-

L 1254

APPLICATION NOTES

The following application notes for RIF pulse transistors were developed

frcm a review of applicable literature, supplier surveys arld Other stress ---derating guidelines. These application notes may also be foUnd in A •Per

A.

1. PW transistors may be sensitive to ESD.2. Design margins should •_ used for gain (+/- 10% for screened devices;

+/- 20% for unscreened devices), leakage Ocrrent (100%), switchingtimes (+ 20%) and saturation voltage (+/- 15%).

3. Heat sinks may be required to maintain derated juctiorylchannelten,)eratures-

4. TMe design may require exceeding voltage and power deratixq limits,but junctionVchannel tu~erature limts should be observed at alltimes.

5. The nmber of on-off cycles (tenperature cycles) should be limitedaccording the derated power as shown in figure 6-4.

126

8.0 OPIO-ELE~rIZONIC DEVICE DERATING GUIDELN

The approach to the development of the stress derating criteria for

cpto-electronic components was initiated in a fashion similar to theapproach used for silicon bipolar poxer transistors. However, it was

realized that the differences between the reliability models of

NIL-HDBK-217D Notice 1 and Mrh-HDBK-217E Notice 1 resulted in up to several

orders of magnitude difference in (improved) predicted failure rates. The

quality factor had charnged 2400% to 7000%, ard the PiT factor ofMIL-HDK-.-217E Notice 1 utilizes an activation energy of approximately one

third of the activation energy used in MIL-HDBK-217D Notice 1. The use of

the silicon bipolar power transistor approach to stress derating would have

resulted in virtually no stress derating rxquired to meet the failure rates

that were considered acceptable at the time the current version of the

Guidelines was released. As an alternative approach, the devellcpmnt of

updated "acceptable" failure rates for the three criticality levels was

considered. The failure rates that can be obtaired by applying currentlyaccepted deratirq guidelines to the reliability nmdels were deemed to be as

"acceptable" as any other values chosen. Therefore, without having to dothe failure rate calculations and the reverse stress analysis, the

currmntly accepted guidelines become the updated stress derating criteria

The stress derating criteria for cpto-electronic devices, including photo

and light emitting diodes, was developed by consensus of currnt strezs

derating guideline sources, as outlined in section 3.0. The Stressderating criteria for cpto-electronic devices cutluind by other derating

guideline sources is shown in table 8-1. In keeping with the gener-al

approach outlined in Section 3.0, and because of tne_ tuxrtainty ofcriticality assumed with guideline sources not specifying three criticality

levels, only those guideline sources suplying derating criteria for three

criticality levels were evaluated for inclusion in the updated guidelines.

Table 8-2 summarizes the new stress derating criteria for cptu-ele:tn-onic

devices.

127

Table 8-1 opto-.alectronic Device Gui~de~lnes

-1 0 -4 .4 s~u~- -. 14 -j. A 4 ý -f -. j-.1 -A in -juZni '0 '

Z2f4 4, M0~ 4 1" 2,:~I4 21 Z. ZZ ;L

fn 4o 4z 411 A C >- 3 jC j - jC j- j4&A4 LA M 0Mn f- Mn 3 t;

-4 - . 4 i -j a.- j- ) 4- j

M) 0~sZ M 10Z N 7Xzz =t M *

43)

I nL -4 -1 VIi 406 t ja.-AI01 w a C)

41 ccV~

LE > 4 -Ik -j 4i 9L -1 44- L - j- i j C i-

(n 44 4

g_ 4 = -.1

,- L. I- c

C. X~t >'O :g Q~N 4

0 a4 4) 0

>4 0 4

41 444 4 128

Table 8-2 Opto-electronic Device Stress Derating Guidelines

*4 40 4o c4 r

&A V% um t9 V4 4m a

Q5 C 40 w m m 4

L I.-4 a ~ 0 Il

44 4 4 1294 4 (.

OP-J.X)ITMIC DEVICE A~ a ,"J'1• N NUMm

Tte fcllowirn application notes for opto-electrordc deviies were developed

from a review of sufplier surveys and othez stress derating guidelines.

These application iotes may also be found in Appendix A.

Ruoto Diodes:

1. nIie gain of APDs should be derated by 3 dB to dcc=-nt for gradualefficiexcy degradation and shiftz in the operating point.

opto-cu.ýplers:

1. External bypassing may be necessaxy to prevent damging internaloscillation due to very high gain circuitry within the opto-coupler.

2. Allow for 15% degradation in ito-coupler current transfer ratio (CIR)over the service life of the design. This degradation is especiallyprevalent at low dri.ve cxrrent. The input drive current should bewell above the turn-cn point.

Light Emitting Diodes (LEIs)

3. OQrent limiting is requirr-d (usxii a series resistor).2. Half or full wave rectified AC sine wave is rot reor-mended for LED

drive current. If rectified AC is used to drive LEDs, the peak valueof the cir-ent must- never exceed the allowable DC current maximum.

Injection Laser Diodes (1l1D.)

1. Power supplies for ILDs must be carefully designed to ccupletelye! --drete ctu _revnt prulses whaich may cause catastropic facet damage.

2. Output power should be given a 3 dB margin to acoourrt fu• yfadi-aldegradation of the device.

3. 1Reaitica1 stress, such as thernal or mecianical shock and vibration,caxue crystal lattice defects (dark lines) to grow. Stress screeningcan be used to eliminate devices with the-se defects.

4. Excess optical power of IrLs will damage facets and will destroy thedevice. Note that optical power output. is strongly teqperaturedeendent and must be monitored and controlled to assure safeoperation.

5. For SiO2 glassivated devices, the integrity of the package hermeticseal must be maintained to prevent iwLture absorption which willdegrade performance.

130

9.0 PASSIVE OJ4PDNEUr DERArING GUIDELI=NS

The passive camponents of interest to this stady were hybrid deposited film

resisthrs, chip resistors (JRM) and chip capacitors, both ceramic (CDR) and

tantalum (GWR). Stress derating guidelines were developed for ttme chip

resistors aid chip capacitors only- Because no stress-failure info, mation

on hybrid deposited fiLm resistors was identified by the literature L: e rch,

supplier -LWveys, other stress derating guideline souces or accumulated

field failure data, no stress derating guidelines for hybrid deposited film

resistors onuld be developed.

The str3ss derating criteria for the chip resistor and chip capacitor was

developed fram a review of carrent stress derating guideline sources, as

outlined in section 3.0. This approach was taken after firdixq virtually

no information In the literature seardx1 6 6 - 1 6 7 concerning stress-failure

relationsmhifE of these passive camponents, and cu firmation by suppliers

that these rw~oi-ents (virtually) do not fail. Te stress derating

zritaria for these passive devices outlined by other deraticg guideline

scnrcai is sJAown in table 9-1. It is noted that none of the five guideline

scoues that typically specify three criticality levels outlined stress

derating criteria for chip capacitors. Tnerefore, the updated stress

deratirj for chip capacitors is based upon best engineering jlxiewent

biased Iy the guideline soirees prawidirg only one criticality level

c-riter ia - he stesdemratir criteria fnr ch in res-isqtn rs Ar &!vcd rrn9A in

a fastion sinilac to that for opto-electronic devices. Table 9-2

sunmarizes the now stress derating criteria for chip resistozs and chipcapacitors.

131

Table 9-1 Passive Device GUidelines

U.E

C4 CU 4m

4~J2c 1c4 4

z Z* Z ;z .XO ~ 4~ Z Z

0 4 4 4

a -A - J4.4j j 4 j A4 ) j .

44)

40 i

* t44O

*2 (nI4

1.32I

Table 9-2 Passive Device stress Derating Criteria

40 Ln Co10, Cfo

41 41

co &41 0 4

41 41

41 4

4-0

W ~ 03L L)

1331

PASSIVE DEVICE APPLICATION NCTES

The following application notes for passive devices were developed from,;

review of supplier surveys and other stress derating guidelines. These

application notes may also be found in Appendix A.

Chip Resistors:

1. COiip resistors are sensitive to ESD.2. 11e design should tolerate a 2% shift in resistance value.3. Proper trimming 3is required to prevant latent failure in low noise

applicatiofs.4. Resistor stacking should be avoided.5. For pilse applications, the average power calculated from pulse

matnritwe, duration and repetition frequency is used to establish thepc'ter desratirq requirement.

6. Pul s matgnitude should be used to establish voltage deratingrexp~d resbant.

7. Film tentrxxtures must stay below 150 degrees Celsius.8. Voltacge stress should stay less than 2 volts/ nil.9. PadMar dc._nsity should stay lests than 200 W per square inc4,.10 Trhe effective resistance value will be reduced when used at,

frequerKies over 200 MHz because of shunt. capacitance between theresistive elenents and the connecting circuits.

Chip Cqpacitor:

1. The sin of the peak AC voltage plus any DC bias voltage must notex•c•ed the maximnm deated c4-rating voltage.

2. Prec•uticos cut-li1d in MIIr-STD-198E should be followed.3. (Ceramic) A design toierarm of +/- 12% should be allc~md.4. (Tantal•u) A design toiel oe UJ. -/ 88% shcid be alla•'•

114

10. 0 SAW DERNII GUIDELINES

The stress detating criteria for SAW devices was developed frcm a review of

current stress derating guideline sources, as outlined in section 3.0.

This approach was taken after finding virtually no information in the

literature search1 69 concerning stress-failure relationships of these SAW

devices. The stress derating criteria for these SAW devices outlined by

other derating guideline sources is shcun in table 10-1. It is noted that

the four of the five guideline scurces that outline stress derating

criteria for SAW devices are split between two sets of inpxt power

derating. Therefore, the updated stress derating for SAW devices is based

upon the most recent update of these guidelines. Table 10-2 summarizes the

nsw stress derating criteria for SAW devices.

SAW DEVICE APPLICATION WYTES

The following application notes for SAW devices were develpped from a

review of sqPPlJr surveys and other stre.s demrating guidelines. rLhese

application notes may also be found in Appendix A.

1. SAW devices may be sensitive to ESD.2. Integrity of the. henretic package mst be maintained.3. The design should not subject the SAW device to the rated maximum of

shock, vibration and tenperature cycl.".

135

Table 10-1 SAW Device Guidelines

C.RXAfQ INPUT POWER INPUT POWER INPUT POWER INPUT POWER OPERATINGGr'AT GUJIDELINE (< 100 MHz) (>•100 MHz) (<500 MHz) (>500 Mhz) TEMPERATURE

LEVEL (dam FML) (dBm FML) (dBm FML) (:IBm FML) (deg C)

A&13 20 10 NL NL NLC NL NL 18 13 125D NI. NL 18 13 125E 20 10 NL NL NLF NL NL NL NL NL

A&B 20 10 NL NL NL iC NL NL 18 13 125

NL NL 18 13 125

E 20 10 NL NL NLF NL NL NL NL NL

A&B 20 10 NL NL NLCNL NL I18 1ý1 125 _

HI NL NL NL 13 125ON20 10 NL NL NLF NL NL NL NL NL

G NL NL NL NL NLH NL NL NL NL NLN4ONE J NL NL NL NL NL

SPECIFIED K NL NL NL NL NLL NL NL NL NL NLM NL NL NL NL NL

W 20 10 NL NL NL -X N4L NL NL NL NL_---

KEY: NL - Not UsLd

FAL From Maximum Uimnt

136

Table 10-2 SAW Device Stress Derating Criteria

EE

6

-j ÷++

4'

Z + +

1372: 1

* Qn )

4.4. 4.4.

u I

137g ~

!1. 0 DERATING VERIFICATION

To determine the validity of the stress derating criteria, field fai!Lre

data was gathered on the ccmponent types of interest to this study.

Because of the. difficulty in verif-ying space system tailures, and the

unavailability of consistent ground based system failure data, only

avionics w-btem failure data was collected and reduced to cobserved failure

rates. Maerefore, the verification of the effectiveness of the stress

derating criteria was limited to criticality level II criteria.

The avionics systems in question included the AN/APG-66 and AN/-M-68

radars and the AIQ-131 radar jammer. The field failure data was retrieved

for the years of 1988 and 1989, in which aver 1500 sorties were flown for

each system. In reducing the data it was understood that, although the

retest OK (RMIOK failures were not included in this failure summiaxy, not

all the remaining failures were verified. This lack of verification may

reult in csrvcd failure rates that are mufch higher than actual failure

rates. Thds scenario is typically true for the resistors and capacitors

which tend to be renved along with associated suspect failed ccmponents as

a lower risk option to leaving them in place and risk another rework cycler.

Table 11-1 outlines the coq~oent types and the observed failure rates

based upon the number of failures observed and the total number of device

hours of operation each component type had experienced. It is noted that

this cbserved failure rate is based upon part removals and rn. ne•xa-ily r

verified failures. Also included in table 11-1 is the predicted failure

rate for criticality level II caxzonents. These predicted failure rates

were generated in the same fashion as the failure rates outlined in table

3-3. Table 11-2 inclWles the factor values and rationale used to geer-atethe failure rates, based on MUr-HDBK-217D Notice 1 and utilizing the stress

deratin3 criteria of the cury ent version of the Guidelines. It is cbserved

that, for the most part, the observed failure rate was ccmparable to or

less than the predicted failure rate of the coxponent. Ihe exceptionsirnluded thick film chip resistors and ceramic chip cap•acitors.

138

Table 11-1 Stress Deratirig As~sessment for Level II Criticality

LO N 0 0 ON ON 0 C) r-N- VI N~ %0 CO 00 0

C-4 (NJ c-4 Sn ccý C; 0 0 0

' .ri t-' m 0 0 c

V

t o %D t r )ma

i i -I Il r(i

ONW 0 % -IAeD-40 --

'IT -( mj tI

1394

Table 11-2 Maximum Failure Rates. For Critica~ity Level 11

'4fl~ '- 0 0 0 1 CD.4 -

41 411(%- 0 c 0 0 0

L~~~~~j- 0. ' .' 4 N 0

-' .c c2Cz .

-- -K

CL M .c cp

.C q

co f - t , Q 1

&A ~ fn M , --K >

-C -K

N, ~ ~ ~ C j CN . .

0 .41 >c * a4I E;

00

1 03

0 f 0 $4 0~' a_ _ _ _ _

I) 9- .0 0~

tj* I

0 EL a 'CL N, 4) cu -ý z; C W G d

aX U dy cc U Ne-'-

0 ~ 0 0 140

Even if the unverified failure rates of the components are greater than

their actual failure rates, then it would be reasonable to asstume the

system design engineer has been fairly sucoessful utilizing the stress

derating criteria. However, with perhaps the exception of the RF

transistors which have a two order- of magnitude difference between observed

and expected failure rates, Iesign engineer may not be guard banding

the design more than that requ by the derating guiuelines. Therefore,

either the stress derating guidelines mast err on the conservative side or

the system design engineer must be more knowledgeable of wtiich stresses are

the most critical. In the derlopment of the updated stress derating

criteria, increased flexibility was provided in the stress derating

criteria such that the system design engineer may be more sensitive to the

way stresses affect the reliability of his design.

Based on the data of table 11-1, it is difficult to conclude that the

stress derating criteria had coupletely fulfilled its intent in keeping the

component failure rate below a specific level for the given mission

criticality. However, it is encouraging that, with the lack of

verification of the assumptions concerning the failures, the observed

failure rates are close to the expected failure rate target.

It is noted here that not all the device types listed in t,:ble 1-1 are

included in table 11-1. The failure rate analysis could not be performed

,,.• •..*'•rr.•'Y--•l •4• 4-11.�%J. % %4- .ýLd' . LA=- . L . J . C Z) I . . I .'. 4- 4=J1 1 [ .L-L

some parts (MIMICs) were not used in these systems. Second, the database

structure for part traceability depends on Westinghouse internal part

=ubers that nust be examined to determine component type (i.e., ASIC,

P"ZM, chip capp.citor, etc.). To perform this task as stated would be

costly and out of scope for this contract. Thet-efore, an alternate

approach was used to collect the failure data.

This approach first identified as many internal part numters for each

component type as possible. Then, these part numbe-rs we-e ccxqpared to the

as-designed parts list for each system. If a matcrh existed, the failure

141

database was search•.-d to identify the number of failures and the total

operate tine of the component. U'fortunately, if the initial list of

caoponent internal part nmtber- was not complete, it is possible that,

alth~ough the cozxronent type was wsd in the system, it would appear as

though that couponent type was not used.

142

12.0 ALTEP-N-ZCE APPROAai

It is well understood that to determirne the influence of each camwornent

failure on the criticality of a mission wunld require a catplete failure

modes and effect- analysis (F!4EA). It is also wJel1 understood that,

dependirg upcn -.. e rchitacture of a system, it is possible to have the

same style of coapnnent in two circuits of different criticality. In one

circuit, failure of the camponent ray result in total missicn failure. In

the other circuit, failure of the cnponent may resiLt in only degraded

performarce. Hawever, because the system mission is of level II

criticality, for example, the applicaticn stresses applied to both

ccanpnets are derated according to the level IT der.tiln criteria.

Actually, the mission-critical oaiponent might have been betteor dezated

according to level I criteria and the other ccx'r-onnt might bave bee•n

better deratea, acrordinj to level III criteria- By choosing Cioy level II

criteria for both ccronens, the mission is potentially in morer jeopardy

due to xcmpoent 1 and tha civnzuit design is overly constrainer due to

ccrronent 2. Unfortunately, this scenario is valid for most system

&-signs, and decidirg whicdh c-iticality level should be used tor which

ccf2onent Jn a given application is futils. An alternate approach to

stress dernting of ccmponenits that can address this dilenmma L proposd.

it is typical, early in the design rtaseA, to perform a reliability

st•yst•ms. In many' cases, t:ese allocations are flo•,,•.l doam to the 2.owest

subsystem level, the camc _ent level. At that time, trade-offs in sy-tem

architecture are made such ttat the system reliability goal may be_

achieved. Stress deratixg guidelines are utilized duri-g this design ptase

to assure mission safety eni success. Since the criticality of each

aumpon.nt on the desired Fystem mission is deperdent upox its role in

pt'formL-Kr the desired function, it is: reasonable to drate the stress on

thxat ccmpornnt according to the "mission" of the cnrponent. The level of

stress derating should therefore Le dependeit upon the acceptable failure

rate of the conponerit in its arplication.

143

In order to derive stress derating criteria that is flexible erngh to be-

utilized in a domain of continuous failure rates requires the stress

derating criteria be -based on accurate reliability models. It is noted

that the updated stress derating criteria for microcirwits and MIMICs

developed as part of this stu4y was based on the updated reliability models

of MII-DESK-217F (to be published). The only differenae between the

approachi taken to update the current version of the Guidplires and this

proposed approach is the replacement of the three levels of criticality

based on system mission type with a contibuais criticality scale based on

camponent "mission".

Ths pr- lem with expanding the scope of criticality levels is identifying

and providiiV accurate values for all the vari.ables associated with

caqaieent failure. This problem is certainly apparent in the example of

microcircuits. Haoever, approximat.iLons, suLi as those used to develop the

critearia in this study, may be made that siplify arnL cornservatively bound

the deratirg criteria until mo.re acurate informatiom is available.

As described earliet 1n this report, the variables of the reliability wrodel

carl be separatead irto thrpee categories, criticality-specific,

device-specitic ard stress-specific. The criticality-specific pxamerters

included the PiE ani PiQ iactors. These factors will typically depend upon

the system mission and cannot be varied to iapprove the safety and suacess

of the ciponent missik-n. The remaining fauctors involving both

devioe-specific and stUess-specific parameters can be varied to improve the

s'afety ird sucess of the cxcponent mission.

A problc=n with evolving cxconerxt reliability models is the rxeed to

incorporate time deperdent failure itnisarams intrt these models. Sinle the

resulting failure rate is no longer constant with time, a failure rate does

notr adequately describe the nuWbr of failures tnat might be expected, that

is, the mean time between failur-es is no longer conotant. Th-efore, it

'ay be more reasonable to describe the cxurnert reliability in tenns of'a

probability of sucax-ss after a given nuqrxr of operating hours.

144

Given both criticality level definition and time dependent failure rateproblems, it is still possible to define the appropriate stress derating

criteria for a ccmponent mission. However, the format in which the stress

derating criteria is to be presented may becoae tedious when presented in

table format. Figures 12-1, 12-2 and 12-3 show graphically the stress

* derating criteria SOas for component missions with probabilities of succss

of 0.9990, 0.9900 and 0.9000, respectively, for ASIC/VHSIC MNS digital

microcircuits. It is noted that because a probability of suocess is used

to generate the SOAs the xzoximm junction temperatures is no longer purely

a function of gate count, when cazqmaed to figures 4-14 throuh 4-16 in

which a constant failure rate was used to generate the SOAs.

Unfortun•tely, to obtain insight into the SOAs for c ncomoent reliability

cther than that for which these graphs were generated requires

interpolation between the grapj s. Although no suggestions are made at this

tine conceriing an acceptable table format for this data, it may bx!

advantageous for the design/reliability engineer to work from stress

derating graphs, such -s the ore presented in figures 12-1 through 12-3, or

better yet, the actual derating algorithms, in order to maintain an

understanding of the trade-offs between component complexity, applied

stress and componerit reliability.

The irportance in making the. stress derating criteria "usable" shculd nort

overwhelm the advantages in making the stress derating criteria arponent

or board "mission" critical rather than system mission critical. The

method by which system design eng 'n.• arrently employ stress derating

guidelines may have to tiange frau time consumz-iq look-ups in the tables of

strtes derating guidelike books to efficient calculations performed

concurtently on the workstation used for producing the system design.

145

Figure 12--1 Ps = 0.9990 SOAs for MOS Digital ASIC/VHSIC

F- -- =1

00

- - _ - to 0\1~

0

(co0) a 0- 0

CL)

V, 0

0-

0 1L C

nunP Tl Iro I i I l I

0 c0

o ooo N- w -

146.

Figure 12-2 Ps 0.9900 SOAs for MOS Digital ASIC/VH SIC

- T1

0

0)00C)

W0 0.4-'. 1o

co joCM- [

co- .001

4-4-

a. -

U) 75

0 U'

U")

00~I to(NJ3 o Y

1.47

Figure 2--3 Ps 0.9000 SOAs for MOS Digital ASIC/VHSIC

' ',W ;

0

-- C)(.) Cci

o2o o

14C)

0 I I I ICL c)

> EC 0~

0

> Qoo 0

0 I

CLC

148

13.0 SUMMARY

There are multiple methods by which stress deratirxg criteria can be

developed. The criteria developed during this study utilized three

methods, the use of existing reliability models, the. generation ofstress-failure relationhps based upon acumulated failure data and

onsergns of stress deratirq guidelines originating from other military and

irrlustrial facilities. Although this latter method utilizes the profound

knowledge of others, there may be no accxnming for how these criteria weredeveloped, and therefore no insight into how to modify the criteria for

charin camponent technologies and complexities. Even thuhg specificstress-failure relationships may be developed from accunulated failure

data, it is not always re&sonable to base the develoqzvnt of the stress

derating criteria on these relationships since the competing effects of the

individual stresses may not being taken into acocumt. The best method (ofthe three methods used), therefore, is the one in which current reliability

cldels are us -d S4 U-2 too %the c- fal- A . ..

This method not only allows the insight into the parameters that may beaffected by changing. component technologi•es and ccplexities, but also

ccubines the ccopeting effects of mfltiple stresses.

Unfortunately, current reliability models were not available for all the

component types described in table 1-1, arn tlerefore the other two methods

of generating stress derating criteria were used. It is noted, however,that mush effort was expezled in evaluating and attempting to update the

reliability models of the discrete ard passive caixonents. mhe literature

searches initially identified over 600 articles of which apprcocimately 240articleG were germane to this study. Of those. 240 articles, 160 articles

were. mrade available and reviewed. Forty-eight cxrponent suppliers of theseventy-two suppliers contacted also provided stxess-failure data.Unfortunately most of the data aocuxulated from these so•r•es cald not be

used to generate stress derating criteria because key elements of the

strcss-failure relatiorsliips were missing. For example, sonie sources didnot provide the time to failure, while other sources left out stress data,

149

and still others neglected to provide a reference point along with the tem-

perature activation energy which is needed to describe the failure distribut-

ion.Mhe level of stress derating should be based upon the expected failure rate

provided by the reliability model. However, not all the factors that may

require derating are currently identified in the reliability model. hese

factors may include outpat current or propagation delay tim. If changes

in these factors result in changes in the observed reliability of the

carponent, then these factors also belong in the reliability molel. An

evaluation of whether the stress deratirn p identified during this

update of the Guidelines should be included in the appruiate_ reliability

model is recxrmenled. In addition, it is reocumended that an alternative

approach to stress derating, as described in section 12.0, be evaluated to

determine the advantages and disadvantages in making the stress derating

criteria ccmonent or board, 'mission" critical rather than system mission

critical.

150

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159

Appendix A

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Apperdix B

C

C PROMGAM DERASICL FOJR

C Cmipute derating oarves for ASIC - MWE Digital andi Lirmearc devrices given a constant prd~ability of suc-ess or aC corstant failure rate (w~ith time). Revision 1C

IMPLICIT REAL*8 (A-11, -Z), I~rBGER*4 (I-F)CJARCTIE*80 HEADERDfl4SION VMMT(7,177) ,NEXT(7)

C Open Ir~it and Ouitput Data Files

OPEN (5, FIIE='IINPU~r. AT' I,STATUS= 'OLD')OPEN (6, FIB~'TEIW. DAV, ,STAITJSz-='NEW,')OPEN (l0,FILE=-' ',STA=S='INEW')

C ¶EVDB Constants

UOX= 8.41)0SO =0.41)0AD = .7816D5rM = 22.1)0Ea =0. 3 YJBD = 2.2221)0BM~T = 4.5D0

C biput Required Data

5 CIrXMNUEREAL (5, 200O,ENh)=50O) ITYPE, DJnM,A,PiQ, PIL, PiE,MINII,MAXTI,

* KLNH, MAXLH, NINTP, MAXrJP, INCrPVP=T (*,2000) IrfYPE,EX]M4Y,A,PiQ,PiL,Pý-F,MnINj,MAXLG,MlNIH,

* ?XTH, M=~r, MAXri, INcm

C Begin Nuznbei of Gates lrxreirnt toWpC

DO0 400 K = 0,6Cc Initialize Data ArrayC

DO0 20 I = 1,7DO0 10 J = 1, 177

NVDATA(1,J) = 0.1)C

D3-1

10 CO~NTINUENEXT (1) =0

20 ODNTIDtJC

GATES = 10.DO**(DBLE(K)/*.2.D0) *1000.M)CC! Calculate # of Tran~sistors andi # of PinsC

TR= GAITES * 4.1)0PINS = 11.07DO * GATz- *jk 0.342D0

CC Calculate MlX, AS, Anaa iI"coe) e-ation, C1 andi C2C

'lOX = 4.931)0 / ' 0. 286W)AS = 1'349.DO TR ** O.0900CALL 7AA(A0,AS, U0,A0CrA)

CCI = 0.0100 + 0.0004271)0 * GATJE5**0.588DO

C2=2.8D)-4 * PINS**1.0800CC Begin Time Incrýrnt IocpC!

DO~ 200 J MAY'~li,MAMXISWIME DBI.E(3)TIME, = 1n.DO~**JrIF (ITYPE) 30,30,40

30 CONJ~TNJEPsmix = DUJMMYElmax = -1.1)6 * DLOG(Psmnax) /lITNEGOlDO 50

40 CrUMIUEElmax = EYM¶YPsmaX = DEXP(-1.D-6 * *~a TDIE)

50 CDNTINUECC Callculate Max Temr Frumi lambda 217F For Numl..-r of Cates andi Pins,C After (Checking For Out Of Range CordiStionC

AG= E'JjdX/(PiQ*Pi-L) - C2 * PLEIF (ARG.IE.0.D0) GWOl 150TEM'P = .DO/298.DO-DLOG(10.1)0*AIlC/C1)/ATEM4P = 1.1)0 / TIEMIP - -A73.1)0MA3CIW-1 = DINT (MI4IN I (1BLE (MAXiP) ,IW

CC Oa~t[ut Status,C

W=-TE (**)'DIV~: I, TF~i?, I Ebrawi = 1ZbaWRrITE (6,*) 'TEXP -',TM3A,' Tý1rna-x = "ma

CC 13#in Temper'ature InrcnexaKnt LoqpC

B~-2

NEXT(J+1) = 0DO~ 100 1 = WMAX P,MAXIMP, INCrP

'IS = DBIE (I)CALL AT (TOn, S, Ea, ACCYAT)

CC Cacul~iate Failure Rate for New TeNmperature Using ?AILr-HDI3K-217FC

PiT = 0.lDO*PEXP(-A*(l.DO/(Ts+273.DO)-l.DO/298.DO))EM = PiQ * PiL * (Cl * PiT + C2 * PiE)IF (EL..GE.E~z-ax.) GOT1O 100Psac =DEXP(-1.D-6 *EL * TIME)Fcc: = 1..D0 - (Psmamx /Psac)CALL ZVAL(Fc-, Z)U =STf4E - SO* ZA(:XAEF = (10.D0**(UO -- U/AGCAA)) /AOCATM~ = DbOG (ACC2AEF) / BMl + DOV = E3 * ¶TUX * 10.1)0IF (V.GT. 18. DO) V =18. DoNEXr(J+1) = NFEcr(J+1) + 1XDATA (3+1, NEXT (J+1)) = VVDATA(1,NE-XT(J+l)) TS

100 ODM71NUEKAXI MAX (NEXT (J) N1DXT(J+1))GWOJX 200

150 0offjh1Y3EWRITE (*,*) 'ARGUMENT aJT OF RANGE'W~rMI (l0,*) 'Am2ALm2 CIT OF RANGE'

200 C0WINr~lUEC

C

'VRITE (** JJMMY,A,PiQ,PiL,PiEWR-iTE kl0,*) £UMMY,A,PiQ,PiL,PiEDO) 300 1=1, MAXI-+1

WRITE (10,1000) 'VDaTA(i,I) ,(VDMAh(J+i,I) ,J=AXUI,MAXLH)300 om~400 CX~?iNhUE

500 STOPCC JFornat Statemm~t.,-C

1,000 FOIRXT (lX, 71F10.22000 FORMAT (12,G9.4,4G8.2,715)

b3-3

IU31 WE AA(AO,AS, TUO,AOC)C

CC SUMi1INE A:CC JPURPOE:CC Calculate the acceleration factor due to dielectric areaC relative to a reference area.CC USAGE:CC CALL AA (AO,ASUO,ACC)CC DESCRIMfION OF PARAMETERS:CC AO - referer~e area (square microns)C AS - operating area (square microns)C UO - log of median t•hi of reference distribution (hours)C ACC - acceleration factorCC SUPROJTITNBE AND FUNCTION S7JBPROGRAMS RIDJTPED:CC Z•AL - calculates number of sigmas frctu the meanC

CT1PLCTI' REAI,*8 (A--H,O-Z), ITITER*4 (I-N)F = AO / (AO + AS)CALL ZVAL(F, Z)AOC = 1. W + (Z / UW)

END

B-4

SUMRUrXTINE AT (TO, TS, Ea, ,AGC)C

CC SUBRUTINE ATCC PRPROSE:Co Calculate the acceleration factor due to tarperature stressC relative to a reference tenpezatu'e-CC USAGE:Co CAlL AT ('ID,Th,,Ea,AOC)CC DESOCRP1TtON OF PARIAMETRaS:CC 110 - reference temperatureC TIS - opeiLating teupenatureo Ea -activation energy, (eV/dag K)C A(X - acre-leration factorCc SUBRUbXrIE A14D FUNCTON SUBFCCX-RAIC RDQUIRED:CC NONEC

CIMPLICIT I-EAL*8 (A-H-,0O-Z), 1NIEGERfl*4 (1-N)B = 8.617D--5ACC = DIX( (Ea/L-')*(1.DO/(¶fl2*273.DQ) - 1.,DO/(TS+273..DO)))PEIYJEN'nm

SUBRYJTINE ZVAL (F, Z)C

CC SUNCUTINE ZVAL~CC PROECC Calculates the number of sigmas away frcmi the mean of aC normal distribuation~ for a given prdoability of failureC (cunilative percent failure in decimal) . This subrcaitibeeC uses the Newton-Paphson methodi of finding~ roots.CC USAGE:CC CALL ZVAL(F, Z)CC DESCIPTION OF PAFPA1EThRS:CC F - probability of failure (canmrlative percent failure inC decimal)C Z - number of sigmas from the me-an of the norffal distributionCC StJBXflJNS AND FUNCrION SUBPiRJGRAIIS REYQ=RE:CC M~A. - cumulative- normlal distribuition approxinationC

CThPUCI PEL*8 (A-H,O-Z), INTDMER*4 (I-N)

CIF (F.I.E.O.SD0) ZNE'W = -O.5D0IF (F.GT.O.5DO) ZNEW = 0.5W~Z = ZNaW

CDO 5 N=-!, 00

IF (IF AG.EXQ.-l) I4FN - O.IX)IT (M~AG.MX.1) flTEW =l.DORII = FNEFPiIP4I = l.DO/(c6QlrT(2.DO*3.141592653589793)*D)EXP(.500*z**2))ZNLV = ZZ=Z - PM¶i / HIR-ItrIF (DAWES(Z-ZNEW)/flBS(Z) .11. 0. OOQOOlODO) RFIURN

5 CflMTNUERL'I1M

END-

tE:4X-INE Q4NDA (Z, F, IFIAG)C

CC SU1BJI'INE CNE)ACC PURRPSE:CC Calculates the value of the cumulative normal distribution atC a given number of sigmas away from the mean. This subroutineC uses a series expansion of the normal distribution to performC the integration.CC USAGE:CC CALL C4DA (Z,F,IFIA)CC DEFI=ON OF PARAMEr:CC Z - nnber of signias frcm the mean = (x - u) /sC F - area under the normal distribution at ZC IFLAG - error flag= 0 OKC -- 1 Z is less than -5. 5C -1 Z is greater than 5.5CC SUBRO=IES AND SUBPROGRAM RBQUIRED:CC NONEC

CIMPLICIT REAL*8 (A-H,O-Z), INTEGER*4 (I-N)N= 0F = O.DO

C1'TrT Ar

IF (Z.Gr.5.5D0) IFLAG = 1IF (Z.LT.-5.5D0) IFtAC = -1IF (I-TAG.NE.0) RPJARN

C1 FAUr = 1.DO

DO 3 N=0,135RN = NIF (N.EQ.0) GO 110 2FACT = FAC' * RN

2 SUMN = (-l.DO)**N * Z**(2*N41)SLUAD = (2.D0*RN41.DO) * 2.DO**N A FACTsW = SUN / SUNDF = F + SUM

3 cou ill".1F = F / 1X3QR1(2.Do * 3.141592653589793) + 0.5D0REIUININD

"-3-7

MISSION

OF

ROME LABORATORY

Rome Laboratory plans and executes an interdisciplinary program in re-

search, development, test, and technology transition in support of Air

Force Command, Control, Communications and Intelligence (C31) activities

for all Air Force platforms. It also executes selected acquisition programs

n several, ureu., of expertise. Technical and engineering support within

areas of competence is provided to ESD Program Offices (POs) and other

ESD elements to perform effective acquisition of C031 systems. In addition,

Rome Laboratory's technology supports other AFSC Product Divisions, the

Air Force user community, and other DOD and non-DOD agencies. Rome

Laboratory maintains technical competence and research prcgrams in areas

including, but not limited to, corn munications, command and control, battlemanagement, intelligence information proeessinjq, computational sciences

~ and software producibility, wide area surveillance/sensors, signal proces-

sing, solid state sciences, photonics, electromagnetic technology, super-

conductivity, and ea .tronic reliAbility/maintainability and testability.