04/10/2023 06:41 AM

A Seminar on ADVANCED TRENDS IN Microprocesssors

PRESENTED BY: 1. Suhel Mulla (MIS no: 121333009)

2. Anjani Gheware (MIS no: 121333003)

College of Engineering, Pune 1

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Discussed TechnologyMicroprocessors advanced through many

stages in the course of time, different features are added to it,two of them which are discussed in the presentation are as follows :

Multicore processing

Inbuilt USB Connectivity

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Moore’s lawIt states that,

“For every 18 to 24 months later in IC fabrication, any one of below case possible –

1. No of transistors on a die gets doubled.2. Size of the chip gets halved.3. Operating frequency gets doubled.4. Supply voltage decreases by √2 times.

If any two conditions are satisfied, that is best design. Any three or all four can never be satisfied.”

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Why Multi-core……?? !!!Shrinking die size and increasing component

density has came to a limit.Escalating clock speed are boosting heat

dissipation problems.Sophisticated pipelining techniques have

reached an optimum balance between improving best case and doing minimum harm in worst case.

Thus, Multi-core processor is a way to extend Moore’s law so that the user gets more performance out of a single piece of silicon.College of Engineering, Pune 4

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Contd… Computer architects needed a new approach to improve

performance. Adding an additional processing core to the same chip

would result in twice the performance and dissipate less heat.

The actual speed of each core is slower than the fastest single core processor.

IEEE Review noted that “the power consumption increases by 60% with every 400MHz rise in clock speed”. But the dual-core approach means you can get a significant boost in performance without the need to run at ruinous clock rates.”

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Microprocessors using multicore architecture

Intel’s Pentium D, core 2 duo & xenon series

AMD’s Athlon, Turion and Opteron series

Sony-Toshiba-IBM’s Cell Processor series

Tilera’s TILE64 Processor

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Conventional Processor Architecture

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Performance and design parameters of multicore processor systems

Power ConsumptionTemperature DissipationFrequency RequirementNo. of Cores in a dieType of cores ( Homogeneous or Heterogeneus )Communication Protocol (e.g. Round Robin, Daisy Chain etc.)Memory Configuration ( Universal vs. Distributed cache )

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Memory Models in Multi-core Processors

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a) Shared memory model b) Distributed memory model

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Comparison of single core and Multi-core Processors

Multicore processors seem to answer the deficiencies of single core processors, by increasing bandwidth while decreasing power consumption.

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Intel and AMD Dual-Core Processors

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Multicore Challenges

Power and Temperature Dependence

Cache Coherence Problem

Multithreading

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Power and Temperature DependenceTo combat unnecessary power consumption

many designs incorporate a power control unit that has the authority to shut down unused cores or limit the amount of power. By powering off unused cores, the amount of leakage in the chip is reduced.

To lessen the heat generated by multiple cores on a single chip, the chip is architected so that the number of hot spots doesn’t grow too large and the heat is spread out across the chip.

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Contd…

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Cell Processor Thermal Digram

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Cache Coherence

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In general there are two schemes for cache coherence, a snooping protocol and a directory-based protocol.

The snooping protocol only works with a bus-based system, and uses a number of states to determine whether or not it needs to update cache entries and if it has control over writing to the block. The directory-based protocol can be used on an arbitrary network and is, therefore, scalable to many processors or cores, in contrast to snooping which isn’t scalable

Intel’s Core 2 Duo tries to speed up cache coherence by being able to query the second core’s L1 cache and the shared L2 cache simultaneously. Having a shared L2 cache also has an added

benefit since a coherence protocol doesn‟t need to be set for this level. AMD‟s Athlon 64 X2,

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Multi-threadingProgrammers have to write applications with

subroutines able to be run in different cores, meaning that data dependencies will have to be resolved or accounted for.

If one core is being used much more than another, the programmer is not taking full advantage of the multi-core system. Applications should be balanced.

Languages with multithreaded extensions are more useful for this purpose.

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Contd…In order to use a multi-core processor at full

capacity the applications run on the system must be multithreaded.

Programmers have to write applications with subroutines able to be run in different cores.

In recent time, companies like Apple, Microsoft designed new products with multi-core facility.

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Universal serial busFeatures:Easy to useFastReliableFlexibleInexpensivePower conserving

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TERMS USED IN USBUSB HostUSB DeviceEnumerationHubEndpoint

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Speed of usb

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Bus Topology

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Data flowControl TransferBulk TransferIsochronous TransferInterrupt Transfer

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Electrical design

Fig : USB Cable

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Powered deviceAt host should pull down register in range

14.25 to 24.8 kohm.Required pull up register of 500 to 900

ohmat device. Bus powerd device.Self power device.

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References Bryan Schaumer, ”Multi-core Processor : A Necessity”,

Realised in Proquest September 2008 D. Geer, “Chip Makers Turn to Multi-core Processors”,

Computer, IEEE Computer Society, May 2009 W. Knight, “Two Heads Are Better Than One”, IEEE

Review, September 2009 P. Frost Gorder, “Multi-core Processors for Science and

Engineering”, IEEE CS, March/April 2007 “Universal Serial Bus Specification”, Revision 2.0,April

27, 2000 Jan Axelson, “USB Complete”, 2nd Edition, Penram

International Publishing.

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Any Questions… ???

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Thank You…!!!

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