ae 773 applied mechatronics

8/14/2019 Ae 773 Applied Mechatronics

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MICROPROCESSOR/MICROCONTROLLER FUNDAMENTALS

AE 773 APPLIED MECHATRONICS

DEPT. OF AEROSPACE ENGINEERING

IIT BOMBAY


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MECHATRONIC SYSTEMS

PRODUCTS, DEVICES, PROCESSES

WHOSE FUNCTIONALITY RELIES ON SYNERGISTIC INTEGRATION OF

MECHANICAL, ELECTRICAL, ELECTRONIC COMPONENTS

CONNECTED BY A CONTROL ARCHITECHTURE

MICROCONTROLLER

(IN MODERN SYSTEMS)


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A microprocessor

key element of a mechatronic device responsible for:

collecting information

processing and decision making storing

handle data in digital form

differences from logic control circuits etc. include:

programmability

digital processing speed

ease of integration

Cost, size..


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General Purpose vs Embedded Processors

General Purpose Processors are mostly used for desk topcomputing

Embedded processors are mostly used for controlling a

system with a fixed function designed to consume small amounts of power

used in everything from

elevators

washing machines

cell phones

network computers set-top boxes for satellite and cable TV

No of embedded processors >> General purpose

processors


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Microprocessor vs Micro-controllers Microprocessors

high end of market where performance matters

high power dissipation

high cost need peripheral devices to work

mostly used in microcomputers

Microcontollers targeted for low end of market where performance does

not matter

low power dissipation

low cost

memory plus I/O de-vices, all integrated into one chip

Mostly used in embedded systems


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Embedded Systems contain microcontroller configured to perform dedicated tasks, along with

any necessary peripheral resources.

application specific hardware and software.

software used to control the embedded processor is not accessible to theuser of the device or system.

required to perform in real time.

external devices provide a limited user interface to the processor.

software: ROM EEPROM, Flash EEPROM; RAM On-chip in single chip mode.

Peripheral devices in expanded mode.

stand-alone system - processor must run software required to control thesystem at power-up.

embedded systems are often required to be low cost, low power andsmall size.


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Outline

Review Microprocessor Fundamentals MPU Register set and Internal Architecture

MPU buses Memory Considerations

MPU interfacing

M68HC11 Microcontroller

Architechture Ports and registers

Application programming


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Review Of MPU Fundamentals

For Simplicity look at a simple model ofan MPU

8-bit

64K address space

Intel style interface


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The CPU processes the data by executing a program stored

in the memory

performs sequence of fetch-and-execute

operations consists of:

Control Unit, ALU, Registers

responsible for the control of address, data andcontrol buses (a master)

all actions within P synchronised to the CPU viaa clock signal

clock signal = a logic square-wave to drive all thecircuitry in the P, typically 1 to 30 MHz


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The Control Unit

determines timing and sequence ofoperations

generates timing signals which are used tofetch program instructions from memory andto execute it

also responsible for decoding instructions supplies control signals to read and write data

into registers, controls ALU and externalcontrol signals


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The ALU

The arithmetic and logic unit (ALU) -responsible for data manipulation

arithmetic operations, logic operations (AND,OR, XOR etc.)

bit shifting, rotating, incrementing,decrementing, negate, complementing,addition etc.


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Registers

Registers data/adresses that CPU currentlyuses - stored in special memory (Small and fast)locations on the CPU

accumulator register- input to ALU is stored temp. flags register ALU latest process result

general purpose register- temporary storage for

data or addresses program counter- tracks CPUs position in program

instruction register-stores instruction where it can

be decoded; not accessible by the programmer index registers- hold data address

stack pointer register- holds the address of the top

of the stack in RAM. Stack - special area of RAM:last-in first-out (LIFO or FILO) file organisation


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General Registers

Small set of internal registers - temporary data storage

CU ensures that data from the correct register ispresented to the CPU

CU ensures that data is written back to correct register Accumulatorusually holds ALU result

Status or Flags RegisterO I T S Z A P C

Overflow Flag

Interrupt Flag

Trap Flag

Sign Flag

Zero Flag

Carry Flag

Parity FlagAuxiliary Flag


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Stack

Part of memory where program data can bestored by a simple PUSH operation

Restore data by a POP Stack is in main memory and is defined by

the program

Stack Pointer (SP) keeps track of the nextlocation available on the Stack

Organised as a FILO Buffer


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Memory Map

Address Bus: 16 bits, 216 = 64K locations.

Data Bus: 8 bits (1 byte)

0000h

FFFFh

1 byte

64K possible locations,

each one is 1 byte wide


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P memory devices

MEMORY

DEVICES

EEPROM (E2PROM)

EPROMROM

RAM

static

dynamic

PROM


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B


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Buses

Data bus - to transfer the data associatedwith the processing function of the

microprocessor. 8 lines, typically Address bus - contains the address of a

specific memory location for accessing stored

data. 16, typically

Control bus - carries the control signals to

the memory and the I/O devices. Arbitrarynumber, often 15

Buses


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Buses

concepts of address and data is fundamental tothe operation of the microprocessor

memory - consists of locations uniquelyidentified by CPU through their address

CPU communicates with those addresses to

read and write the data - all data. the communications go via buses

the CPU - responsible for control of address,

data and control buses

B


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Buses

All devices attached to data bus - potential clash

Devices connected to data buses can be driven

to high-impedance states

The ability of devices to set their output at either

logic 1, logic 0 or in a high impedance state isan essential feature of common bus systemsand is termed a tristate device.


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typical 64k memory map

4K bytesROMRAM

Free

I/O peripheral

User RAM

OS ROM

0x00000x1000

0x2000

0x80000x9000

0xF0000xFFFF

4K bytes

4K bytes

4K bytes

24K bytes

24K bytes

64K byte

M h i l t


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Memory physical arrangement

Memory Read and Write Cycles


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Memory Read and Write Cycles

Hardware Control lines used by the CPU toControl reads and Writes to Memory

Active low signal RD asserted for a ReadCycle

Active Low signal WR indicates a write

RD and WR signals supply timing information

to memory device

Read Cycle


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Read Cycle

8K bytes

OECE

Address

RAM

DataD0..D7

RD

Chip Enable

Output Enable

Read Enable

Processor puts outaddress on the AddressBus, e.g. 50000 0000 0000 0101(A)

Processor asserts theMemory Read signal

Processor reads thecontents of the data bus


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Write Cycle

8K bytes

OECE

Address

RAM

Data

D0..D7

WE

Chip Enable

Output Enable

Write Enable

Processor puts out

address on the Address

Bus, e.g. 9

0000 0000 0000 1001

Processor asserts the

Memory Write signal

Processor writes the data

to the RAM via the data

bus

Timing diagrams read/write cycle


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Timing diagrams - read/write cycle

CLOCK

ADDRESS

DATA

READ

address valid

data valid

CLOCK

ADDRESS

DATA

WRITE

address valid

data valid

(a) read cycle (b) write cycle

1 2

R d l


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Read cycle

It lasts 2 cycles of the clock signal:

1. address of required memory location put onaddress bus (by CPU), at rising edge

2. while device held at tristate level - control

bus issues read signal (active low) to thedevice (2nd cycle begins)

3. after delay - valid data placed on data bus

4. levels on the data bus sampled by CPU atfalling edge of the 2nd cycle

Timing diagrams read/write cycle


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Timing diagrams - read/write cycle

CLOCK

ADDRESS

DATA

READ

address valid

data valid

CLOCK

ADDRESS

DATA

WRITE

address valid

data valid

(a) read cycle (b) write cycle

1 2

Write cycle


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Write cycle

1. CPU places address at rising edge

2. decoding logic selects correct device

3. 2nd cycle - rising edge: CPU outputs data ontodata bus & sets WRITE control bus signal active(LOW)

Note:

memory devices & other I/O components have

static logic - do not depend on clock signal-read data from data bus when write signal high(inactive) - data must be valid for transition


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I/O Instructions vs Memory mapped I/O

Some processors have separate I/O

instructions with an I/O address space,separate from memory (Code and Data)

Allow I/O devices to be decoded separately from

memory devices Some processors only support a single

address space - I/O devices are decoded in

the memory map


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Advantages of Memory Mapped I/O


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Advantages of Memory Mapped I/O

I/O locations are read/written by normalinstructions - no need for separate I/O

instructions Size of instruction set reduced

Memory manipulations can be performeddirectly on I/O locations

No need for separate IORD and IOWR pins

Advantages of Separate I/O Mapping


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Advantages of Separate I/O Mapping

All locations in memory map are available formemory No block removed for I/O

Smaller, faster instructions can be used forI/O

Less Hardware decoding for I/O

Easier to distinguish I/O accesses in

assembly language

Interrupts


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Interrupts

Used to Halt the normal flow of instructions

Exceptions can be due to Hardware or Software

Hardware Interrupts are asynchronous to theprocessor

Could be asserted by an external device requesting

action, e.g. a port ready to transfer data

Interrupts can be globally masked by the processorsInterrupt Enable Flag (IE or I)

IE is set by STI and reset by CLI (or equivalent)

Maskable & Non Maskable Interrupts


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Maskable & Non Maskable Interrupts

Maskable interrupts can be enabled/disabledusing a flag (usually in the flags register

Non Maskable Interrupts (NMI) are toppriority interrupts that cant be masked out

NMIs often used for Parity Errors, Power failsetc

Interrupts


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Interrupts

Main Program

Complete Current InstructionPushFlags Register onto StackPush Instruction Pointer onto Stack

Clear Interrupt Enable FalgTrap to Start of ISR

Interrupt Received

Pop flags from the stackPop Instruction Pointer from the stack

Resume at restored IP address

Main Program

Resumes

Operations shown in

boxes are carriedautomatically by MPU

hardware

ISR

Push Registersonto the Stack

BODY of the ISR

Pop Registersfrom the Stack

Return From Interrupt

Instruction sets


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Instruction sets

The set of instructions given to the P toexecute a task is called an instruction set

Generally, instructions can be classified into thefollowing categories:

Data transfer

Arithmetic

Logical

Program control

Differ depending on the manufacturer, but some

are reasonably common to most P's.

Data transfer


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Data transfer

1. Load

reads the content of a specified memory locationand copies it to the specified register location inthe CPU

2. Store copies the current contents of a specified

register into a specified memory location.

Arithmetic


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3. Add Adds the contents of a specified memory location

to the data in some register 4. Decrement

subtracts 1 from the content of a specified

location.

5. Compare

indicates whether the contents of a register aregreater than, less than or same as the contents ofa specified memory location. The result appearsas a flag in the status register.

Logical


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6. AND carries out the logical AND operation with the

contents of a specified memory location and the

data in some register 7. EXCLUSIVE OR - (similar to 6, but for exclusive OR)

8. Logical shift

moving the pattern of bits in the register one placeto the left or right by moving zero (0) to the end ofthe number

9. Arithmetic shift moving the pattern of bits one place left/right but

with copying of the end number into the vacancy

created by shift

Program control


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g

11. Jump

changes the sequence in which the program isexecuted. So the program counter jumps to some

specified location (other than sequential)

12. Branch

a conditional instruction which might be 'branch if

zero'or 'branch if plus'. It is followed if the rightconditions are met.

13. Halt

stops all further microprocessor activities


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Fetch Decode Execute Cycle


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Obtain instruction from program storage

Determine required actions and instruction size

Compute result value or status

Deposit results in storage for later use

Determine successor instruction

InstructionFetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Locate and obtain operand data


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Machine Cycles and the System Clock


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Each Machine Cycle is spread across 3 4 clockcycles

CPU generates additional signals to synchronisethese events with external events (e.g. responsefrom memory)


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ae 773 applied mechatronics

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