ak5572 english datasheet - velvet sound · 2020. 12. 14. · 30 ovf o analog input over flow flag...

[AK5572]

015016766-E-03 2020/07 - 1 -

1. General Description The AK557x series is a 32-bit, 768 kHz sampling, differential input A/D converter for digital audio systems. It achieves 121 dB dynamic range and 112 dB S/(N+D) while maintaining low power consumption performance. The AK5572 integrates a 2-channel A/D converter, suitable for mixers and multi-channel recorders. Four types of digital filters are integrated and selectable according to the sound quality preference. The AK5572 can be easily connected to a DSP by supporting TDM audio formats. Additionally, it supports DSD output up to 11.2MHz.The channel summation mode improves the dynamic range performance by summing-up multiple channel A/D data and averaging. The dynamic range is improved to 124 dB in 2-to-1 mode.

2. Features

Sampling Rate: 8 kHz - 768 kHz

Input: Full Differential Inputs

S/(N+D): 112 dB

DR: 121 dB (2-to-1 mode: 124 dB)

S/N: 121 dB (2-to-1 mode: 124 dB)

Internal Filter: Four types of LPF, Digital HPF

Power Supply: 4.75-5.25 V (Analog), 1.7-1.98 V or 3.0-3.6 V (Digital)

Output Format

PCM mode: 24/32-bit MSB justified, I2S or TDM

DSD mode: DSD Native 64, 128, 256

Maximized Slot Efficiency in TDM Mode by Optimal Data Placed Mode

Cascade TDM I/F:

TDM512: fs= 48 kHz

TDM256: fs= 96 kHz or 48 kHz

TDM126: fs= 192 kHz, 96 kHz or 48 kHz

Operation Mode: Master Mode & Slave Mode

Detection Function: Input Overflow Flag

Serial Interface: 3-wire Serial and I2C μP I/F (Pin setting is also available)

Power Consumption: 148 mW (@AVDD= 5.0 V, TVDD= 3.3 V, fs= 48 kHz)

Package: 48-pin QFN

2-Channel Differential 32-bit ADC

AK5572

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3. Table of Contents 1. General Description ............................................................................................................................ 1 2. Features .............................................................................................................................................. 1 3. Table of Contents ................................................................................................................................ 2 4. Block Diagram ..................................................................................................................................... 3

■ Block Diagram ..................................................................................................................................... 3 5. Pin Configurations and Functions ...................................................................................................... 4

■ Pin Configurations ............................................................................................................................... 4 ■ Pin Functions ....................................................................................................................................... 5 ■ Handling of Unused Pin ...................................................................................................................... 7

6. Absolute Maximum Ratings ................................................................................................................ 8 7. Recommended Operation Conditions ................................................................................................ 8 8. Analog Characteristics ........................................................................................................................ 9 9. Filter Characteristics ......................................................................................................................... 10

■ ADC Filter Characteristics (fs= 48 kHz) ............................................................................................ 10 ■ ADC Filter Characteristics (fs= 96 kHz) ............................................................................................ 12 ■ ADC Filter Characteristics (fs= 192 kHz) .......................................................................................... 14 ■ ADC Filter Characteristics (fs= 384 kHz) .......................................................................................... 16 ■ ADC Filter Characteristics (fs= 768 kHz) .......................................................................................... 17

10. DC Characteristics ........................................................................................................................ 18 11. Switching Characteristics .............................................................................................................. 19

■ Timing Diagram ................................................................................................................................. 26 12. Functional Descriptions ................................................................................................................. 31

■ Digital Core Power Supply ................................................................................................................ 31 ■ Output Mode ...................................................................................................................................... 31 ■ Master Mode and Slave Mode .......................................................................................................... 31 ■ System Clock .................................................................................................................................... 31 ■ Audio Interface Format ...................................................................................................................... 34 ■ Channel Summation (PCM mode, DSD mode) ................................................................................ 46 ■ Optimal Data Placement Mode (PCM Mode, DSD Mode) ............................................................... 46 ■ CH Power Down & Channel Summation (PCM mode, DSD mode) ................................................ 46 ■ Data Slot Configuration ..................................................................................................................... 50 ■ Digital Filter Setting (PCM mode) ..................................................................................................... 51 ■ Digital HPF (PCM mode)................................................................................................................... 51 ■ Overflow Detection (PCM mode, DSD mode) .................................................................................. 51 ■ LDO ................................................................................................................................................... 52 ■ Reset ................................................................................................................................................. 52 ■ Power Down Function/ Sequence ..................................................................................................... 53 ■ Operation Mode Control .................................................................................................................... 56 ■ Register Control Interface ................................................................................................................. 56 ■ Register Map ..................................................................................................................................... 62 ■ Register Definitions ........................................................................................................................... 62

13. Recommended External Circuits .................................................................................................. 65 14. Package......................................................................................................................................... 68

■ Outline Dimensions ........................................................................................................................... 68 ■ Material & Lead Finish ...................................................................................................................... 68 ■ Marking .............................................................................................................................................. 68

15. Ordering Guide .............................................................................................................................. 69 16. Revision History ............................................................................................................................ 69 IMPORTANT NOTICE ........................................................................................................................... 70

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4. Block Diagram

■ Block Diagram

Figure 1. Block Diagram

Voltage Reference

Serial Output Interface

Delta-Sigma Modulator

Controller

LDO

Decimation Filter

HPF AIN1P

AIN1N DIF0/DSDSEL0

DIF1/DSDSEL1

BICK/DCLK

LRCK/DSDOL1

PSN/CAD0_SPI CKS0/SDA/CDTI CKS1/CAD0_I2C/CSN CKS2/SCL/CCLK CKS3/CAD1

VDD18 VR

EF

H1

VR

EF

L1

LDOE TVDD

AVDD

AVSS

DVSS

PD

N

Delta-Sigma Modulator

Decimation Filter

HPF AIN2P

AIN2N

TDMIN/DSDOR1

SDTO1

DP

TDM0

TDM1

ODP

MC

LK

TE

ST

SL

OW

/DC

KB

SD

/PM

OD

PW

2

PW

1

PW

0

MS

N

OV

F

DC

KS

/HP

FE

I2C

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5. Pin Configurations and Functions

■ Pin Configurations

* The exposed pad at back face of the package must be open or connected to the ground.

Figure 2. Pin Configurations

DIF0/DSDSEL0

DIF1/DSDSEL1

TDM0

TDM1

PSN/CAD0_SPI

I2C

DP

HPFE/DCKS

LDOE

ODP

AIN1P

AIN1N

48QFN TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

36

35

34

33

32

31

30

29

28

27

26

25

37

38

39

40

41

42

43

44

45

46

47

48 Exposed Pad (Back Face) *

SD

/PM

OD

SL

OW

/DC

KB

CK

S3

/CA

D1

CK

S2

/SC

L/C

CL

K

CK

S1

/CA

D0

_I2

C/C

SN

CK

S0

/SD

A/C

DT

I

OV

F

TE

ST

O1

SD

TO

1

TD

MIN

/DS

DO

R1

LR

CK

/DS

DO

L1

BIC

K/D

CL

K

NC

VR

EF

L1

VR

EF

H1

AIN

2N

AIN

2P

AV

DD

AV

SS

TE

ST

IN1

TE

ST

IN2

TE

ST

IN3

TE

ST

IN4

NC

MSN

PW2

PW1

PW0

PDN

VDD18

DVSS

TVDD

MCLK

TEST

TESTIN6

TESTIN5

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■ Pin Functions

No. Pin Name I/O Function Power Down Status

1 NC - No internal bonding. Connect to AVSS. -

2 VREFL1 I ADC Low Level Voltage Reference Input Pin - 3 VREFH1 I ADC High Level Voltage Reference Input Pin - 4 AIN2N I Channel 2 Negative Input Pin - 5 AIN2P I Channel 2 Positive Input Pin - 6 AVDD - Analog Power Supply Pin (AIN1-2), 4.75-5.25 V -

7 AVSS - Analog Ground Pin (AIN1-2) -

8 TESTIN1 - Test Input Pin1 -




12 NC - No internal bonding. Connect to AVSS. -



15 TEST I TEST Enable Pin - 16 MCLK I Master Clock Input Pin -

17 TVDD - Digital I/O Buffers and LDO Power Supply Pin, 1.7-1.98 V (LDOE pin= “L”) or 3.0-3.6 V (LDOE pin= “H”).

-

18 DVSS - Digital Ground Pin -

19 VDD18

I Digital Core Power Supply Pin, 1.7-1.98 V (LDOE pin= “L”) -

O LDO Stabilization Capacitor Connect Pin. (LDOE pin= “H”) Hi-z & Pull Down with

500 Ω

20 PDN I Reset & Power Down Pin “L”: Reset & Power Down, “H” : Normal Operation

-

21 PW0 I Power Management Pin, Channel Summation Select Pin1 -

22 PW1 I Power Management Pin, Channel Summation Select Pin2 -

23 PW2 I Power Management Pin, Channel Summation Select Pin3, - 24 MSN I Master/Slave Select Pin -

25

BICK

I Audio Serial Data Clock Input Pin in PCM & Slave Mode (This pin is pull down by 100 kΩ internally.)

-

O Audio Serial Data Clock Output Pin in PCM & Master Mode (This pin is pull down by 100 kΩ internally.)

Hi-z

DCLK O DSD Clock Output Pin in DSD Mode (This pin is pull down by 100 kΩ internally.)

Hi-z

26

LRCK

I Channel Clock Input Pin in PCM & Slave Mode (This pin is pull down by 100 kΩ internally.)

-

O Channel Clock Output Pin in PCM & Master Mode (This pin is pull down by 100 kΩ internally.)

Hi-z

DSDOL1 O Audio Serial Data Output Pin for AIN1 in DSD Mode (This pin is pull down by 100 kΩ internally.)

Hi-z

27

TDMIN I TDM Data Input Pin in PCM Mode (This pin is pull down by 100 kΩ internally.)

-

DSDOR1 O Audio Serial Data Output Pin for AIN2 in DSD Mode (This pin is pull down by 100 kΩ internally.)

Hi-z

28 SDTO1 O Audio Serial Data Output Pin for AIN1 and AIN2 in PCM Mode L

29 TESTO1 O Test Output Pin1 Hi-z

30 OVF O Analog Input Over Flow Flag Output Pin L

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No. Pin Name I/O Function Power Down Status

31

CKS0 I Clock Mode Select Pin -

SDA I/O Control Data I/O Pin in I2C Bus Serial Control Mode Hi-z

CDTI I Control Data Input Pin in 3-wire Serial Control Mode -

32


CAD0_I2C I Chip Address 0 Pin in I2C Bus Serial Control Mode -

CSN I Chip Select Pin in 3-wire Serial Control Mode -

33


SCL I Control Data Clock Pin in I2C Bus Serial Control Mode -

CCLK I Control Data Clock Pin in 3-wire Serial Control Mode -

34 CKS3 I Clock Mode Select Pin -

CAD1 I Chip Address 1 Pin in I2C Bus or 3-wire Serial Control Mode -

35 SLOW I Slow Roll-OFF Digital Filter Select Pin in PCM Mode -

DCKB I Polarity of DCLK Pin in DSD Mode -

36 SD I Short Delay Digital Filer Select Pin in PCM Mode - PMOD I DSD Phase Modulation Mode Select Pin in DSD Mode -

37 DIF0 I

Audio Data Format Select Pin in PCM Mode “L”: MSB Justified, “H”: I2S

-

DSDSEL0 I DSD Sampling Rate Control Pin in DSD Mode -

38 DIF1 I

Audio Data Format Select Pin in PCM Mode “L”: 24-bit Mode, “H”: 32-bit Mode

-

DSDSEL1 I DSD Sampling Rate Control Pin in DSD Mode -

39 TDM0 I TDM I/F Format Select Pin * This pin must be fixed to “L” when using DSD mode.

-

40 TDM1 I TDM I/F Format Select Pin * This pin must be fixed to “L” when using DSD mode.

-

41 PSN I

Control Mode Select Pin (I2C pin = “H”) “L”:I2C Bus Serial Control Mode, “H” :Parallel Control Mode

-

CAD0_SPI I Chip Address 0 Pin in 3-wire serial control Mode (I2C pin = “L”) -

42 I2C I Control Mode Select Pin “L”: 3-wire Serial Control Mode “H”: I2C Bus Serial Control Mode or Parallel Control Mode

-

43 DP I DSD Mode Enable Pin “L”: PCM Mode, “H”: DSD Mode

-

44 HPFE

I

High Pass Filter Enable Pin “L”: HPF Disable, “H”: HPF Enable

-

DCKS I Master Clock Frequency Select at DSD Mode (DSD Only) -

45 LDOE I

LDO Enable Pin “L”: LDO Disable, “H”: LDO Enable

This pin is pulled down by 100 kΩ internally. -

46 ODP I Optimal Data Placement Mode Enable Pin -

47 AIN1P I Channel 1 Positive Input Pin -

48 AIN1N I Channel 1 Negative Input Pin -

Note 1. All digital input pins must not be allowed to float.

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■ Handling of Unused Pin The unused I/O pins should be connected appropriately. 1. PCM Mode

Classification Pin Name Setting

Analog AIN1-2P, AIN1-2N Open

NC, TESTIN1-6 Connect to AVSS

Digital TDMIN, TEST Connect to DVSS

OVF, TESTO1 Open

2. DSD Mode

Classification Pin Name Setting

Analog AIN1-2P, AIN1-2N Open

NC, TESTIN1-6 Connect to AVSS

Digital TDMIN, TEST Connect to DVSS

SDTO1, OVF, TESTO1 Open

Note 2. Unused channels must be powered down.

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6. Absolute Maximum Ratings (VSS= 0 V; Note 3)

Parameter Symbol Min. Max. Unit

Power Supplies:

Analog (AVDD pin) Digital Interface (TVDD pin) Digital Core (VDD18 pin)(Note 4)

AVDDam TVDDam VDD18am

−0.3 −0.3 −0.3

6.0 4.0 2.5

V V V

Input Current (Any Pin Except Supplies) IIN - 10 mA

Analog Input Voltage (AIN1-4P, AIN1-4N pins) VINA −0.3 AVDD+0.3 V

Digital Input Voltage VIND −0.3 TVDD+0.3 V

Ambient Temperature (Power applied) When the back tab is connected to VSS When the back tab is open

Ta Ta

−40 −40

105 70

C

C

Storage Temperature Tstg −65 150 C

Note 3. All voltages with respect to ground. Note 4. The 1.8 V LDO is off (LDOE pin = “L”) and an external power is supplied to the VDD18 pin. WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

7. Recommended Operation Conditions (VSS= 0 V; Note 3)

Parameter Symbol Min. Typ. Max. Unit

Power Supplies

Analog (AVDD pin) AVDD 4.75 5.0 5.25 V

(LDOE pin= “L”) (Note 5) Digital Interface (TVDD pin) (Note 6) Digital Core (VDD18 pin)

TVDD VDD18

1.7 1.7

1.8 1.8

1.98 1.98

V V

(LDOE pin= “H”) (Note 7) Digital Interface (TVDD pin)

TVDD

3.0

3.3

3.6

V

Voltage Reference (Note 11)

“H” voltage Reference (Note 8) VREFH1 4.75 5.0 5.25 V

“L” voltage reference VREFL1 - AVSS - V

Note 3. All voltages with respect to ground. Note 5. VDD18 must be powered up either at the same time or after TVDD is powered up when the LDOE

pin = “L”. The power up sequence between AVDD pin and TVDD pin or between AVDD pin and VDD18 pin is not critical.

Note 6. TVDD must not exceed VDD18±0.1 V when LDOE pin= “L”. Note 7. When LDOE pin = “H”, the internal LDO supplies 1.8 V (typ). The power up sequences between

AVDD pin and TVDD pin is not critical. Note 8. VREFH1 must not exceed AVDD+0.1 V. Note 9. VREFL1 must be connected to AVSS. Analog Input Voltage is proportional to {(VREFH) – (VREFL)}.

Vin (typ, @ 0dB) = 2.8 {(VREFH) – (VREFL)} / 5 [V]. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

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8. Analog Characteristics

(Ta= 25 C; AVDD= 5.0 V; TVDD= 3.3 V, fs= 48 kHz, BICK= 64fs; Signal Frequency= 1 kHz; 24-bit Data; Measurement frequency= 20 Hz-20 kHz at fs= 48 kHz, 40 Hz-40 kHz at fs= 96 kHz, 40 Hz-40 kHz at fs= 192 kHz, unless otherwise specified.)

Parameter Min. Typ. Max. Unit

Analog Input Characteristics:

Resolution - - 32 Bit

Input Voltage (Note 10) 2.7 2.8 2.9 Vpp

S/(N+D)

fs=48kHz BW=20kHz

−1dBFS −20dBFS −60dBFS

100 - -

112 97 57

- - -

dB dB dB

fs=96kHz BW=40kHz


- - -

110 90 50

- - -

dB dB dB

fs=192kHz BW=40kHz


- - -

110 90 50

- - -

dB dB dB

Dynamic Range (−60dBFS with A-weighted)

Not Sum. mode 2-to-1 mode

117 -

121 124

- -

dB dB

S/N (A-weighted)

Not Sum. mode 2-to-1 mode

117 -

121 124

- -

dB dB

Input Resistance These values will be doubled in DSD 64fs mode. (Values in DSD128 or DSD256 modes are as shown here)

3.0 3.6 4.2 k

Interchannel Isolation (AIN1AIN2)

110 120 - dB

Interchannel Gain Mismatch - 0 0.5 dB

Power Supply Rejection (Note 11) - 60 - dB

Power Supplies

Power Supply Current

Normal Operation (PDN pin = “H”, LDOE pin = “H”)

AVDD+VREFH1

TVDD (fs= 48 kHz)

TVDD (fs= 96 kHz)

TVDD (fs= 192 kHz)

Power down mode (PDN pin = “L”) (Note 12)

AVDD+TVDD

-

-

-

-

-

25

7

11

11

10

33

10

14

14

100

mA

mA

mA

mA

A

Note 10. This value is (AINnP)−(AINnN) that the ADC output becomes full-scale (n=1-2).

Vin = 0.56 (VREFHm−VREFLm) [Vpp]. (m=1) Note 11. PSRR is applied to AVDD, TVDD with 1kHz, 20mVpp sine wave. The VREFH1 is held to the

fixed voltage. Note 12. All digital inputs are fixed to TVDD or TVSS.

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9. Filter Characteristics

■ ADC Filter Characteristics (fs= 48 kHz) (Ta= −40 - +105 C; AVDD= 4.75-5.25 V, TVDD=1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin= “L”))


Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 3) (SD pin=“L”, SLOW pin=“L”)

Passband (Note 13) +0.001/−0.06 dB PB 0 - 22.0 kHz

−6.0 dB - 24.4 - kHz

Stopband (Note 13) SB 27.9 - - kHz

Stopband Attenuation SA 85 - - dB

Group Delay Distortion 0 - 20.0 kHz GD - 0 - 1/fs

Group Delay (Note 14) GD - 19 - 1/fs

Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 4) (SD pin=“L”, SLOW pin=“H”)

Passband (Note 13)

+0.001/−0.076 dB

−6.0 dB

PB

0 -

- 21.9

12.5 -

kHz kHz





Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 5) (SD pin=“H”, SLOW pin=”L”)

Passband (Note 13) +0.001/−0.06 dB PB 0 - 22.0 kHz

−6.0 dB - 24.4 - kHz



Group Delay Distortion 0 - 20.0 kHz GD - - 2.8 1/fs


Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 6) (SD pin=“H”, SLOW pin=“H”)

Passband (Note 13)

+0.001/−0.076 dB

−6.0 dB

PB -

0 -

- 21.9

12.5 -

kHz kHz





Digital Filter (HPF):

Frequency Response (Note 13)

−3.0 dB

−0.5 dB

−0.1 dB

FR - - -

1.0 2.5 6.5

- - -

Hz Hz Hz

Note 13. The passband and stopband frequencies scale with fs.

For example, PB (+0.001 dB/−0.06 dB) =0.46 fs (SHARP ROLL-OFF).

For example, PB (+0.001 dB/−0.076 dB) =0.26 fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog

signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces.

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Figure 3. SHARP ROLL-OFF (fs= 48 kHz)

Figure 4. SLOW ROLL-OFF (fs= 48 kHz)

Figure 5. SHORT DELAY SHARP ROLL-OFF (fs= 48 kHz)

Figure 6. SHORT DELAY SLOW ROLL-OFF (fs= 48 kHz)

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Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 7) (SD pin=“L”, SLOW pin= “L”)

Passband (Note 13)

+0.001/−0.06 dB

−6.0 dB PB

0 -

- 48.8

44.1

-

kHz kHz



Group Delay Distortion 0 ~ 40.0 kHz GD - 0 - 1/fs


Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 8) (SD pin=“L”, SLOW pin= “H”)

Passband (Note 13)

+0.001/−0.076 dB

−6.0 dB PB

0 -

- 43.8

25

-

kHz kHz

Stopband (Note 13) SB 73 - - kHz


Group Delay Distortion 0 ~ 40.0 kHz GD - 0 - 1/fs


Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF (Figure 9) (SD pin=“H”, SLOW pin= “L”)

Passband (Note 13) +0.001/−0.06 dB PB

0 - 44.1 kHz

−6.0 dB - 48.8 - kHz



Group Delay Distortion 0 ~ 40.0 kHz GD - - 2.8 1/fs


Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 10) (SD pin=“H”, SLOW pin= “H”)


0 - 25 kHz

−6.0 dB - 43.8 - kHz



Group Delay Distortion 0 ~ 40.0 kHz GD - - 1.2 1/fs




−3.0 dB

−0.5 dB

−0.1 dB

FR - - -

1.0 2.5 6.5

- - -

Hz Hz Hz


For example, PB (+0.001 dB/−0.06 dB) = 0.46 fs (SHARP ROLL-OFF).

For example, PB (+0.001 dB/−0.076 dB) = 0.26 fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog


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Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 11) (SD pin=“L”, SLOW pin=“L”)

Passband (Note 13)

+0.001/−0.037 dB

−6.0 dB PB

0 -

- 100.2

83.7

-

kHz kHz





Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 12) (SD pin=“L”, SLOW pin=“H”)

Passband (Note 13)

+0.001/−0.1 dB

−6.0 dB PB

0 -

- 75.2

31.5 -

kHz kHz





Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 13) (SD pin=“H”, SLOW pin=“L”)


0 - 83.7 kHz

−6.0 dB - 100.2 - kHz





Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF FILTER (Figure 14) (SD pin=“H”, SLOW pin=“H”)


0 - 31.5 kHz

−6.0 dB - 75.2 - kHz







−3.0 dB

−0.5 dB

−0.1 dB

FR - - -

1.0 2.5 6.5

- - -

Hz Hz Hz


For example, PB (+0.001 dB/−0.037 dB) = 0.436 fs (SHARP ROLL-OFF).

For example, PB (+0.001 dB/−0.1 dB) = 0.164 fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog


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Digital Filter (Decimation LPF) (Figure 15) (SD pin=“X”, SLOW pin=“X”) * It does not depend on the SD pin and SLOW pin.


−0.1 dB

−1.0 dB

−3.0 dB

−6.0 dB

FR

- - - -

81.75 114

137.63 157.2

-

-

-

-

kHz kHz kHz kHz





Note 13. The passband and stopband frequencies scale with fs. Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog


Figure 15. Frequency Response (fs = 384 kHz)

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Digital Filter (Decimation LPF) (Figure 16) (SD pin=“X”, SLOW pin=“X”) * It does not depend on the SD pin and SLOW pin.


−0.1 dB

−1.0 dB

−3.0 dB

−6.0 dB

FR

- - - -

26.25 83.75 144.5 203.1

- - - -

kHz kHz kHz kHz





Note 13. The passband and stopband frequencies scale with fs. Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog


Figure 16. Frequency Response (fs = 768 kHz)

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10. DC Characteristics

(Ta= −40-105 C; AVDD= 4.75-5.25 V, VDD18= 1.7-1.98 V (LDOE pin=“L”))


TVDD= 3.0-3.6 V (LDOE pin=”H”)

High-Level Input Voltage (Note 15) Low-Level Input Voltage (Note 15)

VIH

VIL

70%TVDD

-

-

-

-

30%TVDD

V

V

High-Level Output Voltage (Note 16)

(Iout= −100 µA) Low-Level Output Voltage (Note 17) (except SDA pin: Iout= 100 µA) (SDA pin: Iout= 3 mA)

VOH

VOL

VOL

TVDD−0.5

-

-

-

-

-

-

0.5

0.4

V

V

V

TVDD=1.7-1.98 V (LDOE pin=”L”)

High-Level Input Voltage (Note 15) Low-Level Input Voltage (Note 15)

VIH VIL

80%TVDD -

- -

- 20%TVDD

V V

High-Level Output Voltage (Note 16)

(Iout= −100 µA) Low-Level Output Voltage (Note 17) (except SDA pin: Iout= 100 µA) (SDA pin: Iout= 3 mA)

VOH

VOL

VOL

TVDD−0.3

-

-

-

-

-

-

0.3

20%TVDD

V

V

V

Input Leakage Current Iin - - 10 A

Note 15. MCLK, PDN, PW0-2, MSN, BICK (Slave Mode), LRCK (Slave Mode), TDMIN, SLOW/DCKB, SD/PMOD, CKS0/SDA (Write)/CDTI, CKS1/CAD0_I2C/CSN, CKS2/SCL/CCLK, CKS3/CAD1, DIF0/DSDSEL0, DIF1/DSDSEL1, TDM0, TDM1, PSN/CAD0_SPI, I2C, DP, HPFE/DCKS, LDOE, ODP, TEST

Note 16. BICK (Master Mode)/DCLK, LRCK (Master Mode)/DSDOL1, DSDOR1, SDTO1, OVF Note 17. Note.16 and SDA (Read)

The external pull-up resistors should be connected to TVDD+0.3 V or less.

[AK5572]

015016766-E-03 2020/07 - 19 -

11. Switching Characteristics

(Ta= −40 - +105 C; AVDD= 4.75-5.25 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF)


Master Clock Timing (Figure 18) fCLK dCLK

2.048

45

- -

49.152

55

MHz

% Frequency Duty Cycle

LRCK Frequency (Slave mode) (Figure 17)

Normal mode (TDM1-0 bits = “00”) Normal Speed mode Double Speed mode Quad Speed mode Oct Speed mode Hex Speed mode Duty Cycle

fsn fsd fsq fso fsh

Duty

8

54 108

- -

45

- - -

384 768

-

54

108 216

- -

55

kHz kHz kHz kHz kHz %

TDM128 mode (TDM1-0 bits = “01”) Normal Speed mode Double Speed mode Quad Speed mode High Time Low Time

fsn fsd fsq

tLRH tLRL

8

54 108

1/128fs 1/128fs

- - - - -

54

108 216

- -

kHz kHz kHz ns ns

TDM256 mode (TDM1-0 bits = “10”) Normal Speed mode Double Speed mode High time Low time

fsn fsd

tLRH tLRL

8

54 1/256fs 1/256fs

- - - -

54

108 - -

kHz kHz ns ns

TDM512 mode (TDM1-0 bits = “11”) Normal Speed mode High Time Low Time

fsn

tLRH tLRL

8

1/512fs 1/512fs

- - -

54 - -

kHz ns ns

LRCK Frequency (Master mode) (Figure 18)

Normal mode (TDM1-0 bits = “00”) Normal Speed mode Double Speed mode Quad Speed mode Oct Speed mode Hex Speed mode Duty Cycle

fsn fsd fsq fso fsh

Duty

8

54 108

- - -

- - -

384 768 50

54

108 216

- - -

kHz kHz kHz kHz kHz %

TDM128 mode (TDM1-0 bits = “01”) Normal Speed mode Double Speed mode Quad Speed mode High Time

fsn fsd fsq

tLRH

8

54 108

-

- - -

1/4fs

54

108 216

-

kHz kHz kHz ns

TDM256 mode (TDM1-0 bits = “10”) Normal Speed mode Double Speed mode High Time

fsn fsd

tLRH

8

54 -

- -

1/8fs

54

108 -

kHz kHz ns

TDM512 mode (TDM1-0 bits = “11”) Normal Speed mode High Time

fsn

tLRH

8 -

-

1/16fs

54 -

kHz ns

Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5572 should be reset by the PDN pin or RSTN bit.

[AK5572]

015016766-E-03 2020/07 - 20 -



Audio Interface Timing (Slave mode)

Normal mode (TDM1-0 bits = “00”)

(8 kHz fs 216 kHz) (Figure 19) (LDOE pin = “H”) BICK Period

Normal Speed mode Double Speed mode Quad Speed mode

BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) LRCK to SDTO (MSB) (Except I2S Mode) BICK “↓”toSDTO1

tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD

1/128fsn 1/128fsd 1/64fsq

32 32 25 25 - -

- - - - - - - - -

- - - - - - -

25 25

ns ns ns ns ns ns ns ns ns

Normal mode (TDM1-0 bits = “00”) (8 kHz ≤ fs ≤ 216 kHz) (Figure 19) (LDOE pin = “L”) BICK Period Normal Speed mode(8 kHz ≤ fs ≤ 48 kHz) Double Speed mode(48 kHz ≤ fs ≤ 96 kHz) Quad Speed mode(96 kHz ≤ fs ≤ 192 kHz)

BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) LRCK to SDTO (MSB) (Except I2S Mode) BICK “↓” to SDTO1

tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD

1/128fsn 1/128fsd 1/64fsq

36 36 30 30 - -

- - - - - - -

-

-

- - - - - - -

30 30


Normal mode (TDM1-0 bits = “00”) (fs = 384 kHz, 768 kHz) (Figure 20) BICK Period Oct Speed mode Hex Speed mode

BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1

tBCK tBCK tBCKL tBCKH tLRB tBLR

tBSDD

1/64fso 1/48fsh

12 12 12 12 5

- - - - - - -

- - - - - -

22

ns ns ns ns ns ns ns


Note 19. BICK rising edge must not occur at the same time as LRCK edge.

[AK5572]

015016766-E-03 2020/07 - 21 -



Audio Interface Timing (Slave mode) (Figure 21)

TDM128 mode (TDM1-0 bits = “01”) BICK Period


BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1 TDMIN Hold Time TDMIN Setup Time

tBCK tBCK tBCK

tBCKL tBCKH tLRB tBLR

tBSDD tSDH tSDS

1/128fsn 1/128fsd 1/128fsq

14 14 14 14 5 5 5

- - - - - - - - - -

- - - - - - -

30 - -

ns ns ns ns ns ns ns ns ns ns


Normal Speed mode Double Speed mode

BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1 TDMIN Hold Time TDMIN Setup Time

tBCK tBCK

tBCKL tBCKH tLRB tBLR

tBSDD tSDH tSDS

1/256fsn 1/256fsd

14 14 14 14 5 5 5

- - - - - - - - -

- - - - - -

30 - -



Normal Speed mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “↑” (Note 19) BICK “↑” to LRCK Edge (Note 19) BICK “↑” to SDTO1 TDMIN Hold Time TDMIN Setup Time

tBCK tBCKL tBCKH tLRB tBLR

tBSDD tSDH tSDS

1/512fsn 14 14 14 14 5 5 5

- - - - - - - -

- - - - -

30 - -

ns ns ns ns ns ns ns ns


Note 19. BICK rising edge must not occur at the same time as LRCK edge.

[AK5572]

015016766-E-03 2020/07 - 22 -



Audio Interface Timing (Master mode) (Figure 22)

Normal mode (TDM1-0 bits = “00”) (8 kHz ≤ fs ≤ 216 kHz) BICK Period


BICK Duty BICK “↓” to LRCK Edge BICK “↓”to SDTO1

tBCK tBCK tBCK dBCK tMBLR tBSD

- - - -

−20

−20

1/64fsn 1/64fsd 1/64fsq

50 - -

- - - -

20 20

ns ns ns % ns ns

Normal mode (TDM1-0 bits = “00”) (fs = 384 kHz,768 kHz) (LDOE pin = “H”) BICK Period

Oct speed mode Hex speed mode

BICK Duty BICK “↓” to LRCK Edge BICK “↓” to SDTO1

tBCK tBCK dBCK tMBLR tBSD

- - -

−4

−4

1/64fso 1/64fsh

50 - -

- - - 4 4

ns ns % ns ns

Normal mode (TDM1-0 bits = “00”) (fs = 384 kHz,768 kHz) (LDOE pin = “L”) BICK Period

Oct speed mode Hex speed mode

BICK Duty BICK “↓” to LRCK Edge BICK “↓” to SDTO1

tBCK tBCK dBCK tMBLR tBSD

- - -

−5

−5

1/64fso 1/48fsh

50 - -

- - - 5 5

ns ns % ns ns


[AK5572]

015016766-E-03 2020/07 - 23 -






BICK Duty BICK “↓” to LRCK Edge BICK “↓” to SDTO1 TDMIN Hold Time TDMIN Setup Time

tBCK tBCK tBCK dBCK tMBLR tBSD tSDH tSDS

- - - -

−5

−5 5 5

1/128fsn 1/128fsd 1/128fsq

50 - - - -

- - - - 5 5 - -

ns ns ns % ns ns ns ns


Normal Speed mode Double Speed mode

BICK Duty BICK “↓” to LRCK Edge BICK “↓” to SDTO1 TDMIN Hold Time TDMIN Setup Time

tBCK tBCK dBCK tMBLR tBSD tSDH tSDS

- - -

−5

−5 5 5

1/256fsn 1/256fsd

50 - - - -

- - - 5 5 - -

ns ns % ns ns ns ns


Normal Speed mode BICK Duty BICK “↓” to LRCK Edge BICK “↓” to SDTO1 TDMIN Hold Time TDMIN Setup Time

tBCK dBCK tMBLR tBSD tSDH tSDS

- -

−5

−5 5 5

1/512fsn 50 - - - -

- - 5 5 - -

ns % ns ns ns ns


[AK5572]

015016766-E-03 2020/07 - 24 -




DSD Audio Interface Timing

(64fs mode, DSDSEL 1-0 bits = “00”) DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDOL/R (Note 20)

tDCK tDCKL tDCKH tDDD

-

144 144

−20

1/64fs - - -

- - -

20

ns ns ns ns




-

72 72

−10

1/128fs - - -

- - -

10

ns ns ns ns




-

36 36

−10

1/256fs - - -

- - -

10

ns ns ns ns


Note 20. tDDD is defined from a falling edge of DCLK “↓” to a DSDOL/R edge when DCKB bit = “0” and it is defined from a rising edge of DCLK “↑” to a DSDOL/R edge when DCKB bit = “1”.

[AK5572]

015016766-E-03 2020/07 - 25 -



Control Interface Timing (3-Wire Serial mode): (Figure 25) (Figure 26) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Timing CDTI Hold Timing CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑”

tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH

200 80 80 40 40 150 50 50

- - - - - - - -

- - - - - - - -

ns ns ns ns ns ns ns ns

Control Interface Timing (I2C Bus mode): (Figure 27) SCL CLOCK Frequency Bus Free Time Between Transmissions Start Condition Hold Tune (Prior to First Clock Pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 21) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive Load on Bus

fSCL tBUF

tHD STA tLow

tHIGH tSU STA tHD DAT tSU DAT

tR tF

tSU STO tSP Cb

-

1.3 0.6 1.3 0.6 0.6 0

0.1 - -

0.6 0 -

- - - - - - - - - - - - -

400

- - - - - - -

1.0 0.3 -

50 400

kHz µs µs µs µs µs µs µs µs µs µs ns pF

Power Down & Reset Timing (Figure 28) PDN Pulse Width (Note 22) PDN Reject Pulse Width (Note 22) PDN “↑” to SDTO1 valid (Note 23)

tPD

tRPD tPDV

150

- -

- -

583

-

30 -

ns ns

1/fs

Note 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 22. The AK5572 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held

“L” for more than 150 ns for a certain reset. The AK5572 is not reset by the “L” pulse less than 30 ns.

Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”.

[AK5572]

015016766-E-03 2020/07 - 26 -

■ Timing Diagram [1] PCM mode

1/fCLK

tdCLKL tdCLKH

MCLK

tBCK

tBCKL

VIH

tBCKH

BICK VIL

1/fs

LRCK 50%TVDD

tLRH tLRL Duty=tLRHfs100 or

tLRLfs100

50%TVDD

dCLK=tdCLKHfs100 or

tdCLKLfs100

Figure 17. Clock Timing (Slave mode)

1/fCLK

tCLKL tCLKH

MCLK

1/fBCK

tBCKL tBCKH

BICK 50%TVDD

1/fs

LRCK 50%TVDD

tLRH

VOH

Duty=tLRHfs100

dBCK=tBCKHfBCK100 or

tBCKLfBCK100

50%TVDD

dCLK=tCLKHfCLK100 or

tCLKLfCLK100

Figure 18. Clock Timing (Master mode)

[AK5572]

015016766-E-03 2020/07 - 27 -

tLRB

LRCK

VIH BICK

VIL

tLRS

SDTO1 50%TVDD

tBSD

VIH

VIL

tBLR

Figure 19. Audio Interface Timing (Normal mode & Slave mode: 8kHz≦fs≦216kHz)

tLRB

LRCK

VIH BICK

VIL

SDTO1 50%TVDD

VIH

VIL

tBLR

tBSDD

Figure 20. Audio Interface Timing (Normal & Slave mode: fs=384kHz, 768kHz)

tLRB

LRCK

VIH BICK

VIL

SDTO1 50%TVDD

tBSDD

VIH

VIL

tBLR

tSDS

TDMIN VIH

VIL

tSDH

Figure 21. Audio Interface Timing (TDM & Slave mode)

[AK5572]

015016766-E-03 2020/07 - 28 -

LRCK

BICK

SDTO1

tBSD

tMBLR

50%TVDD

50%TVDD

50%TVDD

TDMIN

tSDH tSDS

VIH

VIL

Figure 22. Audio Interface Timing (Master mode)

[2] DSD mode

VOH DCLK

VOL

tDDD

VOH DSDOL1 DSDOR1

VOL

tDCKH tDCKL

tDCK

Figure 23. Audio Serial Interface Timing (Normal mode, DCKB bit= “0” or DCKB pin= “L”)

VOH DCLK

VOL

tDDD

VOH DSDOL1 DSDOR1

VOL

tDCKH tDCKL

tDCK

tDDD

Figure 24. Audio Serial Interface Timing (Phase Modulation mode, DCKB bit= “0” or DCKB pin= “L”)

[AK5572]

015016766-E-03 2020/07 - 29 -

[3] 3-Wire Serial Interface

tCSS

CSN

VIHCCLK

VIL

VIHCDTI

VIL

VIH

VIL

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

Figure 25. WRITE Command Input Timing (3-wire Serial mode)

CSN

VIH CCLK

VIL

VIH CDTI

VIL

VIH

VIL

D3 D2 D1 D0

tCSW

tCSH

Figure 26. WRITE Data Input Timing (3-wire Serial mode)

[AK5572]

015016766-E-03 2020/07 - 30 -

[4] I2C Interface

tHIGH

SCL

SDA

VIH

tLOWtBUF

tHD:STA

tR tF

tHD:DAT tSU:DAT tSU:STA

Stop Start Start Stop

tSU:STO

VIL

VIH

VIL

tSP

Figure 27. I2C Bus mode Timing

[5] Power-down Timing

Figure 28. Power-down & Reset Timing

VIH

VIL

50%TVDD

tPD

SDTO1

PDN

tPDV tRPD

[AK5572]

015016766-E-03 2020/07 - 31 -

12. Functional Descriptions

■ Digital Core Power Supply The digital core of the AK5572 is operates off of a 1.8 V power supply. Normally, this voltage is generated by the internal LDO from TVDD (3.3 V) for digital interface. The internal LDO will be powered up by setting the LDOE pin = “H”. Set the LDOE pin to “L” and supply a 1.8 V power to the VDD18 pin externally when a 1.8 V is used as TVDD.

■ Output Mode The AK5572 is able to output either PCM or DSD data. The DP pin or DP bit select the output mode. Set the PW2 pin = PW1 pin = PW0 pin = “L” or RSTN bit = “0” or PW2-1 bits = “00” to reset all channels when changing the PCM/DSD mode. The AK5572 outputs data from the SDTO1 pin by BICK and LRCK in PCM mode. DSD data are output from the DSDOL1 and DSDOR1 pin by DCLK in DSD mode.

DP pin DP bit Interface

L 0 PCM

H 1 DSD

Table 1. PCM/DSD Mode Control

■ Master Mode and Slave Mode The AK5572 requires a master clock (MCLK), an audio serial data clock (BICK) and an output channel clock (LRCK) in PCM mode. In this case, the LRCK frequency will be the sampling frequency. Both master and slave modes are available in PCM mode. In master mode, the AK5572 internally generates BICK and LRCK clocks from MCLK inputs and outputs them from the BICK pin and the LRCK pin. MCLK must be synchronized with BICK and LRCK but the phase is not important. The MSN pin controls master/slave mode. The AK5572 is in master mode when the MSN pin = “H” and in slave mode when the MSN pin = “L”. The AK5572 requires a master clock (MCLK) in DSD mode. Slave mode is not available in DSD mode, only master mode is supported.

■ System Clock

[1] PCM Mode The external system clocks, which are required to operate the AK5572, are MCLK, BICK and LRCK in PCM mode. MCLK frequency is determined based on LRCK frequency, according to the operation mode. Table 2, Table 3 and Table 4 show MCLK frequencies correspond to the normal audio rate. Set the frequency ratio between Sampling frequency and MCLK by the CKS3-0 pins (Table 5). All channels must be reset when changing the clock mode or audio interface format by the CKS2-0 pins (bits), TDM1-0 pins (bits), DIF1-0 pins (bits) and the MSN pin. In parallel control mode, all channels will be reset by the PDN pin = “L” or PW2-0 pins = “LLL”. In serial control mode, all channels will be reset by RSTN bit = “0” or PW4-1 bits = “0H”. A stable clock must be supplied after releasing the reset. The AK5572 integrates a phase detection circuit for LRCK. If the internal timing becomes out of synchronization in slave mode, the AK5572 is reset automatically and the phase is resynchronized. The following sequence must be executed when synchronizing multiple AK5572’s. Stop all AK5572’s in reset status by setting the PDN pin = “L” → “H” after stopping the system clock. Make pin or register settings while all channels are in reset status. After that, input the same system clock to all AK5572’s.

[AK5572]

015016766-E-03 2020/07 - 32 -

fs MCLK

32fs 48fs 64fs 96fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs

32 kHz N/A N/A N/A N/A N/A N/A 8.192 MHz

12.288 MHz

16.384 MHz

24.576 MHz

32.768 MHz


18.432 MHz

24.576 MHz

36.864 MHz

N/A


36.864 MHz

N/A N/A N/A

192 kHz N/A N/A N/A N/A 24.576 MHz

36.864 MHz

N/A N/A N/A N/A N/A

384 kHz N/A N/A 24.576 MHz

36.864 MHz

N/A N/A N/A N/A N/A N/A N/A

768 kHz 24.576 MHz

36.864 MHz

N/A N/A N/A N/A N/A N/A N/A N/A N/A

(N/A: Not Available) Table 2 System Clock Example (Slave mode)

fs MCLK



12.288 MHz

16.384 MHz

24.576 MHz

32.768 MHz


18.432 MHz

24.576 MHz

36.864 MHz

N/A


36.864 MHz

N/A N/A N/A

192 kHz N/A N/a N/A N/A 24.576 MHz

36.864 MHz

N/A N/A N/A N/A N/A

384 kHz N/A N/A 24.576 MHz

36.864 MHz


768 kHz 24.576 MHz

36.864 MHz

49.152 MHz

N/A N/A N/A N/A N/A N/A N/A N/A

(N/A: Not available) Table 3. System Clock Example (Master mode)

fs MCLK


32 kHz N/A N/A N/A N/A N/A N/A N/A N/A 16.384 MHz

24.576 MHz

32.768 MHz

48 kHz N/A N/A N/A N/A N/A N/A N/A N/A 24.576 MHz

36.864 MHz

N/A


36.864 MHz

N/A N/A N/A

192 kHz N/A N/a N/A N/A 24.576 MHz

36.864 MHz

N/A N/A N/A N/A N/A

384 kHz N/A N/A 24.576 MHz

36.864 MHz


768 kHz 24.576 MHz

36.864 MHz

N/A N/A N/A N/A N/A N/A N/A N/A N/A

(N/A: Not available) Table 4. System Clock Example (Auto mode)

[AK5572]

015016766-E-03 2020/07 - 33 -

CKS3 pin(bit)

CKS2 pin(bit)

CKS1 pin(bit)

CKS0 pin(bit)

MSN pin MCLK

Frequency Speed Mode

fs Range

L(0) L(0) L(0) L(0) L 128fs

24M Quad Speed

108 kHz fs 216 kHz H

L(0) L(0) L(0) H(1) L 192fs

36M Quad Speed

108 kHz fs 216 kHz H

L(0) L(0) H(1) L(0) L 256fs

12M Normal Speed

8 kHz fs 54 kHz H

L(0) L(0) H(1) H(1) L 256fs

24M Double Speed

54 kHz fs 108 kHz H

L(0) H(1) L(0) L(0) L 384fs

36M Double Speed

54 kHz fs 108 kHz H

L(0) H(1) L(0) H(1) L 384fs

18M Normal Speed

8 kHz fs 54 kHz H

L(0) H(1) H(1) L(0) L 512fs

24M Normal Speed

8 kHz fs 54 kHz H

L(0) H(1) H(1) H(1) L 768fs

36M Normal Speed

8 kHz fs 54 kHz H

H(1) L(0) L(0) L(0) L 64fs

24M Oct Speed

fs = 384 kHz H

H(1) L(0) L(0) H(1) L 32fs

24M Hex Speed

fs = 768 kHz H

H(1) L(0) H(1) L(0) L 96fs

36M Oct Speed

fs = 384 kHz H

H(1) L(0) H(1) H(1) L 48fs

36M Hex Speed

fs = 768 kHz H

H(1) H(1) L(0) L(0)

L NA NA

H 64fs

49.1M Hex Speed

fs = 768 kHz

H(1) H(1) L(0) H(1) L 1024fs

32M Normal Speed

8 kHz ≤ fs ≤ 32 kHz H

H(1) H(1) H(1) L(0) L

NA NA H

H(1) H(1) H(1) H(1) L Auto 8 kHz fs 768 kHz

H NA NA

Table 5. Clock Mode (fs & MCLK Frequency)

[AK5572]

015016766-E-03 2020/07 - 34 -

[2] DSD Mode The AK5572 only supports master mode in DSD mode. The external clock, which is required to operate the AK5572, is MCLK in DSD mode. The AK5572 generates DCLK from MCLK inputs and DSD data outputs (DSDOL1 and DSDOR1) are synchronized with DCLK. The necessary MCLK frequencies are 512fs and 768fs (fs=32 kHz, 44.1 kHz, 48 kHz). MCLK frequency can be changed by the DCKS pin (bit). After exiting reset (PDN pin = “L” → “H”) upon power-up, the AK5572 is in power-down state until MCLK is input.

DCKS pin (bit) MCLK Frequency (default)

L(0) 512fs

H(1) 768fs

Table 6. System Clock (DSD mode) The AK5572 supports 64fs, 128fs and 256fs DSD sampling frequencies (fs= 32 kHz 44.1 kHz, 48 kHz). DSDSEL1-0 pins (bits) control this setting (Table 7).

DSDSEL1 pin (bit)

DSDSEL0 pin (bit)

Frequency Mode

DSD Sampling Frequency

fs= 32 kHz fs= 44.1 kHz fs= 48 kHz

L(0) L(0) 64fs 2.048 MHz 2.8224 MHz 3.072 MHz (default)

L(0) H(1) 128fs 4.096 MHz 5.6448 MHz 6.144 MHz

H(1) L(0) 256fs 8.192 MHz 11.2896 MHz 12.288 MHz

H(1) H(1) - Reserved Reserved Reserved

Table 7. DSD Sampling Frequency Select

■ Audio Interface Format TDM1-0 pins(bits), DIF1-0 pins(bits), SLOW pin(bit) and SD pin(bit) settings should be changed when all channels are reset condition. [1] PCM Mode 48 types of audio interface format can be selected by the TDM1-0 pins (bits), MSN pin and DIF1-0 pins (bits) (Table 8, Table 9). In all formats the serial data is MSB-first, 2's complement format. In master mode, the SDTO1 is clocked out on the falling edge of BICK. Normal output in slave mode, the SDTO1 is clocked out on the falling edge of BICK if 8 kHz ≤ fs ≤ 216 kHz. In other conditions, the data is clocked out on the prior rising edge of BICK to compensate for some delay that renders the edge of data transition near BICK falling edge. Audio interface format is distinguished in four types: Normal mode, TDM128 mode, TDM256 mode and TDM512 mode are available. The TDM1-0 pins (bits) select these modes. In Normal mode (non TDM), AIN1 and AIN2 A/D converted data is output from the SDTO1 pin. The BICK frequency must be in the rage from 48fs to 128fs (fs= 48 kHz) in slave mode if the audio interface format is in normal output (non TDM) and the interface speed is in Normal, Double or Quad mode. Bit length of A/D data is 24-bit or 32-bit and it is selected by the DIF1 pin (bit). The BICK frequency must be set to 32fs, 48fs or 64fs in slave mode if the audio interface format is normal output (non TDM) and the interface speed is in OCT mode. Bit length of A/D data is determined by BICK frequency regardless of the DIF1 pin (bit) if the BICK frequency is 32fs or 48fs. It is 16-bit when the BICK frequency is 32fs and 24-bit when the BICK frequency is 48fs. When the BICK frequency is 64fs, A/D data can be selected between 24-bit and 32-bit by the DIF1 pin (bit).

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The BICK frequency must be set to 32fs or 48fs in slave mode if the audio interface format is normal output (non TDM) and the interface speed is in HEX mode. The 64fs is not available. Bit length of A/D data is determined by BICK frequency regardless of the DIF1 pin (bit). It is 16-bit when the BICK frequency is 32fs and 24-bit when the BICK frequency is 48fs. The BICK frequency will be 64fs in master mode if the audio interface format is normal output (non TDM) and the interface speed is Normal, Double or Quad mode. Data bit length can be selected from 24-bit and 32-bit by the DIF1 pin (bit). The MCLK frequency must be 64fs or 96fs in master mode if the audio interface format is normal output (non TDM) and the interface speed is OCT mode. The BICK frequency will be 64fs. Data bit length can be selected from 24-bit and 32-bit by the DIF1 pin (bit). The BICK frequency will be synchronized with the MCLK frequency in master mode if the audio interface format is normal output (non TDM) and the interface speed is HEX mode. The MCLK frequency must be 32fs, 48fs or 64fs. The bit length of A/D data is 16-bit when the MCLK frequency is 32fs, 24-bit when the MCLK frequency is 48fs and 24-bit or 32-bit can be selected by the DIF1 pin (bit) when the MCLK frequency is 64fs. The DIF0 pin selects the A/D data format between MSB justified and I2S Compatible.

No. Multiplex

Mode Speed Mode

TDM1 pin(bit)

TDM0 pin(bit)

MSN Pin

DIF1 pin(bit)

DIF0 pin(bit)

SDTO LRCK BICK MCLK

Pol. I/O Freq. I/O Freq. I/O

0

Normal

Normal Double Quad

L(0) L(0)

L

L(0) L(0) 24-bit, MSB H/L I 48-128fs I 128-1024fs I

1 L(0) H(1) 24-bit, I2S L/H I 48-128fs I 128-1024fs I

2 H(1) L(0) 32-bit, MSB H/L I 64-128fs I 128-1024fs I

3 H(1) H(1) 32-bit, I2S L/H I 64-128fs I 128-1024fs I

4

H

L(0) L(0) 24-bit, MSB H/L O 64fs O 128-1024fs I

5 L(0) H(1) 24-bit, I2S L/H O 64fs O 128-1024fs I

6 H(1) L(0) 32-bit, MSB H/L O 64fs O 128-1024fs I

7 H(1) H(1) 32-bit, I2S L/H O 64fs O 128-1024fs I

8

OCT HEX

L(0) L(0)

L

* L(0) 16-bit, MSB ↑ I 32fs I 32-96fs I

9 * H(1) 16-bit, I2S ↓ I 32fs I 32-96fs I

10 * L(0) 24-bit, MSB ↑ I 48fs I 32-96fs I

11 * H(1) 24-bit, I2S ↓ I 48fs I 32-96fs I

12 L(0) L(0) 24-bit, MSB ↑ I 64fs * I 32-96fs I

13 L(0) H(1) 24-bit, I2S ↓ I 64fs * I 32-96fs I

14 H(1) L(0) 32-bit, MSB ↑ I 64fs * I 32-96fs I

15 H(1) H(1) 32-bit, I2S ↓ I 64fs * I 32-96fs I

16

H

* L(0) 16-bit, MSB ↑ O 32fs O 32fs I

17 * H(1) 16-bit, I2S ↓ O 32fs O 32fs I

18 * L(0) 24-bit, MSB ↑ O 48fs O 48fs I

19 * H(1) 24-bit, I2S ↓ O 48fs O 48fs I

20 L(0) L(0) 24-bit, MSB ↑ O 64fs O 64-96fs I

21 L(0) H(1) 24-bit, I2S ↓ O 64fs O 64-96fs I

22 H(1) L(0) 32-bit, MSB ↑ O 64fs O 64-96fs I

23 H(1) H(1) 32-bit, I2S ↓ O 64fs O 64-96fs I

*: OCT mode only. Table 8. Audio Interface Format (Normal mode)

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No. Multiplex

Mode Speed Mode

TDM1 pin(bit)

TDM0 pin(bit)

MSN pin

DIF1 pin(bit)

DIF0 pin(bit)

SDTO LRCK BICK MCLK

Edg. I/O Freq. I/O Freq. I/O

24

TDM128 Normal Double Quad

L(0) H(1)

L

L(0) L(0) 24-bit, MSB ↑ I 128fs I 128-1024fs I

25 L(0) H(1) 24-bit, I2S ↓ I 128fs I 128-1024fs I

26 H(1) L(0) 32-bit, MSB ↑ I 128fs I 128-1024fs I

27 H(1) H(1) 32-bit, I2S ↓ I 128fs I 128-1024fs I

28

H

L(0) L(0) 24-bit, MSB ↑ O 128fs O 128-1024fs I

29 L(0) H(1) 24-bit, I2S ↓ O 128fs O 128-1024fs I


31 H(1) H(1) 32-bit, I2S ↓ O 128fs O 128-1024fs I

32

TDM256 Normal Double

H(1) L(0)

L


33 L(0) H(1) 24-bit, I2S ↓ I 256fs I 256-1024fs I


35 H(1) H(1) 32-bit, I2S ↓ I 256fs I 256-1024fs I

36

H


37 L(0) H(1) 24-bit, I2S ↓ O 256fs O 256-1024fs I


39 H(1) H(1) 32-bit, I2S ↓ O 256fs O 256-1024fs I

40

TDM512 Normal H(1) H(1)

L


41 L(0) H(1) 24-bit, I2S ↓ I 512fs I 256-1024fs I


43 H(1) H(1) 32-bit, I2S ↓ I 512fs I 256-1024fs I

44

H


45 L(0) H(1) 24-bit, I2S ↓ O 512fs O 512-1024fs I


47 H(1) H(1) 32-bit, I2S ↓ O 512fs O 512-1024fs I

Table 9. Audio Interface Format (TDM mode)

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Cascade Connection in TDM mode The AK5572 supports cascade connection in TDM mode. All A/D converted data of connected AK5572 are output from the SDTO1 pin of the last AK5572 by cascade connection. When the ODP pin = “L”, a cascade connection of one devices in TDM128 mode, two devices in TDM256 mode and four devices in TDM512 mode are supported. Figure 29 shows a connection example. When the ODP pin = “H”, a cascade connection of two up to sixteen devices is available. When using multiple devices in slave mode on cascade connection, internal operation timing of each device may differ for one MCLK cycle depending on MCLK and BICK input timings. To prevent this timing difference, BICK “↓” should be more than ± 10ns from MCLK “↑” as shown in Table 10. To realize this timing, BICK divided by two should be input on a falling edge of MCLK as shown in Figure 54 when MCLK=2xBICK (normal speed 1024fs mode). When MCLK=BICK (normal speed 512fs mode), MCLK and BICK should be input in-phase as shown in Figure 55 to satisfy the timing shown in Table 10.

48kHz

256fs

256fs, 512fs or 1024fs

GND LRCK

AK5572 #1

BICK

TDMIN

SDTO1

MCLKI

LRCK

AK5572 #2

BICK

TDMIN

SDTO1

MCLKI

16ch TDM

GND LRCK

AK5572 #1

BICK

TDMIN

SDTO1

MCLKI

LRCK

AK5572 #2

BICK

TDMIN

SDTO1

MCLKI

LRCK

AK5572 #8

BICK

TDMIN

SDTO1

MCLKI

TDM256 TDM512

8ch TDM

LRCK

AK5572 #3

BICK

TDMIN

SDTO1

MCLKI

LRCK

AK5572 #4

BICK

TDMIN

SDTO1

MCLKI

256fs, 512fs or 1024fs

Slave mode

Slave mode

Slave mode

Slave mode

Master mode

Slave mode

Slave mode

48kHz

512fs

Figure 29. Cascade Connection

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015016766-E-03 2020/07 - 38 -

LRCK

BICK(64fs)

SDTO1

0 1 2 11 12 13 23 24 31 0 1 2 11 12 13 23 24 31 0

23

1

22 23 22 13 12 11 31

AIN1 Data

13 12 0

23: MSB, 0: LSB

11 1 1 0

AIN2 Data Figure 30. Mode 0/4 Timing (Normal mode, Normal/Double/Quad Speed mode, MSB Justified, 24-bit)

LRCK

BICK(64fs)

SDTO1

0 1 2 3 22 23 24 25 0 0 1 31 29 30

23: MSB, 0: LSB AIN1 Data

0

2 3 22 23 24 25 31 29 30 1

1 23 23 22 2 1 0

AIN2 Data

22 2

Figure 31. Mode 1/5 Timing (Normal mode, Normal/Double/Quad Speed mode, I2S Compatible, 24-bit)

LRCK

BICK(64fs)

SDTO1

0 1 2 11 12 13 20 21 31 0 1 2 12 13 14 24 25 31 0

31

1

30 31 30 22 20 19 31

AIN1 Data AIN2 Data

22 20 11

31: MSB, 0: LSB

1 0 19 12 0 12 11 1

Figure 32. Mode 2/6 Timing (Normal mode, Normal/Double/Quad Speed mode, MSB Justified, 32-bit)

LRCK

BICK(64fs)

SDTO1

0 1 2 3 23 24 25 26 0 0 1 31 29 30

31 30

31: MSB, 0: LSB AIN1 Data AIN2 Data

14

2 3 23 24 25 26 0 31 29 30 1

0 1 2 3 15 16 31 30 16 15 14 3 1 2 0

Figure 33. Mode 3/7 Timing (Normal mode, Normal/Double/Quad Speed mode, I2S Compatible, 32-bit)

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015016766-E-03 2020/07 - 39 -

LRCK (Slave)

BICK (32fs)

SDTO1 (O) 14 9

AIN1 Data

16 BICK

32 BICK

6 1 0 14 9

AIN2 Data

16 BICK

6 1

LRCK (Master)

14 15 8 7 0 15 8 7 0 15

Figure 34. Mode 8/16 Timing (Normal mode, OCT/HEX Speed mode, MSB Justified, 16-bit)

LRCK (Slave)

BICK (32fs)

SDTO1 (O) 14 9

AIN1 Data

16 BICK

32 BICK

6 1 0 14 9

AIN2 Data

16 BICK

6 1

LRCK (Master)

14 15 8 7 0 15 8 7 0 15

Figure 35. Mode 9/17 Timing (Normal mode, OCT/HEX Speed mode, I2S Compatible, 16-bit)

LRCK (Slave)

BICK (48fs)

SDTO1 (O) 22 13

AIN1 Data

24 BICK

48 BICK

10 1 0 22 13

AIN2 Data

24 BICK

10 1

LRCK (Master)

22 23 12 11 0 23 12 11 0 23


LRCK (Slave)

BICK (48fs)

SDTO1 (O) 22 13

AIN1 Data

24 BICK

48 BICK

10 1 0 22 13

AIN2 Data

24 BICK

10 1

LRCK (Master)

22 23 12 11 0 23 12 11 0 23


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015016766-E-03 2020/07 - 40 -

LRCK (Slave)

BICK (64fs)

SDTO1 (O) 22

AIN1 Data

32 BICK

64 BICK

7 0 22 15

AIN2 Data

32 BICK

7 0

LRCK (Master)

22 23 8 23 8 23 15


LRCK (Slave)

BICK (64fs)

SDTO1 (O) 22 15

AIN1 Data 32 BICK

64 BICK

7 0 22 15

AIN2 Data 32 BICK

7 0

LRCK (Master)

22 23 8 23 8 23


LRCK (Slave)

BICK (64fs)

SDTO1 (O) 30 17

AIN1 Data

32 BICK

64 BICK

14 1 0 30 17

AIN2 Data

32 BICK

14 1

LRCK (Master)

30 31 16 15 0 31 16 15 0 31


LRCK (Slave)

BICK (64fs)

SDTO1 (O) 30 17

AIN1 Data

32 BICK

64 BICK

14 1 0 30 17

AIN2 Data

32 BICK

14 1

LRCK (Master)

30 31 16 15 0 31 16 15 0 31


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015016766-E-03 2020/07 - 41 -

LRCK (Slave)

BICK (128fs)

SDTO1 (O) 22 0

Data 1

32 BICK

128 BICK

22 0

Data 2

32 BICK

LRCK (Master)

22 23 23 23

Figure 42. Mode 24/28 Timing (TDM128 mode, MSB Justified, 24-bit)

LRCK (Slave)

BICK (128fs)

SDTO1 (O) 22 0

Data 1

32 BICK

128 BICK

22 0

Data 2

32 BICK

LRCK (Master)

22 23 23 23

Figure 43. Mode 25/29 Timing (TDM128 mode, I2S Compatible)

LRCK (Slave)

BICK (128fs)

SDTO1 (O) 30 1

Data 1

32 BICK

128 BICK

30 1

Data 2

32 BICK

0

LRCK (Master)

30 31 0 31 0 31

Figure 44. Mode 26/30 Timing (TDM128 mode, MSB Justified)

[AK5572]

015016766-E-03 2020/07 - 42 -

LRCK (Slave)

BICK (128fs)

SDTO1 (O) 30 1

Data 1

32 BICK

128 BICK

30 1

Data 2

32 BICK

0

LRCK (Master)

30 31 0 31 0 31

Figure 45. Mode 27/31 Timing (TDM128 mode, I2S Compatible)

LRCK (Slave)

BICK (256fs)

SDTO1 (O) 22 0

#4 Data 1

32 BICK

256 BICK

22 0

#4 Data 2

32 BICK

22 22 0

#3 Data 1

32 BICK

22 0

#3 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#3 SDTO1)

22 0

#3 Data 1

32 BICK

22 0

#3 Data 2

32 BICK

22 22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

23 23 23 23 23 23 23 23 23

23 23 23 23 23 22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

23 23


LRCK (Slave)

BICK (256fs)

SDTO1 (O) 22 0

#4 Data 1

32 BICK

256 BICK

22 0

#4 Data 2

32 BICK

22 0

#3 Data 1

32 BICK

22 0

#3 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#3 SDTO1)

22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

23 23 23 23 23 23 23 23 23

23 23 23 23 23 22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

23 23

Figure 47. Mode 33/37 Timing (TDM256 mode, I2S Compatible, 24-bit)

[AK5572]

015016766-E-03 2020/07 - 43 -

LRCK (Slave)

BICK (256fs)

SDTO1 (O) 30 1

#4 Data 1

32 BICK

256 BICK

30 1

#4 Data 2

32 BICK

30 30 1

#3 Data 1

32 BICK

30 1

#3 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#3 SDTO1)

30 1

#3 Data 1

32 BICK

30 1

#3 Data 2

32 BICK

30 30 1

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

30 1

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

30 1

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31

31 0 31 0 31 0 31 0 31 30 1

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

31 0 31 0


LRCK (Slave)

BICK (256fs)

SDTO1 (O) 30 1

#4 Data 1

32 BICK

256 BICK

30 1

#4 Data 2

32 BICK

0 30 1

#3 Data 1

32 BICK

30 1

#3 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#3 SDTO1)

30 1

#3 Data 1

32 BICK

30

#3 Data 2

32 BICK

30 1

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

30 1

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

30 1

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31

31 0 31 0 31 0 31 0 31 30 1

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

31 0 31 0


LRCK (Slave)

BICK (512fs)

SDTO1 (O) 22 0

#8 Data 1

32 BICK

512 BICK

33 0

#8 Data 2

32 BICK

22 0

#7 Data 1

32 BICK

22 0

#7 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#7 SDTO1)

22 0

#7 Data 1

32 BICK

22 0

#7 Data 2

32 BICK

30 22 0

#6 Data 1

32 BICK

22 0

#6 Data 2

32 BICK

22 0

#6 Data 1

32 BICK

22 0

#6 Data 2

32 BICK

22 0

#5 Data 1

32 BICK

22 0

#5 Data 2

32 BICK

22 0

#4 Data 1

32 BICK

22 0

#4 Data 2

32 BICK

22 0

#3 Data 1

32 BICK

22 0

#3 Data 2

32 BICK

22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

22 0

#5 Data 1

32 BICK

22 0

#5 Data 2

32 BICK

22 0

#4 Data 1

32 BICK

22 0

#4 Data 2

32 BICK

23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23

31

22 23

23 23 23 23 23 23 23 23 22 0

#3 Data 1

32 BICK

22 0

#3 Data 2

32 BICK

22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

23 23 23 23 22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

23 23


[AK5572]

015016766-E-03 2020/07 - 44 -

LRCK (Slave)

BICK (512fs)

SDTO1 (O) 22 0

#8 Data 1

32 BICK

512 BICK

22 0

#8 Data 2

32 BICK

22 0

#7 Data 1

32 BICK

22 0

#7 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#7 SDTO1)

22 0

#7 Data 1

32 BICK

22 0

#7 Data 2

32 BICK

22 0

#6 Data 1

32 BICK

22 0

#6 Data 2

32 BICK

22 0

#6 Data 1

32 BICK

22 0

#6 Data 2

32 BICK

22 0

#5 Data 1

32 BICK

22 0

#5 Data 2

32 BICK

22 0

#4 Data 1

32 BICK

22 0

#4 Data 2

32 BICK

22 0

#3 Data 1

32 BICK

22 0

#3 Data2

32 BICK

22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

22 0

#1 Data 1

32 BICK

22 0

#1 Data2

32 BICK

22 0

#5 Data 1

32 BICK

22 0

#5 Data 2

32 BICK

22 0

#4 Data 1

32 BICK

22 0

#4 Data 2

32 BICK

23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23

23

23

23 23 23 23 23 23 23 23 22 0

#3 Data 1

32 BICK

22 0

#3 Data 2

32 BICK

22 0

#2 Data 1

32 BICK

22 0

#2 Data 2

32 BICK

23 23 23 23 22 0

#1 Data 1

32 BICK

22 0

#1 Data 2

32 BICK

23 23


LRCK (Slave)

BICK (256fs)

SDTO1 (O) 30 1

#8 Data 1

32 BICK

512 BICK

30 1

#8 Data 2

32 BICK

30 1

#7 Data 1

32 BICK

30 1

#7 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#7 SDTO1)

30 1

#7 Data 1

32 BICK

30 1

#7 Data 2

32 BICK

30 30 1

#6 Data 1

32 BICK

30 1

#6 Data 2

32 BICK

30 1

#6 Data 1

32 BICK

30 1

#6 Data 2

32 BICK

30 1

#5 Data 1

32 BICK

30 1

#5 Data 2

32 BICK

30 1

#4 Data 1

32 BICK

30 1

#4 Data 2

32 BICK

30 1

#3 Data 1

32 BICK

30 1

#3 Data 2

32 BICK

30 1

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

30 1

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

30 1

#5 Data 1

32 BICK

30 1

#5 Data 2

32 BICK

30 1

#4 Data 1

32 BICK

30 1

#4 Data 2

32 BICK

30 1

#3 Data 1

32 BICK

30 1

#3 Data 2

32 BICK

30 0

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0

31

30 31

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 1 31 0 30 0

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

31 1 31 0


LRCK (Slave)

BICK (256fs)

SDTO1 (O) 30 1

#8 Data 1

32 BICK

512 BICK

30 1

#8 Data 2

32 BICK

30 1

#7 Data 1

32 BICK

30 1

#7 Data 2

32 BICK

LRCK (Master)

TDMIN (I)

(#7 SDTO1)

30 1

#7 Data 1

32 BICK

30 1

#7 Data 2

32 BICK

30 1

#6 Data 1

32 BICK

30 1

#6 Data 2

32 BICK

30 1

#6 Data 1

32 BICK

30 1

#6 Data 2

32 BICK

30 1

#5 Data 1

32 BICK

30 1

#5 Data 2

32 BICK

30 1

#4 Data 1

32 BICK

30 1

#4 Data 2

32 BICK

30 1

#3 Data 1

32 BICK

30 1

#3 Data2

32 BICK

30 1

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

30 1

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

30 1

#5 Data 1

32 BICK

30 1

#5 Data 2

32 BICK

30 1

#4 Data 1

32 BICK

30 1

#4 Data 2

32 BICK

30 1

#3 Data 1

32 BICK

30 1

#3 Data 2

32 BICK

30 0

#2 Data 1

32 BICK

30 1

#2 Data 2

32 BICK

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0

31

31

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 1 31 0

0

30 0

#1 Data 1

32 BICK

30 1

#1 Data 2

32 BICK

31 1 31 0


Parameter Symbol Min. Typ. Max Unit

MCLK “↑” to BICK “↓” BICK “↓” to MCLK“↑”

tMCB tBIM

10 10

ns ns

Table 10. TDM Mode Clock Timing

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Figure 54. Audio Interface Timing (Slave mode, TDM mode MCLK=2×BICK)

Figure 55. Audio Interface Timing (Slave mode, TDM mode MCLK=BICK)

[2] DSD mode DSD output is available only when the AK5572 is in Master mode. The DCLK frequency can be selected from 64fs, 128fs and 256fs by setting the DSDSEL1-0 pins (bits). The AK5572 enters Phase Modulation mode by setting PMOD pin = “H” or PMOD bit = “1”. It does not support Phase Modulation mode when the DCLK frequency is 256fs. DCKB bit controls DCLK polarity.

DCLK (64fs, 128fs, 256fs) DCKB bit=”1”

DCLK (64fs, 128fs, 256fs) DCKB bit=”0”

DSDOL, DSDOR Normal

DSDOL,DSDOR Phase Modulation

D1

D0 D1 D2

D0 D2 D3

D1 D2 D3

Figure 56. DSD Mode Timing

MCLK

BICK

tMCB tBIM

VIH

VIL

VIH

VIL

MCLK

BICK

tMCB tBIM

VIH

VIL

VIH

VIL

[AK5572]

015016766-E-03 2020/07 - 46 -

■ Channel Summation (PCM mode, DSD mode) Channel Summation function improves the dynamic range and S/N performance by averaging all A/D data of multiple-channel that the same signal is input. The AK5572 supports 2-to-1 mode. 2-to-1 mode (Mono mode)

Improve the dynamic range and S/N for 3 dB (1.5 dB in DSD mode) by averaging two channels. Not-Summation mode (Stereo mode)

Normal mode that does not execute Summation is called as Not-Summation mode or Stereo mode. Refer to the section “CH Power Down & Channel Summation mode” for details.

■ Optimal Data Placement Mode (PCM Mode, DSD Mode) Assigned data to the SDTO1 slot is controlled by the ODP pin setting in parallel control mode. When the ODP pin = “L”, the data is output by Fixed Data Placement mode. Channel assignment of data slot is fixed regardless of enable/disable of channel summation. For example, averaging data of two channels are output to both channel slots. When the ODP pin = “H”, the data is output by Optimal Data Placement mode that is uses data slot more efficiently. In Optimal Data Placement mode, there are no data redundant of channel summation, and the data is output in MSB justified. Therefore, the maximum number of connecting device in cascade connection will be increased. If the AK5572 is set to 2-to-1 mode (Mono Mode), four devices can be connected in TDM128 mode, eight devices can be connected in TDM256 mode and sixteen devices can be connected in TDM512 mode. In serial control mode, the data output is Optimal Data Placement mode regardless of the ODP pin setting. Refer to “CH Power Down & Channel Summation mode” for details.

■ CH Power Down & Channel Summation (PCM mode, DSD mode) [1] Parallel mode The setting of the PW2-0 pins and the ODP pin controls the channel power-down and channel summation mode setting in parallel mode (Table 11 - Table 16). The PDN pin must be set to “L” when changing the ODP pin and the PW2-0 pins. The power consumption of the device can b

ak5572 english datasheet - velvet sound · 2020. 12. 14. · 30 ovf o analog input over flow flag...

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