Alignment Marker Mapping and Insertion - Supporting Material for Comment #3 and #2

Adrian Butter (on behalf of the P802.3bs Logic Ad Hoc team)

Contributors

• Mark Gustlin, Xilinx• Pete Anslow, Ciena• Ben Jones, Xilinx• Jeff Slavick, Avago Technologies• Eric Baden, Broadcom• Juan Carlos Calderon, Inphi• David Ofelt, Juniper Networks• Tongtong Wang, Huawei• Phil Sun, Credo Semiconductor

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Supporters

• Gary Nicholl, Cisco

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Introduction➢ Alignment Marker format definition is one of the Logic Ad Hoc BTIs to resolve in support of a technically

complete P802.3bs draft:

➢ Since December 2015, several Logic Ad Hoc team members have made excellent contributions towards resolving this BTI! For example:

○ Toward 400GbE AMs and PAM4 test pattern characteristics○ 400GbE AMs revised proposal○ Proposed AM Format

➢ Logic Ad Hoc team consensus has been attained on Alignment Marker formatting.➢ Comment #3 was logged against P802.3bs D1.2 to support technical updates capturing this consensus.

○ Comment #2 was also logged identifying an ancillary issue found during this activity.○ As a bonus, the proposed response to comment #69 is also included...

➢ Editing details supporting these technical updates are contained in “butter_3bs_02a_0316”.➢ This presentation identifies those updates with supporting material...

Note: Slide changes based on suggestions received during the 23-Feb-2016 400Gb/s Logic Ad Hoc call are denoted with in the upper right corner.

4Note: Slide changes since submission of butter_3bs_01_0316 are denoted with in the upper right corner.

D1.2 Comments Regarding Alignment Markers

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ObjectivesChange alignment marker format from: … to:

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Objectives

m513

m512

m511

m510

m509

m508

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m513

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m505 m497

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m473 m465

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mNNN 10-bit Message symbol NNN of FEC codeword A. mNNN 10-bit Message symbol NNN of FEC codeword B.

Map alignment markers to FEC codewords in the following manner:

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BitRange 20 23 24 29 30 31 32 39 50 55 56 59 60 63 64 69 80 87 88 89 90 95 96 99 120 129

0

1

2

3

12

13

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Lane

0:5

6:11

12:17

18:23

72:77

78:83

84:89

90:95

98:99

96:97

102:103

100:101

122:123

120:121

126:127

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132:135

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366:371

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378:383

372:377

384:393

394:403

404:413

414:423

504:513

514:519

x:y = PRBS9 bit range for the current Alignment Marker insertion operation (bit 0 generated first).10-bit Message symbol of FEC codeword A. 10-bit Message symbol of FEC codeword B.

PRBS9 padding is organized in the following manner:

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Objectives

Comment #3 and #69 Update - 119.2.4.4 Paragraph 1

Note: Changes since 23-Feb-2016 400Gb/s Logic Ad Hoc call appear in red italicized text. 9

Proposed response to comment #69...

Comment #3 Update - 119.2.4.4 Paragraph 2

Note: Changes since 23-Feb-2016 400Gb/s Logic Ad Hoc call appear in red italicized text. 10

Comment #3 Update - 119.2.4.4 Paragraph 3, Figure 119-4

Note: Changes since 23-Feb-2016 400Gb/s Logic Ad Hoc call appear in red italicized text. 11

Comment #3 Update - 119.2.4.4 Paragraph 4, Table 119-1

Note: Changes since 23-Feb-2016 400Gb/s Logic Ad Hoc call appear in red italicized text.

PCS lane Encodingnumber {CM0 , CM1 , CM2 , CM3 , CM4 , CM5 , UM0 , UM1 , UM2 , UM3 , UM4 , UM5}0 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x9E , 0xEB , 0x27 , 0x61 , 0x14 , 0xD81 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x50 , 0x74 , 0x88 , 0xAF , 0x8B , 0x772 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0xB4 , 0xB7 , 0xEA , 0x4B , 0x48 , 0x153 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0xE4 , 0xFB , 0xF1 , 0x1B , 0x04 , 0x0E4 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0xDC , 0x58 , 0xEE , 0x23 , 0xA7 , 0x115 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0xBD , 0xA9 , 0xBF , 0x42 , 0x56 , 0x406 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x97 , 0x67 , 0x77 , 0x68 , 0x98 , 0x887 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x24 , 0x35 , 0xA5 , 0xDB , 0xCA , 0x5A8 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x57 , 0x64 , 0x51 , 0xA8 , 0x9B , 0xAE9 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x28 , 0xF9 , 0x3E , 0xD7 , 0x06 , 0xC110 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0xCB , 0xD1 , 0xAD , 0x34 , 0x2E , 0x5211 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x5E , 0x1E , 0x38 , 0xA1 , 0xE1 , 0xC712 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x19 , 0x98 , 0xF9 , 0xE6 , 0x67 , 0x0613 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x84 , 0xEC , 0x20 , 0x7B , 0x13 , 0xDF14 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x13 , 0xA4 , 0xED , 0xEC , 0x5B , 0x1215 0x9A , 0x4A , 0x26 , 0x65 , 0xB5 , 0xD9 , 0x3F , 0x8A , 0xBE , 0xC0 , 0x75 , 0x41

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Comment #3 Update - 119.2.4.4 Paragraph 5+ (New Content)

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Comment #3 Update - 119.2.4.4 Paragraph 5+ (New Content)

Note: Changes since 23-Feb-2016 400Gb/s Logic Ad Hoc call appear in red italicized text. 14

Comment #3 Update - 119.2.4.4 Paragraph 5+ (New Content)

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Comment #3 and #2 Update - 119.2.4.4 Paragraph 5+ (New Content)

Note: Changes since 23-Feb-2016 400Gb/s Logic Ad Hoc call appear in red italicized text. 16

Comment #3 and #2 Update - 119.2.4.5

Note: Changes since 23-Feb-2016 400Gb/s Logic Ad Hoc call appear in red italicized text. 17

Thanks!

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