altera remote update ip core user guide · 2021. 1. 1. · altera remote update ip core user guide...

Altera Remote Update IP Core User Guide2015.01.23

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The Altera Remote Update IP core implements a remote system update using dedicated remote systemupgrade circuitry available in supported devices.

Remote system update helps you deliver feature enhancements and bug fixes without recalling yourproduct, and reduces time-to-market and extends product life. The Altera Remote Update IP coredownloads a new configuration image from a remote location, stores the image in a configuration device,and upgrades the configuration circuitry to start a reconfiguration cycle.

The dedicated circuitry performs error detection during and after the configuration process. When thededicated circuitry detects errors, the circuitry facilitates system recovery by reverting back to a safe,default factory configuration image and then provides error status information.

The following figure shows a functional diagram for a typical remote system update process.

Figure 1: Typical Remote System Update Process

Device ControlModule

DevelopmentLocation

Device Configuration

Network

DataData

Data

Configurationdevices

(Serial flash)

Note: Altera recommends you to use 20–MHz fMAX for all devices.

Related Information

• Configuration Center• ALTREMOTE_UPDATE Knowledge Base

Installing and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for production use without purchasing anadditional license. You can evaluate any Altera® IP core in simulation and compilation in the Quartus® IIsoftware using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore® functions,require that you purchase a separate license for production use. You can use the OpenCore Plus feature toevaluate IP that requires purchase of an additional license until you are satisfied with the functionality andperformance. After you purchase a license, visit the Self Service Licensing Center to obtain a licensenumber for any Altera product.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

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Figure 2: IP Core Installation Path

acds

quartus - Contains the Quartus II softwareip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code<IP core name> - Contains the IP core source files

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is<home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site• Altera Software Installation and Licensing Manual

Customizing and Generating IP CoresYou can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog andparameter editor allow you to quickly select and configure IP core ports, features, and output files.

IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize andintegrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,and generate files representing your custom IP variation.

Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-InManager for IP selection and parameterization, beginning in Quartus II software version 14.0. Usethe IP Catalog and parameter editor to locate and paramaterize Altera IP cores.

The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parametereditor and generate files representing your IP variation. The parameter editor prompts you to specify anIP variation name, optional ports, and output file generation options. The parameter editor generates atop-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. Youcan also parameterize an IP variation without an open project.

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families.• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access

partner IP information on the Altera website.• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's

installation folder, andor view links to documentation.

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Figure 3: Quartus II IP Catalog

Search and filter IP for your target device

Double-click to customize, right-click for information

Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includesexclusive system interconnect, video and image processing, and other system-level IP that are notavailable in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, referto Creating a System with Qsys in the Quartus II Handbook.

Using the Parameter EditorThe parameter editor helps you to configure IP core ports, parameters, and output file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter valuesfor specific applications.

• View port and parameter descriptions, and links to documentation.• Generate testbench systems or example designs (where provided).

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Figure 4: IP Parameter Editors

View IP portand parameter details

Apply preset parameters forspecific applications

Specify your IP variation nameand target device

Legacy parameter editors

Specifying IP Core Parameters and OptionsThe parameter editor GUI allows you to quickly configure your custom IP variation. Use the followingsteps to specify IP core options and parameters in the Quartus II software. Refer to Specifying IP CoreParameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacyparameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variationsettings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one ormore of the following. Refer to your IP core user guide for information about specific IP coreparameters.

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specificfeatures.

• Specify options for processing the IP core files in other EDA tools.4. Click Generate HDL, the Generation dialog box appears.5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.6. To generate a simulation testbench, click Generate > Generate Testbench System.

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7. To generate an HDL instantiation template that you can copy and paste into your text editor, clickGenerate > HDL Example.

8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. Ifyou are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files inProject to add the file.

9. After generating and instantiating your IP variation, make appropriate pin assignments to connectports.

Figure 5: IP Parameter Editor

View IP portand parameter details

Apply preset parameters forspecific applications

Specify your IP variation nameand target device

Upgrading IP CoresIP core variants generated with a previous version of the Quartus II software may require upgradingbefore use in the current version of the Quartus II software. Click Project > Upgrade IP Components toidentify and upgrade IP core variants.

The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, orunsupported for specific IP cores in your design. You must upgrade IP cores that require it before you cancompile the IP variation in the current version of the Quartus II software. Many Altera IP cores supportautomatic upgrade.

The upgrade process renames and preserves the existing variation file (.v, .sv, or .vhd) as <my_variant>_BAK.v, .sv, .vhd in the project directory.

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Table 1: IP Core Upgrade Status

IP Core Status Corrective Action

Required Upgrade IPComponents

You must upgrade the IP variation before compiling in the current version ofthe Quartus II software.

Optional Upgrade IPComponents

Upgrade is optional for this IP variation in the current version of the QuartusII software. You can upgrade this IP variation to take advantage of the latestdevelopment of this IP core. Alternatively you can retain previous IP corecharacteristics by declining to upgrade.

Upgrade Unsupported Upgrade of the IP variation is not supported in the current version of theQuartus II software due to IP core end of life or incompatibility with thecurrent version of the Quartus II software. You are prompted to replace theobsolete IP core with a current equivalent IP core from the IP Catalog.

Before you begin

• Archive the Quartus II project containing outdated IP cores in the original version of the Quartus IIsoftware: Click Project > Archive Project to save the project in your previous version of the Quartus IIsoftware. This archive preserves your original design source and project files.

• Restore the archived project in the latest version of the Quartus II software: Click Project > RestoreArchived Project. Click OK if prompted to change to a supported device or overwrite the projectdatabase. File paths in the archive must be relative to the project directory. File paths in the archivemust reference the IP variation .v or .vhd file or .qsys file (not the .qip file).

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IPcore variation. The Upgrade IP Components dialog automatically displays the status of IP cores inyour project, along with instructions for upgrading each core. Click Project > Upgrade IPComponents to access this dialog box manually.

2. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform AutomaticUpgrade. The Status and Version columns update when upgrade is complete. Example designsprovided with any Altera IP core regenerate automatically whenever you upgrade the IP core.

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Figure 6: Upgrading IP Cores

Displays upgrade status for all IP coresin the Project

Upgrades all IP core that support “Auto Upgrade”Upgrades individual IP cores unsupported by “Auto Upgrade”

Checked IP cores support “Auto Upgrade”

Successful“Auto Upgrade”

Upgradeunavailable

Double-click toindividually migrate

Example 1: Upgrading IP Cores at the Command Line

You can upgrade IP cores that support auto upgrade at the command line. IP cores that do notsupport automatic upgrade do not support command line upgrade.

• To upgrade a single IP core that supports auto-upgrade, type the following command:

quartus_sh –ip_upgrade –variation_files <my_ip_filepath/my_ip>.<hdl> <qii_project>

Example:quartus_sh -ip_upgrade -variation_files mega/pll25.v hps_testx

• To simultaneously upgrade multiple IP cores that support auto-upgrade, type the followingcommand:

quartus_sh –ip_upgrade –variation_files “<my_ip_filepath/my_ip1>.<hdl>; <my_ip_filepath/my_ip2>.<hdl>” <qii_project>

Example:quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.v;mega/pll3.v" hps_testx

Note: IP cores older than Quartus II software version 12.0 do not support upgrade.Altera verifies that the current version of the Quartus II software compiles theprevious version of each IP core. The Altera IP Release Notes reports any verifica‐tion exceptions for Altera IP cores. Altera does not verify compilation for IP coresolder than the previous two releases.

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Related InformationAltera IP Release Notes

Simulating Altera IP Cores in other EDA ToolsThe Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supportedEDA simulators. Simulation involves setting up your simulator working environment, compilingsimulation model libraries, and running your simulation.

You can use the functional simulation model and the testbench or example design generated with your IPcore for simulation. The functional simulation model and testbench files are generated in a projectsubdirectory. This directory may also include scripts to compile and run the testbench. For a complete listof models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.NativeLink launches your preferred simulator from within the Quartus II software.

Figure 7: Simulation in Quartus II Design Flow

Post-fit timing simulation netlist

Post-fit timing simulation (3)

Post-fit functional simulation netlist

Post-fit functional simulation

Analysis & Synthesis

Fitter(place-and-route)

TimeQuest Timing Analyzer

Device Programmer

Quartus II Design Flow Gate-Level Simulation

Post-synthesis functional

simulation

Post-synthesis functional simulation netlist

(Optional) Post-fit timing simulation

RTL Simulation

Design Entry(HDL, Qsys, DSP Builder)

Altera Simulation Models

EDA Netlist Writer

Note: Post-fit timing simulation is not supported for 28nm and later device archetectures. Altera IPsupports a variety of simulation models, including simulation-specific IP functional simulationmodels and encrypted RTL models, and plain text RTL models. These are all cycle-accuratemodels. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model isgenerated, and you can simulate that model. Use the simulation models only for simulation and

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not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctionaldesign.

Related InformationSimulating Altera Designs

Arria 10 DevicesThis section covers the remote system configuration modes, components, parameter, ports, andparameter settings for Arria® 10 devices.

Remote System Configuration ModeArria 10 devices support remote configuration mode only.

Remote configuration supports “Direct to application” and “Application to Application” update. Remoteconfiguration only supports 4-bytes address scheme so there is no support for devices with densitiessmaller than 128Mbit.

Figure 8: Transitions Between Factory and Application Configurations in Remote Update Mode

After POR ornCONFIG Assertion

Read Start Addressfrom Flash

Load ApplicationNumber POF

After POR ornCONFIG Assertion

Load Factory POF

Enter FactoryUser Mode

Enter ApplicationUser Mode

Reconfigurationor Start Address = 0

Reconfigurationor Start Address = 0

Reconfiguration & Start Address > 0 and not 32

Error Count > 3

WatchdogTimeout

Error Count <= 3

No Error

Factory Configuration Application Configuration

Reconfiguration &Start Address = 32

Reconfiguration &Start Address = 32

Reconfiguration &Start Address > 0

and not 32

When used with low-voltage quad-serial configuration (EPCQ-L) devices, the remote update mode allowsa configuration space to start at any flash sector boundary, allowing a maximum of 512 pages in theEPCQ-L256 device and 1024 pages in the EPCQ-L512 device, in which the minimum size of each page is512Kbits. Additionally, the remote update mode features a user watchdog timer that can detect functionalerrors in an application configuration.

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Remote System Configuration Components

Table 2: Remote System Configuration Components in Arria 10 Devices

Components Details

Page mode feature The dedicated 32-bit start address register PGM[31..0] holds the start address.

Factory configuration Factory configuration can be set as the default configuration setup depends onthe address pointer set.

The factory configuration loads into the device upon power-up.

If a system encounters an error while loading application configuration dataor if the device reconfigures due to nCONFIG assertion, the device loads thefactory configuration. The remote system configuration register determinesthe reason for factory configuration. Based on this information, the factoryconfiguration determines which application configuration to load.

Application configuration Application configuration can be the default configuration setup depends onthe address pointer set.

The application configuration loads into the device upon power-up.

The application configuration is the configuration data from a remote sourceand the data is stored in different locations or pages of the memory storagedevice, excluding the factory page.

Watchdog timer A watchdog timer is a circuit that determines the functionality of anothermechanism. The watchdog timer functions like a time delay relay that remainsin the reset state while an application runs properly.

Arria 10 devices are equipped with a built-in watchdog timer for remotesystem configuration to prevent a faulty application configuration fromindefinitely stalling the device.

The timer is a 29-bit counter, but you use only the upper 12 bits to set thevalue for the watchdog timer.

The timer begins counting after the device goes into user mode. If the applica‐tion configuration does not reset the user watchdog timer before time expires,the dedicated circuitry reconfigures the device with the factory configurationand resets the user watchdog timer.

To ensure the application configuration is valid, you must continuously resetthe watchdog reset_time within a specific duration during user modeoperation.

Remote update sub-block The remote update sub-block manages the remote configuration feature. Aremote configuration state machine controls this sub-block. This sub-blockgenerates the control signals required to control the various configurationregisters.

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Components Details

Remote configurationregisters

The remote configuration registers keep track of page addresses and the causeof configuration errors. You can control both the update and shift registers.The status and control registers are controlled by internal logic, but are readvia the shift register. The control register is 38-bit wide.

For details about configuration registers, refer to the Configuration, DesignSecurity, and Remote System Upgrades chapter in the respective devicehandbook.

Parameter Settings

Table 3: Altera Remote Update IP Core Parameters for Arria 10 Devices

GUI Name Legal Value in GUI Description

Which operation modewill you be using?

REMOTE Specifies the configuration mode of the ALTERAREMOTE UPDATE IP core.

Which configurationdevice will you be using?

EPCQ-L device Choose the configuration device you are using.

Add support for writingconfiguration parameters

— Enable this if you need to write configurationparameters.

Enable reconfig POFchecking

— Not available as it is not required

Ports

Table 4: Altera Remote Update IP Core Ports for Arria 10 Devices

Name Port Required? Description

read_param Input No Read signal for the parameter specified in param[]input port and fed to data_out[] output port.

Signal indicating the parameter specified on theparam[] port should be read. The number of bits seton data_out[] depends on the parameter type. Thesignal is sampled at the rising clock edge. Assert thesignal for only one clock cycle to prevent theparameter from being read again in a subsequentclock cycle.

The busy signal is activated as soon as read_param isread as active. While the parameter is being read, thebusy signal remains asserted, and data_out[] hasinvalid data. When the busy signal is deactivated,data_out[] is valid, another parameter can be read.

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write_param Input No Write signal for parameter specified in param[] andwith value specified in data_in[].

Signal indicating parameter specified with param[]should be written into remote update block with thevalue specified in data_in[]. The number of bitsread from data_in[] depends on the parameter type.

The signal is sampled at the rising clock edge. Thesignal should be asserted for only one clock cycle toprevent the parameter from being rewritten on asubsequent clock cycle. The busy signal is activated assoon as write_param is read as being active. Whilethe parameter is being written, the busy signalremains asserted, and input to data_ in[] is ignored.When the busy signal is deactivated, anotherparameter can be written. This signal is only valid inFactory configuration mode because parameterscannot be written in Application configuration mode.

The signal cannot be used in Local update mode.

param[] Input No Bus that specifies which parameter need to be read orupdated.

A 3-bit bus that selects the parameter to be read orupdated. If left unconnected, the default value for thisport is 000.

data_in[] Input No Data input for writing parameter data into the remoteupdate block. Input bus for parameter data.

For some parameters, not all bits are used. In thiscase, the lower-order bits are used (for example,status values use bits [4:0]).

If left unconnected, this bus defaults to 0. The port isignored if the current configuration is the Applicationconfiguration.

A 32-bit bus width(4-bytes addressing configurationdevice, for example EPCQ-L256) in the Quartus IIsoftware version 14.0 or later.

reconfig Input Yes Signal indicating that reconfiguration of the partshould begin using the current parameter settings. Avalue of 1 indicates reconfiguration should begin.This signal is ignored while busy is asserted to ensureall parameters are completely written before reconfi‐guration begins.

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reset_timer Input No Reset signal for watchdog timer.

Signal indicating the internal watchdog timer shouldbe reset. Unlike other inputs, this signal is notaffected by the busy signal and can reset the timereven when busy is asserted.

A falling edge of this signal triggers a reset of the userwatchdog timer.

This signal cannot be used in local update mode.

For the timing specification of this parameter, refer tothe specific device handbook.

clock Input Yes Clock input to the remote update block.

Clock input to control the machine and to drive theremote update block during the update of parameters.

This port must be connected to a valid clock.

reset Input Yes This is an active high signal. Asserting this signal highwill reset the IP core.

Asynchronous reset input to the IP core to initializethe machine to a valid state. The machine must bereset before first use, otherwise the state is notguaranteed to be valid.

busy Output No Busy signal that indicates when remote update blockis reading or writing data.

While this signal is asserted, the machine ignoresmost of its inputs and cannot be altered until themachine deasserts this signal. Therefore, changes aremade only when the machine is not busy.

This signal goes high when read_param or write_param is asserted, and remains high until the read orwrite operation completes.

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data_out[] Output No Data output when reading parameters.

This bus holds read parameter data from the remoteupdate block. The param[] value specifies theparameter to read.Whenthe read_param signal isasserted, the parameter value is loaded and driven onthis bus. Data is valid when the busy signal isdeasserted.

If left unconnected, the default value for the port is 0.

The width of this bus is device-dependent. For theQuartus II software version 14.0 and onwards, the buswidths is 32-bit bus width—using 4-byte addressingconfiguration device, for example EPCQL-256.

ctl_nupt Input Yes This port allows you to select which register to beread whenever read_param operation is running.

• A logic high will select the Control Register—register containing the current RU settings such aswatchdog timer settings, configuration mode(AnF) and page address.

• A logic low will select the Update Register—register containing similar data as held in ControlRegister, but the values is updated via write_param operation to be used in next reconfigura‐tion.

ParametersFor Arria 10 devices, mapping to each parameter type and corresponding parameter bit width is definedas follow:

Table 5: Parameter Type and Corresponding Parameter Bit Width Mapping

Bit Parameter Width Comments

000 Reconfiguration triggerconditions (Read Only) 5

• Bit 4—wdtimer_source: User Watchdog Timertimeout.

• Bit 3—nconfig_source: External configurationreset (nCONFIG) assertion.

• Bit 2—runconfig_source: Configuration resettriggered from logic array.

• Bit 1—nstatus_source: nSTATUS asserted by anexternal device as the result of an error.

• Bit 0—crcerror_source: CRC error duringapplication configuration

The POR value for all bits are 0.001 Illegal Value

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010 Watchdog Timeout Value 12 —011 Watchdog Enable 1 —100 Page Select 32 For the Quartus II software version 14.0 and onwards:

• Width of 32 when reading and writing the startaddress.

• For active serial devices using 32-bit addressing,such as EPCQL-256, PGM[31..2] corresponds tothe upper 30 bits of the 32-bits start address.PGM[1..0] is read as 2'b0.

101 Configuration Mode (AnF) 1 In local update mode, this parameter can only be read.This parameter is set to 1 in application page and is setto 0 in factory page. In remote update mode, thisparameter can be read and written.

Before loading the application page in remote updatemode, Altera recommends that you set this parameterto 1. The content of the control register cannot be readproperly if you fail to do so.

110 Illegal Value111 Illegal Value

Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V DevicesThis section covers the remote system configuration modes, components, parameter, ports, andparameter settings for Arria II, Arria V, Cyclone® V, Stratix® IV, and Stratix V devices.

Remote System Configuration ModeArria II, Arria V, Cyclone V, Stratix IV, and Stratix V devices support remote configuration mode only.

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Remote Configuration Mode

Figure 9: Remote Configuration Mode

Power Up Set Control Registerand Reconfigure

Reload a Different Application


Set Control Registerand Reconfigure

Configuration Error

Configuration Error

Configuration Error

Application 1Configuration

Application nConfiguration

FactoryConfiguration

(page 0)

When used with serial configuration (EPCS) or quad-serial configuration (EPCQ) devices, the remoteupdate mode allows a configuration space to start at any flash sector boundary, allowing a maximum of128 pages in the EPCS64 device and 32 pages in the EPCS16 device, in which the minimum size of eachpage is 512Kbits. Additionally, the remote update mode features a user watchdog timer that can detectfunctional errors in an application configuration.


Table 6: Remote System Configuration Components in Arria II, Arria V, Cyclone V, Stratix IV, and Stratix VDevices

Components Details

Page mode feature The dedicated 24-bit start address register PGM[23..0] holds the startaddress.

Factory configuration Factory configuration is the default configuration setup.

In remote configuration mode, the factory configuration loads into thedevice upon power-up.

If a system encounters an error while loading application configurationdata or if the device reconfigures due to nCONFIG assertion, the deviceloads the factory configuration. The remote system configurationregister determines the reason for factory configuration. Based on thisinformation, the factory configuration determines which applicationconfiguration to load.

Application configuration The application configuration is the configuration data from a remotesource and the data is stored in different locations or pages of thememory storage device, excluding the factory default page.


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Components Details

Watchdog timer A watchdog timer is a circuit that determines the functionality ofanother mechanism. The watchdog timer functions like a time delayrelay that remains in the reset state while an application runs properly.

Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V devices areequipped with a built-in watchdog timer for remote system configura‐tion to prevent a faulty application configuration from indefinitelystalling the device.

The timer is a 29-bit counter, but you use only the upper 12 bits to setthe value for the watchdog timer.

The timer begins counting after the device goes into user mode. If theapplication configuration does not reset the user watchdog timerbefore time expires, the dedicated circuitry reconfigures the devicewith the factory configuration and resets the user watchdog timer.

To ensure the application configuration is valid, you must continu‐ously reset the watchdog reset_time within a specific duration duringuser mode operation.

Remote update sub-block The remote update sub-block manages the remote configurationfeature. A remote configuration state machine controls this sub-block.This sub-block generates the control signals required to control thevarious configuration registers.

Remote configuration registers The remote configuration registers keep track of page addresses andthe cause of configuration errors. You can control both the update andshift registers. The status and control registers are controlled byinternal logic, but are read via the shift register. The control register is38-bit wide.

For details about configuration registers, refer to the Configuration,Design Security, and Remote System Upgrades chapter in therespective device handbook.

Parameter Settings

Table 7: Altera Remote Update IP Core Parameters for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix VDevices



REMOTE Specifies the configuration mode.


• EPCS device• EPCQ device

Choose the configuration device you are using.



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— Allows you to enable .pof checking, which allows theremote update block to verify the existence of anapplication configuration image before the image isloaded. When you turn on this parameter, the AlteraRemote Update IP core checks the .pof and sends thereconfig signal. This option is disabled by default.

POF checking feature detect and verify the existence of an application configuration image before theimage is loaded. Loading an invalid application configuration image may lead to unexpected behaviour ofthe FPGA including system failure. Example of invalid application configuration images are:

• A partially programmed application image• A blank application image• An application image assigned with a wrong start address

Ports

Table 8: Altera Remote Update IP Core Ports for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices

Name Port Required?

Description

read_param Input No Read signal for the parameter specified inparam[] input port and fed to data_out[]output port.

Signal indicating the parameter specified on theparam[] port should be read. The number of bitsset on data_out[] depends on the parametertype. The signal is sampled at the rising clockedge. Assert the signal for only one clock cycle toprevent the parameter from being read again in asubsequent clock cycle.

The busy signal is activated as soon as read_param is read as active. While the parameter isbeing read, the busy signal remains asserted, anddata_out[] has invalid data. When the busysignal is deactivated, data_out[] is valid,another parameter can be read.

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Name Port Required?

Description

write_param Input No Write signal for parameter specified in param[]and with value specified in data_in[].

Signal indicating parameter specified withparam[] should be written into remote updateblock with the value specified in data_in[]. Thenumber of bits read from data_in[] depends onthe parameter type.

The signal is sampled at the rising clock edge.The signal should be asserted for only one clockcycle to prevent the parameter from beingrewritten on a subsequent clock cycle. The busysignal is activated as soon as write_param is readas being active. While the parameter is beingwritten, the busy signal remains asserted, andinput to data_in[] is ignored. When the busysignal is deactivated, another parameter can bewritten. This signal is only valid in Factoryconfiguration mode because parameters cannotbe written in Application configuration mode.

The signal cannot be used in Local update mode.

param[] Input No Bus that specifies which parameter need to beread or updated.

A 3-bit bus that selects the parameter to be reador updated. If left unconnected, the default valuefor this port is 000.

For more information, refer to Parameters onpage 23.

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Name Port Required?

Description

data_in[] Input No Data input for writing parameter data into theremote update block. Input bus for parameterdata.


If left unconnected, this bus defaults to 0. Theport is ignored if the current configuration is theApplication configuration.

A 24-bit bus width in the Quartus II softwareversion 13.0 or earlier. For the Quartus IIsoftware version 13.1 and onwards, the buswidths are as follow:

• 24-bit bus width—using 3-byte addressingconfiguration device, for example EPCS128.

• 32-bit bus width—using 4-byte addressingconfiguration device, for example EPCQ256.

reconfig Input Yes Signal indicating that reconfiguration of the partshould begin using the current parametersettings. A value of 1 indicates reconfigurationshould begin. This signal is ignored while busy isasserted to ensure all parameters are completelywritten before reconfiguration begins.


Signal indicating the internal watchdog timershould be reset. Unlike other inputs, this signal isnot affected by the busy signal and can reset thetimer even when busy is asserted.

A falling edge of this signal triggers a reset of theuser watchdog timer.


For the timing specification of this parameter,refer to the specific device handbook.


Clock input to control the machine and to drivethe remote update block during the update ofparameters.


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Name Port Required?

Description

reset Input Yes This is an active high signal. Asserting this signalhigh will reset the IP core.

Asynchronous reset input to the IP core toinitialize the machine to a valid state. Themachine must be reset before first use, otherwisethe state is not guaranteed to be valid.

busy Output No Busy signal that indicates when remote updateblock is reading or writing data.

While this signal is asserted, the machine ignoresmost of its inputs and cannot be altered until themachine deasserts this signal. Therefore, changesare made only when the machine is not busy.

This signal goes high when read_param orwrite_param is asserted, and remains high untilthe read or write operation completes.


This bus holds read parameter data from theremote update block. The param[] valuespecifies the parameter to read. When the read_param signal is asserted, the parameter value isloaded and driven on this bus. Data is valid whenthe busy signal is deasserted.

If left unconnected, the default value for the portis 0. The width of this bus is device-dependent:




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Name Port Required?

Description

asmi_busy Input No Input from the altasmi_parallel component.

Available when the check_app_pof parameter isset to true.

A logic high on this pin indicates that theALTASMI_PARALLEL IP core is busyprocessing the operation. The Altera RemoteUpdate IP core waits for this pin to go low beforeinitiating another operation.

Wire this pin to the asmi_busy output port ofthe ALTASMI_PARALLEL IP core.

asmi_data_valid Input No Input from the altasmi_parallel component.


A logic high on this pin indicates valid data inthe asmi_dataout[7..0] output port of theALTASMI_PARALLEL IP core.

Wire this pin to the asmi_data_valid outputport of the ALTASMI_PARALLEL IP core.

asmi_dataout Input No Input from the altasmi_parallel component.


The Altera Remote Update IP core presents theaddress information on this pin before initiatingthe read operation on the ALTASMI_PARALLEL IP core.

pof_error Output No Detects and invalid application configurationimage.

Available when the check_app_pof parameter isset to TRUE.

A logic high on this pin indicates that the AlteraRemote Update IP core detects an invalidapplication configuration image. If asserted high,you must take corrective action by reloading anew application configuration image orspecifying a different address location in theEPCS or EPCQ that contains a valid applicationconfiguration image. Wire this pin based on yoursystem requirement.

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Name Port Required?

Description

asmi_addr Output No Address signal to altasmi_parallelcomponent.

Available when the check_app_pof parameter isset to TRUE. The Altera Remote Update IP corepresents the address information on this pinbefore initiating the read operation on theALTASMI_PARALLEL IP core.

asmi_read Output No Read signal to altasmi_parallel component.

Available when the check_app_pof parameter isset to TRUE. A logic high on this pin initiates theread operation on the ALTASMI_PARALLEL IPcore.

Wire this pin to the asmi_read input port of theALTASMI_PARALLEL IP core.

asmi_rden Output No Read enable signal to altasmi_parallelcomponent.

Available when the check_app_pof parameter isset to TRUE. This pin enables the read operationon the ALTASMI_PARALLEL IP core.

Wire this pin to the asmi_rden input port of theALTASMI_PARALLEL IP core.

ParametersFor Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V devices, mapping to each parameter type andcorresponding parameter bit width is defined as follow:

Table 9: Parameter Type and Corresponding Parameter Bit Width Mapping


000 Reconfiguration triggerconditions (Read Only) 5

• Bit 4—wdtimer_source: User Watchdog Timertimeout.

• Bit 3—nconfig_source: External configurationreset (nCONFIG) assertion.

• Bit 2—runconfig_source: Configuration resettriggered from logic array.

• Bit 1—nstatus_source: nSTATUS asserted by anexternal device as the result of an error

• Bit 0—crcerror_source: CRC error duringapplication configuration

The POR value for all bits are 0.

001 Illegal Value

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010 Watchdog Timeout Value 12 —011 Watchdog Enable 1 —100 Page Select 24 or 32 For the Quartus II software version 13.1 and onwards:

• Width of 24 or 32 when reading and writing thestart address.

• For active serial devices using 24-bit addressing,such as EPCS128 or EPCQ128, PGM[23..2]corresponds to the upper 22 bits of the 24-bits startaddress. PGM[1..0] is read as 2'b0.

• For active serial devices using 32-bit addressing,such as EPCQ256, PGM[31..2] corresponds to theupper 30 bits of the 32-bits start address.PGM[1..0] is read as 2'b0.

For the Quartus II software version 13.0 and earlier:

• Width of 24 when reading and writing the startaddress.

• For Arria II, Stratix III, and Stratix IV devices,PGM[23..0] form the 24-bit start address.

• For Arria V, Cyclone V, and Stratix V devices, ifyou use active serial devices using 24-bitaddressing, such as EPCS128 or EPCQ128,PGM[23..0] corresponds to the 24 bits of the startaddress. If you use active serial devices using 32-bitaddressing, such as EPCQ256, PGM[23..0]corresponds to the 24 MSB of the start address,thus the 32 bits start address is PGM[23..0],8'b0.

101 Configuration Mode (AnF) 1 In local update mode, this parameter can only be read.This parameter is set to 1 in application page and is setto 0 in factory page. In remote update mode, thisparameter can be read and written.

Before loading the application page in remote updatemode, Altera recommends that you set this parameterto 1. The content of the control register cannot be readproperly if you fail to do so.

110 Illegal Value111 Illegal Value

Cyclone III and Cyclone IV DevicesThis section covers the remote system configuration modes, components, parameters, ports, and remoteupdate operation for Cyclone III and Cyclone IV devices.

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Remote System Configuration ModeCyclone IV devices support remote configuration mode only.

Remote Configuration Mode

Figure 10: Remote Configuration Mode

Power Up Set Control Registerand Reconfigure



Set Control Registerand Reconfigure

Configuration Error

Configuration Error

Configuration Error


Application nConfiguration


(page 0)

Cyclone IV E devices support the active parallel (AP) configuration scheme for Altera devices.

When used with EPCS or EPCQ devices, the remote update mode allows a configuration space to start atany flash sector boundary, allowing a maximum of 128 pages in the EPCS64 device and 32 pages in theEPCS16 device, in which the minimum size of each page is 512Kbits. Additionally, the remote updatemode features a user watchdog timer that can detect functional errors in an application configuration.


Table 10: Remote System Configuration Components in Cyclone IV Devices

Components Details

Page mode feature For both AS and AP configurations, Cyclone IV devices use a 24-bitboot start address in which you set the most significant 22 bits. Cyclonedevices do not support pgmout ports.

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Components Details

Factory configuration Factory configuration is the default configuration setup.

In remote configuration mode, the factory configuration loads intoCyclone III and Cyclone IV devices upon power-up.

If a system encounters an error while loading application configurationdata or if the device reconfigures due to nCONFIG assertion, the deviceloads the factory configuration. The remote system configurationregister determines the reason for factory configuration. Based on thisinformation, the factory configuration determines which applicationconfiguration to load.

Upon power-up in remote update in the AP configuration scheme,Cyclone III and Cyclone IV devices load the default factory configura‐tion located at the following address:

boot_address[23:0] = 24'h010000 = 24'b1 0000 0000 0000

0000.

You can change the default factory configuration address to anyaddress using the APFC_BOOT_ADDR JTAG instruction. The factoryimage is stored in non-volatile memory and is never updated ormodified using remote access. This corresponds to the default startaddress location 0x010000 (or the updated address if the defaultaddress is changed) in the supported parallel flash memory. Note that0x010000 is the 16-bit word address for the AP flash memory.However, the Quartus II software implements 8-bit byte addressing.Therefore, the correct Quartus II software setting for this address is0x020000.

Application configuration The application configuration is the configuration data from a remotesource and the data is stored in different locations or pages of thememory storage device, excluding the factory default page.


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Components Details

Watchdog timer A watchdog timer is a circuit that determines the functionality ofanother mechanism. The watchdog timer functions like a time delayrelay that remains in the reset state while an application runs properly.

Cyclone IV devices are equipped with a built-in watchdog timer forremote system configuration to prevent a faulty application configura‐tion from indefinitely stalling the device.

The timer is a 29-bit counter, but you use only the upper 12 bits to setthe value for the watchdog timer.

The timer begins counting after the device goes into user mode. If theapplication configuration does not reset the user watchdog timerbefore time expires, the dedicated circuitry reconfigures the devicewith the factory configuration and resets the user watchdog timer.

To ensure the application configuration is valid, you must continu‐ously reset the watchdog reset_time within a specific duration duringuser mode operation.

Remote update sub-block The remote update sub-block manages the remote configurationfeature. A remote configuration state machine controls this sub-block.This sub-block generates the control signals required to control thevarious configuration registers.

Remote configuration registers The remote configuration registers keep track of page addresses andthe cause of configuration errors. You can control both the update andshift registers. The status and control registers are controlled byinternal logic, but are read via the shift register.

For Cyclone IV devices, the remote system upgrade status register hasadditional capabilities. Three sets of registers store the status for thecurrent application configuration and the two previous applicationconfigurations.

For details about configuration registers, refer to the Configuration,Design Security, and Remote System Upgrades chapter in therespective device handbook.

Parameter Settings

Table 11: Altera Remote Update IP core Parameters for Cyclone IV Devices



REMOTE Specifies the configuration mode of the Altera RemoteUpdate IP core.



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• EPCS device• EPCQ device

Choose the configuration device that you are using.




— Allows you to enable .pof checking, which allows theremote update block to verify the existence of anapplication configuration image before the image isloaded. When you turn on this parameter, the AlteraRemote Update IP core checks the .pof and sends thereconfig signal. This option is disabled by default.

Ports

Table 12: Altera Remote Update IP Core Ports for Cyclone IV Devices

Name Port Required?

Description

read_param Input No Read signal for the parameter specified inparam[] input port and fed to data_out[]output port.

Signal indicating the parameter specified on theparam[] port should be read. The number of bitsset on data_out[] depends on the parametertype. The signal is sampled at the rising clockedge. Assert the signal for only one clock cycle toprevent the parameter from being read again in asubsequent clock cycle.

The busy signal is activated as soon as read_param is read as active. While the parameter isbeing read, the busy signal remains asserted, anddata_out[] has invalid data. When the busysignal is deactivated, data_out[] is valid,another parameter can be read.

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Name Port Required?

Description

write_param Input No Write signal for parameter specified in param[]and with value specified in data_in[].

Signal indicating parameter specified withparam[] should be written into remote updateblock with the value specified in data_in[]. Thenumber of bits read from data_in[] depends onthe parameter type.

The signal is sampled at the rising clock edge.The signal should be asserted for only one clockcycle to prevent the parameter from beingrewritten on a subsequent clock cycle. The busysignal is activated as soon as write_param is readas being active. While the parameter is beingwritten, the busy signal remains asserted, andinput to data_in[] is ignored. When the busysignal is deactivated, another parameter can bewritten. This signal is only valid in Factoryconfiguration mode because parameters cannotbe written in Application configuration mode.

The signal cannot be used in local update mode.

param[] Input No Bus that specifies which parameter need to beread or updated.

A 3-bit bus that selects the parameter to be reador updated. If left unconnected, the default valuefor this port is 000.

For more information, refer to Parameters onpage 34.

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Name Port Required?

Description

data_in[] Input No Data input for writing parameter data into theremote update block. Input bus for parameterdata.


If left unconnected, this bus defaults to 0. Theport is ignored if the current configuration is theApplication configuration.




reconfig Input Yes Signal indicating that reconfiguration of the partshould begin using the current parametersettings. A value of 1 indicates reconfigurationshould begin. This signal is ignored while busy isasserted to ensure all parameters are completelywritten before reconfiguration begins.


Signal indicating the internal watchdog timershould be reset. Unlike other inputs, this signal isnot affected by the busy signal and can reset thetimer even when busy is asserted.

A falling edge of this signal triggers a reset of theuser watchdog timer.


For the timing specification of this parameter,refer to the specific device handbook.

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Name Port Required?

Description

read_source Input Yes Specifies whether a parameter value is read fromthe current or a previous state.

This 2-bit port specifies the state from which aparameter value is read. This signal is valid onlywhen the read_param signal is valid.

Mapping read_source[1..0] to Selected Sourceis defined as follow:

• 00 - Current State Content in Status Register• 01 - Previous State Register 1 Content in

Status Register• 10 - Previous State Register 2 Content in

Status Register• 11 - Value in Input Register

For details, refer to the Configuration, DesignSecurity, and Remote System Upgrades chapterin the respective device handbook.


Clock input to control the machine and to drivethe remote update block during the update ofparameters.


reset Input Yes This is an active high signal. Asserting this signalhigh will reset the IP core.

Asynchronous reset input to the IP core toinitialize the machine to a valid state. Themachine must be reset before first use, otherwisethe state is not guaranteed to be valid.

busy Output No Busy signal that indicates when remote updateblock is reading or writing data.

While this signal is asserted, the machine ignoresmost of its inputs and cannot be altered until themachine deasserts this signal. Therefore, changesare made only when the machine is not busy.

This signal goes high when read_param orwrite_param is asserted, and remains high untilthe read or write operation completes.

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Name Port Required?

Description


This bus holds read parameter data from theremote update block. The param[] valuespecifies the parameter to read. When the read_param signal is asserted, the parameter value isloaded and driven on this bus. Data is valid whenthe busy signal is deasserted.

If left unconnected, the default value for the portis 000. The width of this bus is device-dependent:




asmi_busy Input No Input from the altasmi_parallel component.


A logic high on this pin indicates that theALTASMI_PARALLEL IP core is busyprocessing the operation. The Altera RemoteUpdate IP core waits for this pin to go low beforeinitiating another operation.

Wire this pin to the asmi_busy output port ofthe ALTASMI_PARALLEL IP core.

asmi_data_valid Input No Input from the altasmi_parallel component.


A logic high on this pin indicates valid data inthe asmi_dataout[7..0] output port of theALTASMI_PARALLEL IP core.

Wire this pin to the asmi_data_valid outputport of the ALTASMI_PARALLEL IP core.

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Name Port Required?

Description

asmi_dataout Input No Input from the altasmi_parallel component.


The Altera Remote Update IP core presents theaddress information on this pin before initiatingthe read operation on the ALTASMI_PARALLEL IP core.

pof_error Output No Detects and invalid application configurationimage.

Available when the check_app_pof parameter isset to TRUE.

A logic high on this pin indicates that the AlteraRemote Update IP core detects an invalidapplication configuration image. If asserted high,you must take corrective action by reloading anew application configuration image orspecifying a different address location in theEPCS or EPCQ that contains a valid applicationconfiguration image. Wire this pin based on yoursystem requirement.

asmi_addr Output No Address signal to altasmi_parallelcomponent.

Available when the check_app_pof parameter isset to TRUE. The Altera Remote Update IP corepresents the address information on this pinbefore initiating the read operation on theALTASMI_PARALLEL IP core.

Wire this pin to the asmi_addr input port of theALTASMI_PARALLEL IP core.

asmi_read Output No Read signal to altasmi_parallel component.

Available when the check_app_pof parameter isset to TRUE. A logic high on this pin initiates theread operation on the ALTASMI_PARALLEL IPcore.

Wire this pin to the asmi_read input port of theALTASMI_PARALLEL IP core.

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Name Port Required?

Description

asmi_rden Output No Read enable signal to altasmi_parallelcomponent.

Available when the check_app_pof parameter isset to TRUE. This pin enables the read operationon the ALTASMI_PARALLEL IP core.

Wire this pin to the asmi_rden input port of theALTASMI_PARALLEL IP core.

ParametersFor Cyclone IV devices, mapping to each parameter type and corresponding parameter bit width isdefined as follow:

Table 13: Mapping to Each Parameter Type and Corresponding Parameter Bit Width


000 Master State MachineCurrent State Mode (ReadOnly)

2 00—Factory mode.

01—Application mode.

11—Application mode with the master state machineuser watchdog timer enabled.

001 Force early CONF_DONE(cd_early) check

1 —

010 Watchdog Timeout Value

12 Width of 12 when writing.

The 12 bits for writing are the upper 12 bits of the 29-bit Watchdog Timeout Value

29 Width of 29 when reading.011 Watchdog Enable 1 —

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100 Boot Address — For the Quartus II software version 13.1 andonwards:

• Width of 29 or 32 when reading the boot address.• Width of 24 or 32 when writing the boot address.• For active serial devices using the 24-bit

addressing, such as EPCS128 or EPCQ128, boot_address[23..2] corresponds to the upper 22 bitsof the 24-bits boot address. boot_address[1..0]is read as 2'b0.

• For active serial devices using the 32-bitaddressing, such as EPCQ256, boot_address[31..2] corresponds to the upper 30 bitsof the 32-bits boot address. boot_address[1..0]is read as 2'b0.

For the Quartus II software version 13.0 or earlier:

• Width of 24 when reading the boot address.• Width of 22 when writing the boot address.• Writes the boot address to the upper 22 bits of the

24-bits boot address.

101 Illegal Value110 Force the internal oscillator

as startup state machineclock (osc_int) option bit

1 —

111 Reconfiguration triggerconditions (Read Only)

5 Bit 4 (nconfig_source)—external configuration reset(nconfig) assertion.

Bit 3 (crcerror_source)—CRC error duringapplication configuration.

Bit 2 (nstatus_source)—nstatus asserted by anexternal device as the result of an error.

Bit 1 (wdtimer_source)—User watchdog timertimeout.

Bit 0 (runconfig_source)—Configuration resettriggered from logic array.

Remote Update OperationNote: read_source specifies whether a parameter value is read from the current or a previous state. For

more information, refer to Table 14.

Note: Perform remote update operations in the corresponding master state machine (MSM) mode.

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read_para

m

write_

param

read_source param Remote Update Operation data_outwidth(bits)

MSM Mode

1 0 [00] [000] Master State Machine Current State Mode(Read Only)

• 00—Factory mode• 01—Application mode• 11—Application mode with Master State

Machine User Watchdog Timer Enabled

2 Factory orApplication

1 0 [00] [100] Read factory boot address 24 Factory

1 0 [01] [100] Read Past Status 1 boot address.

For more information, refer to Figure 11.

24 Factory

1 0 [01] [111] Read Past Status 1 reconfiguration triggercondition source.


5 Factory

1 0 [10] [100] Read Past Status 2 boot address.


24 Factory

1 0 [10] [111] Read Past Status 2 reconfiguration triggercondition source


5 Factory

1 0 [01] [010] Read current application mode watchdogvalue

29 Application

1 0 [01] [011] Read current application mode watchdogenable

1 Application

1 0 [10] [100] Read current application mode boot address 24 Application

0 1 [00] [001] Write the early confdone check bit.

All parameters can be written in factorymode only.

1 Factory

0 1 [00] [010] Write the watchdog time-out value.


12 Factory

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read_para

m

write_

param

read_source param Remote Update Operation data_outwidth(bits)

MSM Mode

0 1 [00] [011] Write the watchdog enable bit.


1 Factory

0 1 [00] [100] Write application boot address.


22 Factory

0 1 [00] [110] Write to force the internal oscillator asstartup state machine clock. All parameterscan be written in factory mode only.

1 Factory

1 0 [11] [001] Read the early confdone check bits 1 Factory

1 0 [11] [010] Read watchdog time-out value 12 Factory

1 0 [11] [011] Read watchdog enable bit 1 Factory

1 0 [11] [100] Read boot address 22 Factory

1 0 [11] [110] Read to check whether the internal oscillatoris set as startup state machine clock

1 Factory

read_source

The following table lists the details for read_source. read_source specifies whether a parameter value isread from the current or a previous state. When you trigger the read operation, all contents in statusregister or input register latched to the data_out node in the Altera Remote Update IP core.

Table 14: read_source

read_source Description

00 Current state contents in status register01 Previous state register 1 contents in status register10 Previous state register 2 contents in status register11 Current contents is in input register

State Register

The previous state register 1 reflects the current application configuration and the previous state register 2reflects the previous application configuration.

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Figure 11: State Register




Configured the Application 1from Factory

Switched to Application 2

Back to factory(State register 1 reflects to current application which is application 1)

Back to factory(State register 1 reflects to current application which is application 2, whilethe state register 2 is reflects to previous application which is application 1)

Design Example: Factory Image and Application Image ProgrammingSequence

This design example illustrates the sequence of programming the Factory Image and Application Imageby using the programmer in Quartus II.

In this example, you will be perform the following activities:

• Generate both SRAM object file (.sof) for Application Image and Factory Image.• Convert Programming file to generate the JTAG indirect configuration file (.jic)• Program the .jic file into the FPGA

The following instructions guide you to perform the design example tasks:

1. Unzip the contents of the RSU.zip file to your working directory on your PC.2. In the Quartus II software, click Open Project in the File menu,3. Compile Application Image:

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a. Browse to the folder in which you unzipped the files and open the Application_Image.qpf.b. Click Yes in the message box "Do you want to overwrite the database for C:/your working

directory/Application_Image.qpf created by Quatus II 64-Bit Version 13.0.a Build 232 Service Pack1 SJ Full version?"

c. On the Processing menu, choose Start Compilation.d. Click OK when the full compilation successful dialog box appears.e. Application_Image.sof will be generated in c:\your working directory\output_files.f. Click close project in the file menu.

4. 4. Compile Factory Image:

a. Browse to the folder in which you unzipped the files and open the SVRSU.qpf.b. Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/

Application_Image.qpf created by Quatus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Fullversion?"

c. Choose Start Compilation on the Processing menu.d. Click OK when the full compilation successful dialog box appears.e. Factory_Image.sof will be generated in c:\your working directory\output_files.

5. On the File Menu, click Convert Programming Files and select the detail as shown below:

• Programming File type: JTAG Indirect Configuration File (.jic)• Select Configuration Device: EPCQ 128• Mode: Active Serial x4• File name: c:/your working directory/output_file.jic

• Flash loader: click add device and choose 5CEFA7ES• SOFT DATA PAGE_0: click Add File and select the factory image file (SVRSU.sof)• SOFT DATA PAGE_0: click Add File and select the Application image file (Application_Image.sof)• Click Generate.• Click OK when the dialogue box of .jic file successfully generated appears.

6. On the Tool Menu, click Programmer:

a. Make sure the board is power up and the USB Blaster is connected between computer and theboard. This design example uses USB Blaster and JTAG mode.

b. Click Auto Detect.c. Right click on the 5CEFA7ES and select change file.d. Browse to the output_file.jic that was generated in previous steps.e. Tick the Program/Configure checkbox and click Start.f. Configuration successful indicates the FPGA is configured successfully.

Document Revision HistoryThe following table lists the revision history.

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Table 15: Document Revision History

Date Version Changes

January 2015 2015.01.23 Updated Arria 10 remote system configuration mode flowdiagram.

December 2014 2014.12.15 • Updated POF checking feature description and invalidconfiguration image examples.

• Added Arria 10 device support with descriptions, portsand parameters.

• Replaced outdated design examples with a currentapplication design example.

June 2014 2014.06.30 • Replaced MegaWizard Plug-In Manager informationwith IP Catalog.

• Added standard information about upgrading IP cores.• Added standard installation and licensing information.• Removed outdated device support level information. IP

core device support is now available in IP Catalog andparameter editor.

• Added a note to recommend users to use 20–MHzfMAX for all devices.

May 2014 2014.05.13 • Updated the Device Support section to includeinformation on device families that will be phased outfrom Quartus II software version 13.1 and Quartus IIsoftware version 14.0.

• Rearranged content for remote system configurationmodes, remote system configuration components,parameter settings, ports, param for each group ofdevices. Refer to Device Support section for moreinformation.

August 2013 2013.08.16 Added Cyclone IV devices support for Active SerialRemote Configuration Mode in Parameters, Output Ports,and Active Serial Remote Configuration Mode.

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July 2013 2013.07.12 • Updated Watchdog Timer to include the watchdogreset_time requirement to ensure the validity of theapplication configuration. Listed the supported devicesfor the watchdog timer feature.

• Updated Device Support section.• Added Active Serial Remote Configuration Mode to

clarify that the active serial configuration mode is asubset of the remote configuration mode. Also clarifiedthat this mode is only available for EPCS devices.

• Added a link to the Configuration Handbook in theRemote System Configuration Modes.

• Updated Remote Configuration Mode to add thatCyclone IV E devices support AP configurationscheme and included a link to the Configuration andRemote System Upgrades in Cyclone IV Deviceschapter.

• Updated Remote System Configuration Componentsto clarify that the local configuration mode does notsupport the user watchdog timer feature.

• Included a cross-reference to the Input Port in PageMode Feature.

• Updated Parameters to update values and supporteddevices of the GUI parameter settings.

• Updated Factory Configuration to clarify that thedefault factory configuration address does not applyfor Cyclone V devices.



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July 2013 2013.07.12 • Added Cyclone III and Cyclone IV Devices RemoteUpdate Operation.

• Updated Input Ports to include Arria V and Cyclone Vsupport for data_in[] port.

• Added Param[] as a standalone section.• Updated Parameter Type and Corresponding

Parameter Bit Width Mapping to include Arria V andCyclone V support for Reconfiguration triggerconditions parameter. Also updated Page Selectparameter to include information for Arria V, CycloneV, and Stratix V devices.

• Updated Parameter Type and CorrespondingParameter Bit Width Mapping to update the Configu‐ration Mode (AnF) information.

• Updated Input Ports to add a link to the Configura‐tion, Design Security, and Remote Upgrades in theCyclone III Device Family chapter.

• Updated Input Ports to clarify that a falling edge of thereset_timer signal triggers a reset of the userwatchdog timer.

• Updated Output Ports to add Arria II, Arria V,Cyclone V, Stratix IV, and Stratix V device support for24-bit bus for data_out[] port.

• Added Knowledge Base section.• Added Simulation to clarify that simulation capability

are for Arria GX, Stratix, and Stratix II devices only.

February 2012 3.0 Add Cyclone IV support for param[] parameter.

August 2010 2.5 Updated for Quartus II software v10.0, including:

• Updated the Device Family Support section.• Add Parameters table to Specifications chapter.• Added new parameters and ports to Specifications

chapter.• Added new prototypes and declarations sections to

Specifications chapter.• Updated design example figures and steps.

April 2009 2.4 Updated for Quartus II software v9.0, including:

• Updated the section.• Added the Maximum Clock Frequency (fMAX) for the

supported devices.• Updated ports and parameter tables.

42 Document Revision HistoryUG-31005

2015.01.23


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May 2007 2.3 Updated for Quartus II software v7.1, including:

• Updated to include support for Arria GX devices.• Updated to include Cyclone III device information.• Added Referenced Documents section.

March 2007 2.2 Updated Chapter 1 to include Cyclone III support.

December 2006 2.1 Updated Chapter 1 to include Stratix III support.

September 2006 2.0 General update for Quartus II software version 6.0,including screenshots; added ModelSim®-Alterasimulation tool section to Chapter 3.

March 2005 1.0 Initial release.



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