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Altera Altera Technical Technical Solutions Solutions Seminar Seminar 2000 2000

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Page 1: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Altera Altera Technical Technical Solutions Solutions SeminarSeminar

20002000

Page 2: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

ScheduleSchedule Opening Opening

Introduction Introduction

FLEXFLEX®® 10KE Devices 10KE Devices

APEXAPEX™™ 20K & Quartus 20K & Quartus™™OverviewOverview

Design Integration Design Integration

EDA IntegrationEDA Integration

Intellectual PropertyIntellectual Property

Design IterationDesign Iteration

Design OptimizationDesign Optimization

Internet InterfaceInternet Interface

RoadmapRoadmap

Quartus Demo Quartus Demo

Page 3: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

AgendaAgenda

IntroductionIntroduction

FLEXFLEX®® 10KE Devices 10KE Devices

APEXAPEX™™ 20K & 20K & QuartusQuartus™™OverviewOverview

Design IntegrationDesign Integration

EDA IntegrationEDA Integration

Intellectual PropertyIntellectual Property

Design IterationDesign Iteration

Design OptimizationDesign Optimization

Internet InterfaceInternet Interface

RoadmapRoadmap

u Incremental Compilation

u SignalTap™ Logic Analysis

u SameFrame™ Pin-Out

Page 4: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Easy-to-Use Verification ToolsEasy-to-Use Verification Tools

Integrated HDL Simulator for Verifying Integrated HDL Simulator for Verifying Code Before CompilationCode Before Compilation

Integrated Gate-Level and Timing-Level Integrated Gate-Level and Timing-Level SimulationSimulation

Nodes Automatically Located in Source Nodes Automatically Located in Source CodeCode

Easy Integration with Third-Party Easy Integration with Third-Party Verification ToolsVerification Tools

Page 5: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Project Root

A B

D E

G H

C

F

HDLSimulator

Compiler

Timing & BoardVerification

Incremental RecompilationIncremental Recompilation

Page 6: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

SignalTap™ Logic AnalysisSignalTap™ Logic Analysis

APEX

Embedded Logic Analysis

Communication CableCommunication Cable

QuartusQuartus

Page 7: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Debugging Internal LogicDebugging Internal Logic

EmbeddedLogic

Analyzer

CPUCPUDesignDesignBlockBlock

DesignDesignBlockBlockPCIPCI

Page 8: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Embedded Logic AnalyzerEmbedded Logic Analyzer

Parameterized MegafunctionParameterized Megafunction Integrated with QuartusIntegrated with Quartus

Signal Selection Signal Selection Trigger Setup Trigger Setup Run ControlRun ControlWaveform DisplayWaveform Display

Operates at System SpeedOperates at System Speed

Page 9: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Memory UsageMemory Usage

11

22

44

88

1616

3232

6464

128128

11

11

22

44

88

1616

3232

6464

11

11

11

22

44

88

1616

3232

11

11

11

11

22

44

88

1616

11

11

11

11

11

22

44

88

2,0482,0481,0241,024512512256256128128

11

22

44

88

1616

3232

6464

128128

Ch

an

nels

Ch

an

nels

Memory Depth - SamplesMemory Depth - Samples

DeviceDevice

EP20K10EP20K1000

EP20K16EP20K1600

EP20K20EP20K2000

EP20K30EP20K3000

EP20K40EP20K4000

EP20K60EP20K6000

EP20K10EP20K100000

ESBsESBs

2626

4040

5252

7272

104104

152152

264264

............

Page 10: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

SignalTap PlusSignalTap Plus

Page 11: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

SignalTap Plus System AnalyzerSignalTap Plus System Analyzer

JTA

G

Internal Chip-level

Activity

ExternalBoard-level

Activity SystemCentricDebug

MasterBlasterCommunications

Cable

Page 12: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

SignalTap Plus SpecificationsSignalTap Plus Specifications

All MasterBlaster capabilities All MasterBlaster capabilities Plus:Plus: 32 channel logic analyzer32 channel logic analyzer

1 external clock input1 external clock input

1 trigger output1 trigger output 1M samples per channel1M samples per channel Sample RateSample Rate

Synchronous - 166 MHz (external clock)Synchronous - 166 MHz (external clock)

Asynchronous - 166 MHz (internal clock)Asynchronous - 166 MHz (internal clock)

Page 13: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

SignalTap Plus SignalTap Plus SpecificationsSpecifications

TriggeringTriggering4 level sequence4 level sequence

Event count (1k occurrences)Event count (1k occurrences)

Pattern duration (1k clocks)Pattern duration (1k clocks)

Timeout (16M clocks)Timeout (16M clocks)

Page 14: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Industry ComparisonIndustry Comparison

Agilent (HP) LogicWave

Page 15: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

APEX 20K SameFrame Support APEX 20K SameFrame Support

196-196-Pin Pin FineLine FineLine

BGABGA

DeviceDevice

EP20K100EP20K100

EP20K200EP20K200

EP20K400EP20K400

324-324-Pin Pin FineLine FineLine

BGABGA

484-484-Pin Pin FineLine FineLine

BGABGA

672-672-Pin Pin FineLine FineLine

BGABGA

Page 16: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

APEX 20KE SameFrame APEX 20KE SameFrame SupportSupport

196-196-Pin Pin FineLinFineLine BGAe BGA

DeviceDevice

EP20K100EEP20K100E

EP20K160EEP20K160E

EP20K200EEP20K200E

EP20K300EEP20K300E

EP20K400EEP20K400E

EP20K600EEP20K600E

EP20K1000EP20K1000EE

324-324-Pin Pin FineLinFineLine BGAe BGA

400-400-Pin Pin FineLinFineLine BGAe BGA

484-484-Pin Pin FineLinFineLine BGAe BGA

672-672-Pin Pin FineLinFineLine BGAe BGA

900-900-Pin Pin FineLinFineLine BGAe BGA

Page 17: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Design Iteration SummaryDesign Iteration Summary

Verify Behavior Before CompilingVerify Behavior Before Compiling Incremental Compilation Speeds Time Incremental Compilation Speeds Time

to Marketto MarketChanges Made QuicklyChanges Made QuicklyCompilation Only Performed on Changed Compilation Only Performed on Changed

Portions of DesignPortions of DesignMore Opportunity to OptimizeMore Opportunity to Optimize

SignalTap/Plus for Real-Time Hardware SignalTap/Plus for Real-Time Hardware DebugDebug

SameFrame Pin-Out for Density, SameFrame Pin-Out for Density, Package ChangesPackage Changes

Page 18: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

SOPC Development Board SOPC Development Board OverviewOverview

Complete Hardware Platform for Complete Hardware Platform for SOPC DesignSOPC Design System resources for microprocessor, System resources for microprocessor,

memory, custom logic, & standard I/Osmemory, custom logic, & standard I/Os

Order code: SOPC-BOARD/A4EOrder code: SOPC-BOARD/A4E AAPEX 20KPEX 20K440000EE 652–1 652–1

Now ships with –1 or –2XNow ships with –1 or –2X Plan to ship with –1X when availablePlan to ship with –1X when available

Future upgradeable to 20K1500 - 652Future upgradeable to 20K1500 - 652

Shipping now!

Page 19: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Key Feature OverviewKey Feature OverviewGeneral Purpose Memory

EPC2EJTAGJTAG

MasterBlaster

Configuration

VGA LCD16 x 2 Ch

LED Switches

Display/Switches

SRAMDIMM Socket

PMCMezazanineConnector

SRAM Bank-1

256K x 32

SRAM Bank-1

256K x 32

High-speed Cache Memory

SRAM Bank-1

256K x 32

SRAM Bank-1

256K x 32

EPROMEPROM

SDRAM 4M x 64SDRAM 4M x 64

FlashFlash

Logic Analyzer

Connector Pins

Logic Analyzer

Connector Pins

General Purpose Connectors

Configuration IEEE1284

Parallel I/O

Serial I/O

USB

EthernetMII

IEEE1394A

PS2/ mouse/keybrd

RS232

Page 20: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Product Overview Product Overview

SOPC Development Board product ships SOPC Development Board product ships with:with:SOPC BoardSOPC BoardMasterBlasterMasterBlaster™™CD ROM CD ROM

User Guide User Guide Test coresTest cores 99 IP Catalog99 IP Catalog Link to web infoLink to web info

Page 21: Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration

Product Overview (continued)Product Overview (continued)

Operates with Altera and AMPP IPOperates with Altera and AMPP IP PCI development using PMC PCI development using PMC

connector onlyconnector onlyNot in PCI form factor (standalone)Not in PCI form factor (standalone)APEX PCI board scheduled for 3Q00APEX PCI board scheduled for 3Q00

Demonstration programming files Demonstration programming files (.pof)(.pof)Posted on IP MegaStore site as Posted on IP MegaStore site as

availableavailable